JPS61146019A - Signal processing method - Google Patents

Abstract

PURPOSE:To execute a data compression of a signal having a periodicity by converting a signal to the first residual signal by a linear forecasting method, calculating a difference between said signal and the first residual signal of one or plural periods before, and taking a difference of this difference signal between prescribed samples. CONSTITUTION:A signal of an input terminal T1 is brought to sampling, the first residual data D1 is obtained by a subtracter 2 and a linear forecasting circuit (LPC), and a data compression is executed. The input signal has a periodicity, therefore, the first residual data D1 also has a periodicity. Subsequently, the first residual data D1 is delayed by one period by a delay element 5, and the second residual data D2 is obtained by taking a difference between said data and the first residual data of one period before (one period is (m) samples) by a subtracter 6. In this way, the data compression is further executed. This second residual data D2 is delayed by one sample time by a delay element 8 and a difference between said data and that of one sample time before by a subtracter 9, by which a difference pulse code is modulated, and the data compression is further executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a signal processing method used when digitally processing a signal having periodicity, such as a musical tone signal.

[Prior art]

2. Description of the Related Art Techniques for sampling signals such as audio signals and musical tone signals, converting the signals into digital sampling data, and processing the data are widely used in fields such as voice synthesis, electronic musical instruments, and data communications.

[Problem that the invention seeks to solve]

By the way, the biggest problem with such data processing technology is that the amount of data becomes enormous.For example, when converting a musical tone signal from a natural instrument (such as a piano) into digital sampling data and storing it in memory, this memory capacity becomes extremely large. Therefore, various methods have been considered to compress the number of bits of sampling data, such as the DM (destructive modulation) method, ADMr adaptive demarcation JR1! l! 1) method, DPCM (differential pulse code modulation) method, etc. are known.

An object of the present invention is to provide a signal processing method that can further compress the amount of data than the above-mentioned conventional methods, especially in processing signals having periodicity such as musical tone signals.

[Means to solve the problem]

First invention: A processed signal having periodicity is converted into a first residual signal based on a linear prediction method, and the first residual signal obtained by this conversion and the first residual signal one period or a plurality of periods before A second residual signal is obtained by calculating the difference between the two residual signals, and a processed signal is obtained by calculating the difference between this second residual signal and a second residual signal obtained before a predetermined sample time.

Second invention: A processed signal having periodicity is converted into a first residual signal based on a linear prediction method, and the first residual signal obtained by this conversion and the first residual signal one period or a plurality of periods before A second residual signal is obtained by calculating the difference between the signals, and a processed signal obtained by calculating the difference between the second residual signal and the @22 residual signal before a predetermined sample time is used as the processed signal. In the signal processing method for returning,
A sum of the processed signal and a first demodulated signal before a predetermined sample time is calculated to obtain the first demodulated signal, and a sum of the first demodulated signal and a second demodulated signal one cycle or a plurality of cycles before is calculated. The calculation is performed to obtain the second demodulated signal, and the demodulation processing based on the linear prediction method is performed on the previously calculated two demodulated signals to obtain the processed signal.

Third invention: A first residual signal is obtained by calculating the difference between the processed signal and the processed signal one cycle or a plurality of cycles ago, and this first residual signal is converted into a second residual signal based on a linear prediction method. Convert to signal and convert this ff1
2 residual signal is output as a processed signal.

Fourth invention: A first residual signal is obtained by calculating the difference between the processed signal and the previous processed signal for one cycle or a plurality of cycles, and the first residual signal is subjected to transformation based on a linear prediction method. In the signal processing method for returning a processed signal obtained by The second demodulated signal is obtained by calculating the sum with the vIS2 demodulated signal from a plurality of cycles earlier, and this '@2 demodulated signal is output as the processed signal.

Fifth invention: A signal to be processed is converted into a first residual signal based on a linear prediction method, and a coefficient is obtained by multiplying this first residual signal and a first residual signal from one cycle or a plurality of cycles earlier. Calculate the difference between the signal and
This calculation result is output as a processed signal.

Sixth invention: A signal to be processed is converted into a first residual signal based on a linear prediction method, and this first residual signal and a signal obtained by multiplying a first residual signal one period or a plurality of periods ago by a coefficient. In the signal processing method for returning a processed signal obtained by calculating the difference between the processed signal and the first signal one cycle or plural cycles earlier,
The sum of the demodulated signal and the signal multiplied by the coefficient is calculated to obtain the first demodulated signal, and the first demodulated signal is subjected to demodulation processing based on the linear pre-harvesting method to obtain the processed signal.

〔Example〕

■Example of the first invention and the second invention FIG.
FIG. 1 is a block diagram showing the configuration of an embodiment of the invention. In this figure, reference numeral 1 denotes an ADC (analog/digital converter), which samples the musical tone signal G (analog signal) supplied to the input terminal T every time a certain period of time elapses.
Next, the sampled value is converted into digital sampling data SDK, and the subtracter 2 and linear prediction circuit (hereinafter referred to as LPC (L@naar Pr5diotivs)
(referred to as 'odiq)). in this case,
The number of samples of AD ("1") in one period of musical tone signal G is an insult. LP01 is a circuit that calculates a predicted value by a well-known linear prediction method. For example, the circuit shown in FIG. 2 may be used. In Fig. 2, rZ-IJ is a delay element (for example, a delay flip-flop) of one sample time.
, r M J is a multiplier, and "+" is an adder. Also,
The subscript of multiplication 5M is the multiplication coefficient (number to be multiplied). Although the circuit shown in FIG. 2 calculates the predicted value corresponding to the current sampling data from past data, it is also possible to calculate this predicted value from past and future data. However, in this case, it is necessary to insert a delay element at the position shown by the broken line in FIG. The subtracter 2 subtracts the output (predicted value) of LPC'3 from the output of ADCl, and outputs the subtraction result as first residual data D1. Here, since this first residual data D1 is the difference between the sampling data SD and the predicted value, its value is much smaller than the value of the sampling data SD, and therefore the number of pits is also small (data compression). Note that, hereinafter, the circuit composed of the above-mentioned LP01 and subtracter 2 will be referred to as LT'CC''4.

Next, the 11-cycle delayed JfI element 5 converts the first residual data D1 into one cycle period of the musical tone signal G (that is, m sample times).
This is a delay circuit, and is composed of, for example, an m-pit shift register. The subtracter 6 subtracts the output of the one-period delay element 5 from the first residual data D1, and uses this subtraction result as the second
It is output as residual data D2. Here, the musical tone signal G has periodicity, and therefore, the first residual data D1 is also data that changes at the same period as the musical tone signal G. As a result, the difference between the current value of the first residual data D1 and the value of the first residual data D1 m sample times ago (second residual data D2
) becomes a value even smaller than the value of the first residual data D1, and therefore the number of bits thereof also becomes smaller. In addition, below,
The circuit constituted by the one-period delay element 5 and the subtracter 6 described above is called P'LPC (periodio Lsn@
It is called ar Pr@diotima@Coding) 7.

Next, the delay element 8 is a circuit (for example, a delay flip-flop) that delays the second residual data D2 by one sample time.
The subtracter 9 is a circuit that subtracts the output of the delay element 8 from the second residual data D2. The circuit composed of these delay elements 8 and subtracters 9 uses the well-known differential pulse code modulation method (Diff@r@ntial Pu1
se Coae Molation ;r)Pα
), which further compresses the second residual data D2 and supplies it to the output terminal T. Note that, hereinafter, this circuit will be referred to as PCM10.

According to the configuration of the first prisoner described above, LPCC4
. Note that each of the circuits described above may be configured by an analog circuit, and the ADCI may be inserted on the output side of the subtracter 9.

With this configuration, the number of ADCI bits can be reduced. Further, the data output from the output terminal T is stored in a memory, for example, or transmitted to another location via a transmission line.

Next, FIG. 3 is a block diagram showing the configuration of an embodiment of the second invention, and the circuit shown in this diagram is a circuit that demodulates the data compressed by the circuit of FIG. 1 to the original musical tone signal GVc. It is. In FIG. 3, input terminal T is a terminal to which compressed data is sequentially supplied. Here, the order in which each data is supplied is the same as the order in which it is output from the output terminal T in Figure 1, and the time interval at which each data is supplied is the sampling interval in ADCIK in Figure 1. is the same as The circuit composed of the adder 12 and the delay element 13 is a DPCM demodulation circuit 14, and the data supplied to the input terminal T is converted into first demodulated data R1 by this DPCM demodulation circuit 14. In addition,
This first demodulated data R1 is the same data as the second residual data D2 in FIG. Next, the circuit composed of the adder 15 and the one-period delay element 16 is a PLPC demodulation circuit 17, which converts the first demodulated data R1 into second demodulated data R2Kf. This second pigeon data R2 is the first □□
This is the same data as the first residual data D1 in □.

The LPC demodulation circuit 18 converts the 2411th modulation data R2 into the third
This is a circuit for converting into demodulated data R3, and for example, the circuit shown in FIG. 4 is used.

Here, the third demodulated data R3 is the sampling data SD
This is the same data as . Then, this third demodulated data R
3 is converted into an analog signal by a DAC (digital/analog converter) 19 and output from an output terminal T. Note that the operations of each of the demodulation circuits 14, 17, and 18 described above are likely to be obvious from their respective configurations, so a description thereof will be omitted.

In addition, in the circuit shown in FIG. 1, D P C' MI
If O is connected in series in multiple stages, data compression can be further achieved. FIG. 5 shows an example of its configuration.

In this case, in the demodulation system, the DPCM demodulation circuit 1 of FIG.
Of course, the same number of DPCMIOs as the number of DPCMIOs shown in FIG. 5 are required. Also, in Figures 1 and 3, [, m
Delay elements 5 and 16 that delay the sample time are used, but instead of this, 2 m sample time (28 periods), 5
m sample time (3 cycles)...A delay element may be used. Moreover, as the delay elements 8 and 13, elements that delay 2 sample times, 3 sample times, etc. may be used.

■Example of the third invention and the fourth invention Fig. 6 is the third embodiment.
1 is a block diagram showing the configuration of an embodiment of the invention; in this embodiment, there is one input child T;

ADCI, PLPC7°LPC between output terminal 73 and output terminal 73
C4 is connected in series. Then, the sampling data SD outputted from the ADCI is processed by the PLPC7. ! ! 4 difference data DIχ, then LP
CC4￥Cyotsu'''C second residual data D11Cffi is outputted from the output terminal T. In this embodiment, already compressed data is supplied to the input terminal of the LPCC4, so the LP( The number of calculation pits in ?04 is reduced, making calculation easier.

FIG. 7 is a block diagram showing the configuration of an embodiment of the fourth invention. This embodiment is a circuit that demodulates data 1) 12 compressed by the circuit shown in FIG. 6, and a K1LPC demodulation circuit 18, a PLPC demodulation circuit 17, and a DAC1 blind are connected in series between the input terminal T and the output terminal T4. There is. Then, the data supplied to the input terminal T1 is processed by the LPC demodulation circuit 18 into @1 demodulated data R11 (data D in FIG.
ll), and then this data R11 is converted to P
It is converted into second demodulated data R12 (same as the sampling data SD in FIG. 6) by the LPC demodulation circuit 17, and
It is converted into an analog signal by the AC191C and output from the output terminal T4.

■Example of the fifth invention and the sixth invention FIG.
FIG. 1 is a block diagram showing the configuration of an embodiment of the invention. In this figure, the musical tone signal G applied to the input terminal T1 is
It is converted into digital sampling data SD by C1, then data compressed by LpCC4, and output as first residual data D21. Next, this first residual data D21 is further compressed by the modified PLPC 22 and output as second residual data D22 through the output terminal T. In this circuit, modified PLPC22
is the multiplier 2 on the input side of the one-period delay element 50 of the PLPC 7.
3 is inserted, and after the first residual data D21 is multiplied by a multiplication coefficient 1 in this multiplier 23, it is supplied to the 1 dark period delay element 5. Here, the multiplication factor is "1"
A coefficient with a value close to ``k'' and a high data compression efficiency are selected. The reason for multiplying the first residual data D21 by the multiplication coefficient A is as follows. For example, if the first residual data D21 increases at a constant rate of increase, if the first residual data D21 is multiplied by the coefficient A corresponding to the rate of increase and then supplied to the one-cycle delay element 5, the current The difference between the first residual data D21 and the data output from the one-cycle delayed element 5 is extremely small, making it possible to further improve the data compression efficiency; therefore, the multiplication coefficient is @1 residual data It may be determined according to the rate of change of D21, and
It is desirable to change it sequentially over time. Note that the insertion position of the multiplication fis 23 may be on the output side of the one-cycle delay element 5. Furthermore, when data obtained at the output terminal T is to be stored in a memory, for example, it is necessary to store the coefficients at the same time.

FIG. 9 is a block diagram showing the configuration of an embodiment of the sixth invention, and the embodiment shown in this figure is a circuit for demodulating the data D22 compressed by the circuit of FIG. In the circuit shown in FIG. 9, data supplied to the input terminal T is converted into first demodulated data R21VCf by the modified PLPC demodulation circuit 25&C. This first demodulated data R21 is the same data as the first residual data D21 in FIG.

This modified PLPC demodulation circuit 25 includes the PLPC demodulation circuit 1
This is a circuit in which a multiplier 26 is inserted into the output side of the 1-period lag element 16 of 7 (see FIG. 3). The multiplication coefficients in the figure are multiplied and supplied to the adder 15. Next, the first demodulated data R21 output from the modified PLPC demodulation circuit 25 is converted into second demodulated data R22Vc by the LPC demodulation circuit 1B. This second demodulated data R22 is the same data as the sampling data SD in FIG. Then, this second demodulated data R22 is
It is converted into an analog signal by C19, and the output terminal T,
is output from.

■Variation of the above example Next, modifications of each of the above embodiments will be described.

■ Fig. 10 is a redrawn diagram of the circuit shown in Fig. 8 after ADC 1. In this figure, block 30 represents LPC 3 of Fig. 8, and block 31 represents the multiplier 23 of Fig. 8 and one period delay. Element 5 is shown. Also, Pl axis) -
P t (g) is a transfer function, and is expressed by the following equation.

Ps (z) =, l, a n Z″″n...
・(l)p, (m)=person z −Wt
......(2) The transfer function of the entire circuit shown in FIG. 10 is ('pt(b)) (1-P, (i
)=1-Pt (z)-Pt (m)+P, (m
)・P, (z) ・・・・・・(at=1−p
t(x)-T's(g)(t-px(x))
・---(4)=1-(Pt (m)(1-P
@ (!l))+P, (g) ・−・−(51
It is expressed by the following formula. If the above formulas (3) to (n) are faithfully converted into circuits, the circuits shown in FIG. 110) to (c) can be obtained. That is, the circuit shown in FIG. 10 is as shown in FIG. 11 (
It is equivalent to the circuits shown in (a) to (c), and therefore, the same data compression effect can be obtained even if the circuits in Figure 11 (a) to e→ are used in place of the circuit shown in Figure 10. can.

Note that the above formulas (3) to 151 are merely examples, and it goes without saying that various other expansion formulas can be considered. Further, similar modifications can be made not only to the circuit shown in FIG. 10 but also to the circuits shown in FIGS. 1 and 3, for example.

[F]) FIG. 12 is a block diagram showing a modification of the PLPC 7. In this figure, input data PDI is sequentially delayed by one-period delay elements 5-1 to 5-P, and the output of each one-period delay element 5-1 to 5-P is applied to one multiplier 33-1 to 33-P.
The coefficients b1 to bp are multiplied by 33-PK, and the respective multiplication results are added by adders 34-1, 34-2, . . . k to obtain predicted data YD. Then, the predicted data YD is subtracted from the current input data PDI, thereby obtaining compressed data PD2. In this case, the coefficient b1
~bp is a coefficient of "1" or less, and b1+b
2+...+bP=1...(6) There is a relationship. According to the configuration shown in FIG. 12, the compression efficiency can be further increased than that of the PLPC4 shown in FIG. 1 and the like. Note that FIG. 13 shows the configuration of a demodulation circuit that demodulates the compressed data PD2 to the original data PDIK.

0 FIG. 14 is a block diagram showing a modified example of DPCMIO. The DPCMIO shown in Figure 1 etc. obtains compressed data by taking the difference between the data one sample time ago and the current data, but in the circuit shown in this figure, the current data and one cycle are Compressed data is obtained by taking the difference from the previous data (m sample times ago), and this process is repeated a plurality of times to increase the compression efficiency. In addition, Fig. 15 shows the first
This demodulation circuit returns the data DD2 compressed by the circuit shown in FIG. 4 to the original data DDIVc. Note that the circuit configuration of FIG. 14 may be applied to the PLPC 7 shown in FIG. 1 and the like. In this case, the PLPC demodulation circuit 17 shown in FIG. 3 etc. shall be configured as shown in FIG. 15.

(2) FIG. 6 is a block diagram showing a modification of the PLPG7. When the input signal is a musical tone signal, its cycle actually changes due to vibrato, pitch fluctuations at the rising edge, and the like. Therefore, in order to further improve the compression efficiency, K detects the period of the input signal and performs PLPC according to this detection result.
It is desirable to change the delay time of the one-period delay element 5 of 7. Figure 16 shows a circuit constructed from the above points,
Input data F1 is compressed by I and PCO2 and then supplied to subtractor 40 and delay elements 5m, 5, and 5b, respectively. In this case, the delay element 5& is the input data m-
)-1 sample time, and the delay element 5b is a circuit that delays input data by -1 sample time.

The output of each delay element 5a, 5, 5b is then supplied to a selector 41, respectively. The selector 41 has delay elements sa and s.
, sb is selected based on the data Lk supplied to its select terminal SE, and output to the subtracter 40. The stage number control circuit 42 detects the period of the input data Fl from the change state thereof, and outputs data L for controlling the selector 41 according to the detection result.

In the above configuration, when the period of the input data F1 is m+1 sample times, the output of the delay element 5& is supplied to the subtractor 540 via the selector 4.1, and when the period of the input data F1 is m sample times. , m-1 sample times, the outputs of the delay elements 5 and 5b are supplied to the subtracter 40 via the selector 41, respectively. As a result,
Even when the cycle of the input data Fl changes, the data from the previous cycle is accurately subtracted from the current data in the subtracter 40, so that the output data F2 of the subtracter 40 can be easily compressed. data can be obtained.

In addition, when storing data F2 in a memory, for example,
At the same time, data L must also be stored in the memo IJK.

Further, instead of the configuration consisting of the delay elements sa, s, sb and the selector 41, a RAM or the like may be used. Furthermore, it would be even more effective if the number of delay elements 5a and 5.5b were increased to enable delays of m-2 sample times, m+2 sample times, and so on. Further, FIG. 17 shows the configuration of a demodulation circuit that demodulates data F2.

〔Effect of the invention〕

As explained above, according to the first to sixth inventions, when digitally processing a periodic signal, the amount of digital data to be processed (c bit number) is significantly reduced compared to the conventional method. You can get the desired effect.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the first invention, 8
2 is a block diagram showing a configuration example of the LPC 3 in FIG. 1, FIG. 3 is a block diagram showing a configuration of an embodiment of the second invention, and FIG. 4 is a block diagram showing a configuration example of the LPC demodulation circuit 18 in FIG. 3. 5 is a block diagram showing a modification of the embodiment shown in FIG. 1, FIG. 6 is a block diagram showing the configuration of the embodiment of the third invention, and FIG. 7 is a block diagram of the embodiment of the fourth invention. FIG. 8 is a block diagram showing the configuration of the embodiment of the fifth invention. FIG. 9 is a block diagram showing the configuration of the embodiment of the sixth invention. FIG. 10 is the human DCI of FIG. 8. FIG. 11 is a block diagram showing a modified example of the circuit shown in FIG. 10, and FIG. 12 is a block diagram showing a modified example of the PLPC7. 13
The diagram was compressed by the circuit of FIG. A block diagram showing the configuration of a demodulation circuit that demodulates data, FIG.
CM! A block diagram showing a modified example of O, FIG. 15 is the 14th
A block diagram showing the configuration of a demodulation circuit that demodulates data compressed by the circuit shown in the figure, Fig. 16 is a block diagram showing another modification of PLPC7, and Fig. @17 shows data compressed by the circuit shown in Fig. 16. FIG. 2 is a block diagram showing the configuration of a demodulation circuit that demodulates the . 3...Linear prediction circuit (LPC), 4...
・LPC(1゜7...PLPC%lO...
...DPCM%14...DPCM demodulation circuit, 17...P L P C'41 circuit, 18
......LPC demodulation circuit, 22...Modification P
L.P.C. 25...Modified PLPC demodulation circuit. LPG fLK river circulation example 4th diagram January 5 Roichimugi 4[3i 11 r3 Kidiro #Mika example Figure 6 Figure 4 R Rou's back box f row Figure 7 GO-□ LP (7C4 Deformed PLPC22 7 large'5 I-do) l-Kaku I left a smile on my face 11th 8th
Is A1 etc. a customer? Straight (k figure 10 figure λ10 figure deformed circle PLPC t@Italy 121 figure I; time 77ru 1 summer flil Lil road 1 figure figure 13 DPCM food shape appearance 1 figure 14 r ”Li41 ;j?rf: 1% fhlii circuit happiness 1e: demand

Claims (6)

[Claims] (1) In a signal processing method for processing a signal to be processed having periodicity, the signal to be processed is converted into a first residual signal based on a linear prediction method, and a first residual signal obtained by this conversion. and the first residual signal a period or a plurality of periods ago to obtain a second residual signal, and the difference between this second residual signal and the second residual signal a predetermined sample time ago. A signal processing method characterized in that a processed signal is obtained by calculating . (2) Convert the periodic signal to be processed into a first residual signal based on the linear prediction method, and convert the first residual signal obtained by this conversion to the first residual signal from a period or multiple periods before. A second residual signal is obtained by calculating the difference with the difference signal, and the processed signal obtained by calculating the difference between the second residual signal and the second residual signal obtained before a predetermined sample time is used as the processed signal. In the signal processing method for returning the processed signal to a processed signal, the sum of the processed signal and a first demodulated signal before a predetermined sample time is calculated to obtain the first demodulated signal, and the sum of the processed signal and a first demodulated signal before a predetermined sample time is calculated, and a second demodulated signal to obtain the second demodulated signal, and perform demodulation processing on the second demodulated signal based on the linear prediction method to obtain the processed signal. Method. (3) In a signal processing method for processing a signal to be processed that has periodicity, a difference between the signal to be processed and a signal to be processed one cycle or a plurality of cycles ago is calculated to obtain a first residual signal, and the first residual signal is A signal processing method comprising: converting a first residual signal into a second residual signal based on a linear prediction method; and outputting the second residual signal as a processed signal. (4) A first residual signal is obtained by calculating the difference between the periodic processed signal and the processed signal one cycle or multiple cycles ago, and the first residual signal is subjected to transformation based on the linear prediction method. In the signal processing method for returning the processed signal obtained by the above processing to the processed signal, the processed signal is subjected to demodulation processing based on the linear prediction method to obtain a first demodulated signal, and the first demodulated signal and A signal processing method, characterized in that the second demodulated signal is obtained by calculating a sum with a second demodulated signal from a period or a plurality of periods before, and the second demodulated signal is outputted as the signal to be processed. (5) In a signal processing method for processing a signal to be processed having periodicity, the signal to be processed is converted into a first residual signal based on a linear prediction method, and the first residual signal and one period or multiple periods are converted. A signal processing method characterized by calculating a difference between a signal obtained by multiplying a first residual signal before a cycle by a coefficient, and outputting the calculation result as a processed signal. (6) Convert the periodic signal to be processed into a first residual signal based on the linear prediction method, and multiply this first residual signal and the first residual signal from one cycle or multiple cycles ago by a coefficient. A signal processing method in which a processed signal obtained by calculating a difference between the processed signal and the processed signal is returned to the processed signal, wherein the processed signal and a signal obtained by multiplying the first demodulated signal one cycle or a plurality of cycles earlier by the coefficient. A signal processing method comprising: calculating the sum of the first demodulated signal to obtain the first demodulated signal, and performing demodulation processing based on the linear prediction method on the first demodulated signal to obtain the processed signal.