JPS61145634A - Symbol string identification device and its control system - Google Patents

Abstract

PURPOSE:To obtain a circuit system in which plural symbol strings are identified in parallel and flexible identification is attained by changing an input speed by symbol or a drive speed of a charge transfer voltage pulse in response to the allowance. CONSTITUTION:In registering a symbol string MEMO, the symbols M, E, M, O are inputted sequentially to an address decoder 101. The 1st-3rd word lines 102 are selected and driven sequentially, control signals of 1010, 0100, 1010, 0001 are outputted in parallel from four R/W circuits 104 and inputted to a logical circuit 124. When each output of the circuits 104 is logical '1', a voltage pulse phi1 is fed to a gate G1, the electric charge in capacitors C0, C2, C4, C6 is transferred respectively to capacitors C2, C4, C6, C8. When the output of the circuits 104 is logical '0', the pulse phi1 is not fed to the G1 and the electric charge is inhibited. The gate G1 forms a quantized circuit 130, and is closed when the quantity of the electric charge fed to the capacitor C8 is a threshold value or over to generate an output signal Y falling down from a +V0 to 0 volt, the Y is inputted to an encoder 140, where it is converted into a symbol string identification code.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to the configuration of an artificial intelligence system, and more specifically, to a symbol string that outputs a classification code in response to an input symbol string. It is related to an identification device @ (Year-end technology) The above symbol string identification device is used for classifying feature sequences in a slam recognition system, extracting keywords from the original text file of a sentence created with a word processor, supporting language translation, and correspondence. Conventional symbol string identification, which is used to decipher abbreviations of G and is indispensable in the formation of these intelligent information processing systems, could be achieved by setting an identification program on a microcomputer. However, this was limited to small-scale projects due to the sequential processing of the program. Furthermore, there is a drawback that the processing time is too long for flexible symbol string identification that allows variations in the constituent elements of the symbol string.

(Objective of the Invention) The present invention solves the above-mentioned deficiencies l), and its purpose is to provide a circuit system that enables parallel identification and highly flexible identification of multiple symbol strings. .

Furthermore, to be more specific, 3, it is not only possible to store and read symbol strings, but also to determine whether or not the symbol string input from the outside contains the same symbol string as the one stored in the memory device. The object of the present invention is to provide a technology for realizing a sequential logic circuit on the same chip as a memory device.

(Structure of the Invention) Therefore, according to the present invention, the following symbol string identification device is obtained. That is, the present invention provides a memory device consisting of a word line selected by inputting a symbol and a plurality of bit line groups crossing the word line, a charge transfer device in which a plurality of charge storage elements are connected in series through gates, and a charge transfer device therein. The source of the voltage pulse applied to the gate for charge transfer and whether or not the voltage pulse is applied to a plurality of gates prepared for each bit line are determined for each bit line of the memory device for each input symbol. a logic circuit controlled by an output, a charging circuit connected to an input terminal of the charge transfer device, a quantization circuit connected to an output terminal of the charge transfer device, and a plurality of quantization circuits corresponding to a plurality of bit line groups. and an encoding circuit connected to a symbol string identification device, and when registering a symbol string with a number of symbols smaller than the number of bit lines in each bit line group in the memory device, a dummy dummy is provided at the beginning of the symbol string. A control method for a symbol string identification device characterized by adding a symbol so that the charge always reaches the middle of the charge transfer device.

When the registration of the symbol string to the memory device is completed,
A control method for a symbol string identification device, and a method for controlling a standard symbol string and an input symbol string, which is characterized in that mark information instructing a group of lines is stored at the intersection with a specific word line of the memory device. A control method for a symbol string identification device, which changes the voltage of the charging circuit according to the tolerance when identifying a symbol string by allowing partial mismatch, and a standard symbol string and an input symbol string. Control of a symbol string identification device characterized by changing the input speed of the symbol string or the drive speed of the voltage pulse for charge transfer according to the degree of tolerance when making the symbol string distinguishable by allowing partial mismatches. (Example) The present invention will be described in more detail with reference to the drawings. Figure 1 is an explanatory diagram of a first embodiment of the present invention. The ORAM device 110 is divided into a RAM device 110 and a charge transfer device 120.The ORAM device 110 is divided into an address decoder 101 that accepts serially input symbol codes, a word total 102 connected to it, a bit line 103, and each bit line 103. It consists of a connected R/W (read/write) circuit 104. A control signal indicating whether or not charge transfer is to be performed on a large number of bit lines 103 that intersect with the word line 102 corresponding to the input symbol code is @l'' or @0.
This l'LAM device 110 is a semiconductor 8RAM-?DRAM-?R.
OM, F ROM or lPROM-? This can be realized using BEFROM, etc., and its storage capacity is 1M bits per chip. Therefore, even if there are 256 word lines 102, there are 4192 bit lines 103. FIG. 1 shows only an example of storing l symbol strings. When storing a large number of standard symbol strings, a large number of bits a group 105 are stored in one word line 102.
A charge transfer device 120 and a quantization circuit 130 are connected to each bit line group.

On the other hand, charge transfer (CT) device 120
is a gate G that couples the array 121 of distributed capacitors C0 to C8 between adjacent capacitors.

and G, and is realized with a simple circuit in a small area.

Two-phase voltage pulses φ1 and φ are generated by the voltage pulse generation source 124 at the gates G and G in the CT device 120.
When is applied directly to each, the charge stored in the leading capacitor co is transferred to the capacitor 〇, via the adjacent capacitors 01 to C1 one after another. Voltage pulse φ
, is not applied, capacitors C1 to C8 other than c0
The charge remains in the original capacitor and gradually attenuates through the five distributed resistors 126.

Therefore, according to the driving speed of voltage pulses φ and φ,
When a symbol is input to the RAM device 110 and the voltage pulse φ1 is controlled by the output signal of each bit line 103 of the RAM device 110, the charge of the capacitor C0 is changed to the capacitor cm s C by the sequence of outputs of the R, AM device 110. ! t C8t C4t c,
It may or may not reach the capacitor C through "tCa*Cyt".

RAM device 110 stores standard symbol strings in a symbol addressed manner. That is, the symbol code input to the address decoder 101 is associated with each word line 102, and when it is stored that the first symbol is applied to the jth symbol from the beginning of the symbol string, the symbol code input to the address decoder 101 is assigned to the first word line 102 A charge transfer control signal of @1'' is written to the intersection with the j-th bit line 103. For example, 1 for the three symbols M, E, and 0.
Corresponding the second, second and third word lines, the symbol string M
When EMO data is stored, @1'' will be written in the position indicated by the small circle in the memory matrix in Figure 1. However, @□II will be written at the intersection where there is no small circle. If the symbols M, E, M, 0 are sequentially input to the address decoder 101 after registering MEMO, the 1st, 2nd, 1st, and 3rd words @ 102 become 11. Next, it is selectively driven and connected in parallel (1°o,
l, O), (0,1,0,1), (1,0,xt O
) and (Op (L O? 1) control signals are output,
It is input to the logic circuit 124. Therefore, four R/W [
When each output of the 51 path 104 is 111, the voltage pulse φ
1 is applied to the gate GK, and the charge of the upper capacitor Co e C2, C4 @ Cs connected to the gate GK is transferred to the lower capacitor C! *Transferred to C4, C@s c, respectively, but the R/W circuit 104. ..., 1
When the output of 07 is wO', the voltage pulse φ is applied to the gate G
If a symbol string other than MFiMO is applied, the charge in capacitor C0 will not be transferred to capacitor C8, but the symbol string that matches the registered symbol string will be transferred. When MEMO is input, charge is transferred to capacitor C.

G3 connected after the capacitor C6 forms a quantization circuit 130, which closes when the magnitude of the charge transferred to the capacitor C8 is equal to or higher than the dark value.

This output signal pulse y is input to an encoder 140 and converted into a string identification code.

When a symbol string that does not match a registered standard symbol string is applied to the address decoder 101 of the RAM device 120, the third . 4th. The fifth word line 102 is selected and the first bit line 103 outputs 10'. Even if some bit lines 103 output @1' and the charge travels halfway through the capacitor array 121, when it encounters the @0' output from the bit line 103, the charge is attenuated through the distributed resistor 126. do. The time constant of decay is determined by the resistance r of the distributed resistor 126 and the capacitance C of the charge storage elements C, -C.
If the product r-C is equal to the input period of the symbol or the drive period of the voltage pulse φ1 or φ, then each time the standard symbol and the input symbol increase by one symbol, the line 103 The electric charge of the connected capacitor is attenuated to l/e, where e means the natural logarithm.

Therefore, when a symbol string including many mismatched symbols is input, the amount of charge attenuation increases in the CT device 120'. If the time constant determined by r or C is set larger than the drive cycle in advance, the amount of attenuation will be reduced. This means that the flexibility for some structures of the symbol string can be adjusted by adjusting the drive cycle. 2 is a state transition diagram of sequential logic for explaining the symbol string identification operation of FIG. 1. As an example, the case where the symbol string MEMOi is accepted is shown. That is, the state at the starting state node S is transferred to the state node S1 by inputting the symbol M, and firstly transferred to the state node S by inputting the symbol E. after that.

When symbols M and 0 are input, the state of state node s2 changes from state node 5st- to terminal state node S4.
Proceed to. On the other hand, when the symbol string MOMEO is input, the state of state node So advances through state node S, then state node S, then terminal state node S.
By refusing to proceed to , MBMO will be accepted and MOMEiO will not be accepted. The above is the sequential logic for identifying symbol strings.

Note that the transition path 210 connecting state nodes causes the state to transition only for symbols written along the path. The return path 220 means that the state of the state node connected to it does not change, but stays at that state node. The symbol M represents a symbol other than the symbol M.

The transition path 210 and return path 220 cause the state to transition along the path or stay there when the state node connected to them has a state, but when the state has not reached the state node connected to them, no state is changed. It does not produce transition or stationary effects.

Looking at the state transition diagram in Figure 2 in a general sense, in addition to the symbol and string MEMO, the symbol strings MMEPGHMMMO and MBM
All symbol strings containing extra symbols, such as BFGHO, will be accepted. However, as shown in Figure 1, capacitor C! When the charges stored in *cat C@*c, are respectively associated with the states transitioned to the state nodes all Ehl EFtS, it becomes clear that the state stagnation due to the return pass 220 cannot occur in real division without charge attenuation. Without it, the symbol string MMMEFGHMMMO or MEMEFGH
O will no longer be accepted. For example, symbol string M
This means that EMMFiQ is not accepted, but MFiMEO is accepted. others.

Symbol strings such as MMEMO and MBNMO are accepted, but 1MEMO with part missing or changed to another symbol is not accepted.For example, EMO and M B M
−? It's an MMO, but it's not accepted.

In order to accept cases where some symbols in MEMO are replaced with space symbols φ or unintelligible symbols I, the state transition diagram is rewritten as shown in Figure 3, and the memory matrix is changed to the one shown in Figure 4. In FIG. 1, the speed at which the charge is stored in the capacitor Cn changes depending on the resistor r6. time constant rowc.

When is multiplied by the symbol input period t0, after the same symbol M is input, the voltage of the capacitor C0 becomes ■ only after ? or more other symbols are input. has not been reached◎K
By making it larger than ftl, it is possible to naturally suppress excessive reactions to continuous input of the symbol M.

FIG. 5 is an explanatory diagram of another embodiment of the present invention. This figure is exactly the same as FIG. 1 when looking at one bit line group 105. Therefore, the same components as in the WJ1 diagram are given the same numbers. The difference from FIG. 1 is that there are multiple bit line groups 105, each of which has a MEMORY,
Standard symbol strings such as 5TORE and 5TORAGE are registered.

The group 105 of six pins in the RAM device 110 is useful for identifying strings with more pins than the length of the string.8 A symbol string below a character is one bit @ group 105
When storing a standard symbol string, a dummy symbol is added in front of the standard symbol string to match the length of the symbol string to the number of bit lines. It is assumed that the dummy symbol %shi1 includes all symbols. Its symbol is the gate Gtf connected to the written bit i 103, which is always on and serves to advance the charge halfway.Each bit line group 105 of the RAM device 110 in FIG. 5 has eight bit lines 103. -, and the topmost bit line group 105 is MEMORY t” @ @
It is stored in the form of MEMORY. That is, in the first and second bit lines 103, @1'' is applied to all word lines 102,
On the third and fifth bit lines 103, the word @ 102 VC"1" corresponding to the symbol M is also on the fourth. 6th. 7th
and the eighth bit line) @103, @l'' is written in the word lines 102 corresponding to the symbols E, 0, R, and Y, respectively.The second and lowest bit line group 105 is 0 each @ 8. TORE and @ 8 TORAGE
When the symbol string is input to the decoder 101 after writing a symbol string like this in which the
During the input period of symbol strings other than EMORY, the charge always reaches the capacitor corresponding to the third bit line 103. After that, when a symbol string containing MEMORY is input, its charge is controlled to be output from the fourth and subsequent bit lines 103, transferred to the capacitor corresponding to the eighth bit line 103, and output to the quantization circuit 130. Generate a voltage pulse.

When the symbol string length is longer than the number of bit lines in the bit line group 105, the standard symbol string may be broken down into symbol strings of eight characters or less and registered. Since symbol string identification is possible through a combination of the outputs of several CT devices 120, the number of bit lines 103 in each bit line group 105 may be fixed at about eight.

When registering a standard symbol string in the RAM device 110 of FIG. 5, it is necessary to check which bit line group 105 has been registered. In preparation for that case, it is wise to write mark information indicating whether or not it has been registered at the intersection of one of the bit lines in each bit line group and a specific word line. When registering, first of all, do you have a specific word? If IN is selected and a new symbol string is written to the bit line group 105 from which mark information is not read, confusion will not occur. Of course, it is always possible to specify the position of the bit line group 105 using a decoder circuit or the like and write a new symbol string thereto.

In FIG. 5, the voltage v0 supplied by the power supply 123 is designed to be adjusted to be high when the output of the encoder 140 occurs infrequently. However, the amount of charge reaching the output terminal of the CT device 120 increases and the quantization circuit 130 generates an output voltage pulse, thus causing the encoder 140 to output an identification code. As explained in FIG. 1, the charge transfer voltage pulses generated by the address decoder 101 are matched to the input speed of the symbol string applied to the coder 101.
The drive period of the voltage pulse is adjusted to be equal to y, the time constant of discharge in each charge storage element and distributed resistor in the CT device 120. The charge transferred within the CT device 120 is then l/e for the introduction of one mismatched symbol.
However, if the input symbol string and the transfer voltage pulse are applied at a pitch much shorter than the discharge time constant, the amount of attenuation of the charge when one mismatch symbol is mixed becomes small. Therefore, an identification code can be output from the encoder 140 even when a large number of unmatched symbols are included. On the other hand, if the input symbol string is applied slowly at a pitch longer than the discharge time constant, the amount of charge attenuation due to the inclusion of mismatched symbols increases, and a symbol string containing even one extra symbol will not be accepted. It disappears. In this way, by changing the printing speed of the input symbol string, it is possible to make the matching criteria easier or stricter. If the frequency of output of the identification code from the encoder 140 is too high when the matching standard is made lenient, the voltage of the power supply 123 (■). You can adjust it to a lower value. The opposite can also happen.

The input symbol string does not have to be input at a constant speed as a whole, but the speed may be changed between parts that are important for identification and parts that are not. For example, when inputting a long English word, if you can speak the first part slowly and quickly and still be understood, enter the symbol string of the English word at different speeds in the first half and second half. The first half of the standard symbol string can be faithfully matched to the first half of the English word, and the second half can be made by thinning out the second half of the English word.

In the RAM device 110 of FIG. 5, an example of registering dummy symbols in each bit line group is shown, and the dummy symbol is defined as a collection tb of all symbols, but in general, not all symbols, but standard It is also effective to omit only the symbols included in the symbol string. If such a dummy symbol is 9, @MEMO
In the case of RY, 9 is all alphabets except M, E, 0, R, and Yl.

Using this, 1 MEMORY is +! 5) 9MEMOR
It is stored in the form of a Y.

As described above, the symbol string identification device combining the RAM device 110 and the CT device 120t via the logic gate 125 can be easily implemented on a single L8I chip.
The RAM device 110 is a 5 mm square chip and has a storage capacity of more than IMb.

A symbol string consisting of a combination of 8-bit symbols is 51
◎ The CT device 120 may be a part of the COD memory, and its occupied area is negligible compared to the RAM device. When connected to the data reading terminal of the chip, it determines whether the text file contains a symbol string that matches the symbol string such as a keyword registered in the chip, depending on the reading speed of the text file. It becomes possible to do so.

Jin is useful for extracting keywords from the Sentence 7 isle and using them as search indexes for text files.

Furthermore, the chip of the symbol string identification device is also useful for identifying the meaning of sentences inputted through speech recognition, including ambiguity. First, bit line group 10 corresponding to each identification code
Register a standard sentence in step 5. Even if one chip only identifies the constituent words of the sentence, use the other chip to input the sentence as a series of word codes and use the other chip to input the sentence's identification code. It becomes possible to output.

Even if one chip can only store about 512 symbol strings, the identification process simultaneously compares the 512 symbol strings with the input symbol string, so compared to conventional sequential processing, ``Processing speed increases by 512 times. Regarding conventional sequential processing, it is possible to increase the processing speed by using multiple CPUs, but it is also possible to increase the processing speed by using multiple chips for the symbol string identification device.
It becomes possible to simultaneously compare an input symbol string with thousands of symbol strings. Therefore, the difference in processing speed between the conventional method and the present invention cannot be easily narrowed.

Such a symbol string recognition device is also useful in character recognition and image recognition. Convert sample characters and images into a string of serial feature codes (a type of text), store the string of feature codes as a standard symbol string, and store up to several hundred to several thousand pieces to find unknown characters and images. By comparing the symbol string with 1000 standard symbol strings all at once, it becomes possible to perform high-speed button recognition. ・The feature code series is of a lower level (primitive features such as edges, lines, and points). There are two types: collections of features such as squares, triangles, trapezoids, circles, ellipses, fruit shapes, and human shapes. Also useful.

(Effects of the Invention) As described above, according to the present invention, it is possible to easily eliminate defects in which the identification speed is low due to sequential processing of a symbol string identification program and defects in which errors in part of a symbol string cannot be flexibly tolerated. I know it can be solved. It can also be seen that all the components of the present invention can be implemented on one silicon chip. Therefore, it is believed that such chips will play an important role as a component of artificial intelligence systems based on the recognition of bangs.

In the above description of the embodiment, the assignment of symbols to each word line 102 is not in accordance with the standard, but is done appropriately for the convenience of the description. If it is possible to write 256 word lines, all the symbols represented by 8 bits can be assigned. Therefore, the assignment of symbols to each word line is not fixed but can be easily changed. The two-phase voltage pulses (φ1 and φ,) supplied by the voltage pulse generation source 124 transfer charges from an even-numbered capacitor to an odd-numbered capacitor one above, and from an odd-numbered capacitor to an even-numbered capacitor one above. Although it was divided into charge transfer to the capacitor, the voltage pulse may be three-phase, in which case each pin) 81
03 All you need to do is prepare three capacitors.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention, and FIG. 2 is a diagram showing a first embodiment of the present invention.
FIG. 3 is a state transition diagram of the symbol string identification order logic corresponding to the embodiment shown in FIG.
This figure shows the RAM device part of FIG. 1 which has been changed in accordance with the state transition diagram of FIG. 3, and FIG. 5 shows a second embodiment of the present invention. In the figure, 101... address decoder, 102... word line. 103...Bit line, 104...R/W circuit, 10
5...Bit line group, 11O...RAM device, 1
20... Charge transfer (CT) de/(chair, 121...
Capacitor play, 122... Gate array for charge transfer, 123... Power supply, 124... Source of two-phase voltage pulse, 125... Logic game), 126... Distributed resistor, 130 ... Quantization circuit, 140 ... Encoder mouth

Claims (6)

[Claims] (1) A memory device consisting of a word line selected by inputting a symbol and a group of bit lines crossing it, a charge transfer device having a plurality of charge storage elements connected in series via a gate, and charge transfer there. The source of the voltage pulse applied to the gate for each bit line and whether the voltage pulse is applied to a plurality of gates prepared for each bit line are determined by the output of each bit line of the memory device for each input symbol. A control logic circuit, a charging circuit connected to the input terminal of the charge transfer device, a quantization circuit connected to the output terminal of the charge transfer device, and a plurality of quantization circuits corresponding to the plurality of bit line groups. 1. A symbol string identification device comprising: (2) The plurality of charge storage elements in the charge transfer device prepared for each bit line store untransferred charges according to the drive period of the voltage pulse during a period in which the application of voltage pulses is prohibited by the output of the bit line. 2. The symbol string identification device according to claim 1, wherein the symbol string identification device is coupled to a discharge element that attenuates with substantially the same time constant. (3) A memory device consisting of a word line selected by inputting a symbol and a group of bit lines crossing the word line, a charge transfer device having a plurality of charge storage elements connected in series via a gate, and charge transfer there. The source of the voltage pulse applied to the gate for each bit line and whether the voltage pulse is applied to a plurality of gates prepared for each bit line are determined by the output of each bit line of the memory device for each input symbol. A control logic circuit, a charging circuit connected to the input terminal of the charge transfer device, a quantization circuit connected to the output terminal of the charge transfer device, and a plurality of quantization circuits corresponding to the plurality of bit line groups. A control method for a symbol string identification device comprising an encoding circuit that encodes a dummy symbol at the beginning of a symbol string when registering a symbol string with a number of symbols smaller than the number of bit lines of each bit line group in the memory device. 1. A control method for a symbol string identification device, characterized in that the charge always reaches the middle of the charge transfer device by adding . (4) A memory device consisting of a word line selected by inputting a symbol and a group of bit lines crossing it, a charge transfer device having a plurality of charge storage elements connected in series via a gate, and charge transfer there. The output of each bit line of the memory device for each input symbol determines the source of the voltage pulse applied to the gate for each bit line and whether or not the voltage pulse is applied to a plurality of gates prepared for each bit line. a charging circuit connected to an input terminal of the charge transfer device, a quantization circuit connected to an output terminal of the charge transfer device, and a plurality of quantization circuits corresponding to a plurality of bit line groups. A control method for a symbol string identification device comprising an encoding circuit connected to the bit line group, wherein mark information instructing a bit line group for which registration of a symbol string to the memory device has been completed is transmitted to the memory device. A control method for a symbol string identification device characterized in that a symbol string is stored at an intersection with a specific word line. (5) A memory device consisting of a word line selected by inputting a symbol and a group of bit lines crossing the word line, a charge transfer device having a plurality of charge storage elements connected in series via a gate, and charge transfer there. The source of the voltage pulse applied to the gate for each bit line and whether the voltage pulse is applied to a plurality of gates prepared for each bit line are determined by the output of each bit line of the memory device for each input symbol. A control logic circuit, a charging circuit connected to the input terminal of the charge transfer device, a quantization circuit connected to the output terminal of the charge transfer device, and a plurality of quantization circuits corresponding to the plurality of bit line groups. 1. A control method for a symbol string identification device comprising: an encoding circuit in which a partial mismatch between a standard symbol string and an input symbol string is tolerated to identify a symbol string; A control method for a symbol string identification device characterized by changing the voltage of the circuit. (6) A memory device consisting of a word line selected by inputting a symbol and a group of bit lines crossing it, a charge transfer device having a plurality of charge storage elements connected in series via a gate, and charge transfer there. The source of the voltage pulse applied to the gate for each bit line and whether the voltage pulse is applied to a plurality of gates prepared for each bit line are determined by the output of each bit line of the memory device for each input symbol. A control logic circuit, a charging circuit connected to the input terminal of the charge transfer device, a quantization circuit connected to the output terminal of the charge transfer device, and a plurality of quantization circuits corresponding to the plurality of bit line groups. This is a control method for a symbol string identification device equipped with an encoding circuit that allows a partial mismatch between a standard symbol string and an input symbol string to make the symbol string distinguishable. A control method for a symbol string identification device characterized by changing the input speed of a symbol string or the driving speed of a voltage pulse for charge transfer.