JPS61139133A - Pcm signal multiplexing system - Google Patents

Abstract

PURPOSE:To obtain a bit unit method adaptable to the change with time of the phase difference between input data by multiplexing PCM signals of N- number of systems after the PCM signal of each system is delayed by a prescribed time if the delay time difference between a reference OPCM signal and the PCM signal of the system is not within an allowable delay time difference range. CONSTITUTION:Phase relations between two data strings De and D0 are detected by inputting clock pulse trains Ce and C0 to a phase discriminator 10 capable of operating in a high speed. One data string D0 out of two data strings De and D0 is branched into two, and one is delayed in a delay circuit 11 by T/2 (T is the bit cycle of the PCM signal) to obtain a data string D0pi, and this obtained data string is inputted to a 2X1 selecting switch 12 together with the original data string D0, and the data string D0 or D0pi is selected and outputted by the output of the phase discriminator 10. Since constituting elements such as the phase discriminator 10, the delay circuit 11, the selecting switch 12, etc. are operated in a high speed, high-speed data of N-number of systems where the phase difference between input data is changed with time are automatically multiplexed correctly.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a PCM signal multiplexing method in which input data is multiplexed in bit units of N systems of PCM signals.

(Prior Art) One method of effectively utilizing transmission lines such as optical fiber submarine cables and intermediate repeaters to reduce the cost per line is to multiplex and transmit communication information. There are various methods for multiplexing information, but among them, time division multiplexing is the most representative one, and PCM
It is an unreliable technology for transmission. This time-division multiplexing can be roughly divided into a word-based multiplexing method and a bit-based multiplexing method. Word-by-word multiplexing is usually used at coding terminal stations, while bit-by-bit multiplexing is useful for high-order multiplexing because it is sufficient to simply arrange the low-order pulse sequences sequentially in a time-division manner. It is used in oxidation equipment.

FIG. 1 shows a conventional example of a multiplexing circuit for multiplexing two systems of PCM signals whose bit repetition frequencies are synchronized bit by bit. In the same figure, three transistor pairs (
Tr+, Tr2), (Trs, Tr+) and (T
rl T'r6 ) constitutes a current switching type logic circuit, and signals having a negative relationship with each other are applied to the two bases of each transistor pair.

Now, data NRZ pulse trains De and Do with a bit repetition period T are used as the multiplexed data signal, and a rectangular wave pulse train C with a repetition period T and a pulse occupancy rate of 50% is used as a clock signal in a synchronous relationship with the multiplexed data signal. think of. These data pulse trains De and Do and the negation (inversion of "1" and "0°') signals of the clock signal C are respectively designated as De and D6.C, and these six signals are connected to each transistor as shown in Fig. 1. By inputting to the base, the output terminal OUT,.

A bit-wise multiplexed signal pulse train is obtained from 0UT2. FIG. 2 shows the phase relationship between each input signal at this time. (1) and (4) in the figure are data strings De, respectively.

This is an eye pattern display of Do. In the figure, between the data string and the clock (De and C, Do and C), T/
A delay time difference of 4 is given, and the delay is adjusted in advance so that the period of "0'° of the clock signal is approximately at the center of the corresponding Data. Therefore, in this case, the delay time difference between the two input data strings De and Do is δ. There is a delay time difference of = T/2.Now, when the clock signal C is II, during the period 1), Tr in Fig. 1 is in the OFF state, Tr'a is in the ON state, and De and De are in the output state. does not contribute to the output terminal OUT
,,0UT2 has data D, respectively. , Do is inverted.

, Do. On the other hand, clock signal C is NO
On the other hand, during the period ``, Tr is ON and T.

becomes OFF state. , Do do not contribute to the output, and the output terminals OUT, , 0UT2 have data De, De, respectively.
is inverted and output as De and De. Therefore, the output waveforms Dm, D'm from the output terminals OUT, 0UT2
As shown in FIG. 2 (51, (6)), waveforms appear.

By the way, between the data strings De and Do in FIG. 2, δ=T
The explanation has been given using an example in which a delay time difference of /2 is set in advance, but there are certain constraints on the delay time difference δ between De and Do in order to correctly execute multiplexing. Now, the phase relationship between the data string De and the black signal C is shown in Figure 2 (1), +2
Assuming the state shown in i, in order to perform multiplexing correctly, the delay time difference δ between the data sequences De and Do must be
must satisfy the relationship T/4 x δ<3T/4. FIG. 3 shows an example where this relationship is not satisfied. (1) in the figure.

(2) shows the data strings De and Do, respectively, where Do is D
The case where there is a time delay of δ=09T with respect to e is shown. The output waveform D'm from the output terminal 0UT2 when multiplexing is performed using the circuit shown in FIG. 1 is shown in FIG. 3 (5).

As shown in the figure, the data string De is output correctly, but the data string De is output correctly. It can be seen that depending on the code pattern, the output is not correct depending on the code pattern.

Therefore, in the multiplexing circuit, the multiplexed data string De.

The phase relationship between Do must be adjusted to satisfy specific conditions depending on the multiplexing circuit. For example, in the circuit configuration of FIG. 1, the conditions are T/4 x δ x 3T/4.

FIG. 4 shows an example of a conventional device for adjusting the phase relationship between multiplexed data strings De and Do to meet a certain specific condition. Here, De, Do are multiplexed data strings, Ce, Co
are clock pulse trains having a specific phase relationship with De and Do, respectively, and the phase difference (delay time difference) between De and D(1) can be uniquely determined by the phase difference (delay time difference) between Ce and C0. The phase difference between the multiplexed data strings De and Do is determined by detecting the phase difference between the clocks Ce and Co using a phase difference detector 1.
Based on the phase difference, the calculation circuit 2 calculates the required delay amount, and the delay circuit 3 processes the data. The multiplexing circuit 5 multiplexes De and Do to obtain a multiplexed output D+rI. Note that 4 in the figure is a negative (inversion) circuit. Further, the multiplexing circuit 5 is, for example, the one shown in FIG. Normally, the phase difference between the data De and Do is constant, and in that case, the phase difference detector 1 is detected by the oscilloscope.

The phase adjustment is performed by observing the phase difference between Ce and Co, and by using the delay circuit 3 to calculate the amount of delay calculated by the operator in the calculation circuit.

Furthermore, when attempting to multiplex data signals that have passed through different transmission lines such as optical fiber cables, the phase difference between the data signals that have passed through each transmission line changes over time due to external conditions such as temperature changes. . In this way, even if the phase difference between the data signals changes over time, the phase relationship between the data signals must be adjusted to satisfy specific conditions depending on the multiplexing circuit, as described above. For this purpose, as shown in FIG. The phase difference is detected by extracting the . In addition, by using an addition/subtraction circuit as the calculation circuit 2 and a variable delay circuit that can control the delay time using the output of the calculation circuit 2 as the delay circuit 3, the phase relationship between the two data strings is reset to a specific condition. are doing. The variable delay circuit is constructed by cascading two monostable multivibrators. The output of a monostable multivibrator is reversed by trigger input, but the reversal time depends on the circuit constant (
Since it can be arbitrarily determined by (resistance x capacitance), the circuit constant of the first stage multivibrator is controlled by the output of calculation circuit 2,
The inversion time is made equal to the required delay amount, and the next stage multivibrator is driven at the timing when this inversion returns to its original state. However, in this case, Non E3.
The e-turn Zero (NRZ) pulse train is
After the circuit for converting the etern zero (RZ) pulse train and the delay circuit 3, a circuit for restoring the RZ pulse to the NRZ pulse is inserted.

(Problems to be Solved by the Invention) By the way, the conventional circuit configuration example shown in FIG. 4 does not work for high-speed signals with short pulse repetition periods. In other words, the phase difference detector 1 and the delay circuit 3 use a multivibrator that operates using a signal obtained by differentiating the input signal as a trigger input, so the differential waveform must also be narrower for high-speed signals. Generally, a pulse signal has a finite rise time, but if you try to obtain a differential waveform with a narrow pulse width from such a waveform, the output will decrease, and the circuit will not be large enough to be used as a trigger input. It may stop working, or even if it does work, it may become unstable.Furthermore, as data speeds become faster, the amount of delay in the variable delay circuit becomes smaller, making it difficult to control it (
Ru. As described above, the conventional circuit configuration has the disadvantage that as the speed of multiplexed data increases, it becomes difficult to control the amount of delay or the circuit stops operating.

The present invention was made in view of the drawbacks of the prior art described above, and is a bit-based PCM that can be applied to high-speed input data and is adaptable even when the phase difference between the input data changes over time.
The purpose is to provide a signal multiplexing method.

(Means for Solving the Problems) A feature of the present invention is that in a PCM signal multiplexing method in which N systems of PCM signals whose bit repetition frequencies are synchronized are multiplexed bit by bit, the N systems of PCM signals are It has means for creating N systems of clock pulses from the reference PCM signal, with one system among them as a reference PCM signal, and means for determining a delay time difference between the reference PCM signal and the PCM signal of each system, If the delay time difference is outside the predetermined allowable delay time difference range, the clock pulse is applied after giving a relative delay time of T/2 (T is the bit period of the PCM signal) to the PCM signal of that system. The purpose is to multiplex N systems of PCM signals using the PCM signal.

(Example 1) FIG. 5 shows an example of the present invention. In the following description, an example will be taken in which there are two PCM signal input systems. The data strings to be multiplexed are De and Do, each of which is led from an input terminal 6.9. Also, Ce.

Co is a clock pulse train having a specific phase relationship (delay time difference relationship) with the data sequences De and Do, respectively, and each is led to an input terminal 7.8. Furthermore, the phase relationship (delay time difference relationship) between the two clock pulse trains Ce and Co is measured, and the two data trains De and D are determined.

Indirectly detecting the phase relationship between them is the same as the method described in FIG.

The phase relationship between the two data strings De and Do is determined by a clock pulse string Ce in a phase discriminator IO capable of high-speed operation.

Detect by inputting co. Also, two data strings D.
e, D(, one of the data strings is branched into two,
One side is delayed by T/2 using delay circuit 1). , and use this as the original data sequence. It is also input to the 2×1 selection switch 12 and output from the phase discrimination circuit 10. Selectively output. FIG. 6 shows a time chart showing this relationship. fl) and (3) are clocks Ce and Co, respectively.

(2+, +4) are data strings De and Do, and it is assumed that there is a delay time difference δ between the clock strings and between the data strings.

Also, data string (5) is a data string. T with delay circuit 1)
This is delayed by /2. The output of the phase discriminator 10 controls a 2×1 selection switch 12, for example, a beam in this example. By outputting π and guiding it to the multiplexing circuit 5, correctly multiplexed output (7) Dh+ can be obtained. According to the output of the phase discriminator 10, the sum of 2× is Do
This can be realized by configuring a circuit to output π when T≦δ≦+T. In this case, the phase discriminator 10 uses two clock signals Ce.

This can be realized by a gate circuit such as an AND circuit, an OR circuit, a NOR circuit, or an exclusive OR circuit that inputs co. These gate circuits are currently commercially available with waveform rise and fall times of 1) S or less, and are capable of high-speed operation. FIG. 7 shows, as an example, a phase discriminator 10 constructed using a NOR circuit.

In the figure, 10-1 is an N whose input is the clock Ce and C6.
It is an OR circuit, for example, FIG. 8 (1).

For inputs like (2), outputs like (3) are given.

When this NOR circuit output is led to the DC component extraction circuit 10-2 in FIG. 7, a DC output having the relationship shown in FIG. 8(4) with respect to the time difference δ between both clocks is obtained. After that, this output is led to the discriminator 10-3 in FIG. 7 whose threshold value is set to 1 volt (and the eighth phase relationship can be identified.Next, the 2×1 selection switch also connects the gate circuit to the discriminator 10-3 in FIG. It can be realized by combining. Figure 9 shows A as an example.
An example is shown in which a 2×1 selection switch is realized using an ND gate circuit. In the figure, 12-5.12-7 is an AND circuit, 1
2-6 is a negative circuit. The input terminal 12-1 receives the output of the phase discriminator IO, and the input terminal 12-2 receives the data D. But 12
-3 has data D. π is applied. Now, O≦δ≦
7 or +T≦δ≦T, the phase discriminator 10
”, but in this case, the AND circuit 12-5 outputs 0, and the 12-7 outputs π, so the output terminal 1
From 2-4. π is output. Also, 〒≦δ≦＋T
Now, on the other hand. is selected and output.

According to the above, the present invention provides data strings De and R.

The data sequence De whose phase is shifted (delayed) by
It can be seen that multiplexing is possible by creating π (DOπ) and selecting one of them according to the delay time difference (phase difference) between input data signals.

Further, according to the present invention, the phase discriminator 10.2×1 selection switch 12 can also be realized by a gate circuit capable of high-speed operation.
Furthermore, since the delay circuit 1) has a fixed delay amount and only requires a small delay amount for high-speed data, a short coaxial cable delay line can be used, so high-speed operation is possible.

(Embodiment 2) In the above example, the case where the number of PCM sequences to be multiplexed is N==2 has been described as an example, but the present invention is also applicable to N22. FIG. 1O shows an embodiment of the multiplexing device when N=3. Also, Fig. 1) shows an example of a multiplexing circuit (18 in Fig. 10), which is an extension of the conventional multiplexing circuit for N = 2 in Fig. 1 to the case of N = 3. It is something. now,
Figure 12 +2), (6), (8
), D2. Consider D3.

Here, the phase relationship between each data and the clock signal is, for example, a certain relationship as shown in FIG. 12 (21, (1)) or C. can be determined indirectly from the phase relationship between the corresponding clock signals, as in the previous embodiment.Therefore, the phase relationships between data D1, D2, D, and D3 are the same as those in FIG. It can be detected by the discriminator 10. Here, delay circuits 1)-1, 1)-2 are inserted on the input side of the phase discriminator, the reason for which will be explained later. .Divide each D3 into two and lead one side to the 7 delay circuit 1) to form D2□.

Input data sequence D≦ for correct multiplexing with the output of the device 10
, D'3 are also selectively output as in the first embodiment described above. The difference is that three auxiliary clock signals C:C:, which are time-shifted from the clock signal C4 by 1 (generally T/N), are newly required. Auxiliary clock signal C? , C:, C: is shown in Figure 12 (31
, (4), (as shown in 51 (, repetition period T, O
F'F period T/3 (generally Tc), ON period 2T/3
(generally (N-1)Tc), and the 10th
It is created by the auxiliary clock creation circuit 17 shown in the figure. A specific example of the circuit 17 is shown in FIG. Divide the input clock into two, lead one side to the fixed delay circuit 1)-3 to obtain the clock C1δ delayed by δ, and apply this together with 01 to the OR game 1.
-Leads to 20. FIG. 14 shows the time chart. In the same figure, (1) shows the original clock C7, and (2) shows the output C7δ of the fixed delay circuit 1)-3. At this time, the output C1' of the OR circuit 20 is as shown in (3).As is clear from the figure, the output signal C: has a repetition period T and an OFF period.In this way, the required auxiliary clock C: It can be obtained from the output terminal 21.Furthermore, if the delay amount of the fixed delay circuit 1)-4 is set to T/N, that is, T/3, the output terminal 22
．． 23 to 14 (C2''I shown in 41, (51)
C3* is obtained.

From the above, data D and its inverted signal DI + signal D≦, DI2゜D; , D; furthermore, auxiliary clock Cτr c:l C
3'' to the corresponding transistor bases of the multiplexing circuit shown in Figure 1], a multiplexed signal train as shown in Figure 12 GO) is obtained.The phase relationship of the human data is shown in Figure 12. In the example above, D2o is D', and D
D3π is selected as S and subjected to multiplexing. This selection criterion is for each two input data of the 2×1 selection switch 12,
It can be easily determined from the phase relationship between Dio, Diπ and the corresponding auxiliary clock C: (Here, when N=3, i=2.3). Here, - as an example, data "20" as DI
1 We will explain whether to select D or □.

As shown in FIG. 15 (1) and (31), data D1゜D2
It is assumed that there is a delay time difference δ1□ between them. data D2o
Regarding , let W2Og be the time difference from the 1-0 conversion point of data to the midpoint of the OFF period of auxiliary clock C;, and let W2or be the time difference from the midpoint of the OFF period of C: to the next σ conversion point of data D2o. (See Figure 15 (3)). Similarly, regarding data D2, as shown in (4)
Define W2, β, and W in the same way. Next, Min
(W2oO2W20 r) ,””n (W2 yt
l, W2 yrr) with respect to δ, 2, the first
Figure 6 is obtained. However, Min (A, B) is A
, H. From the same figure T/12
It is understood that if ≦δ1□≦7/12T, D2o should be selected; otherwise, D2□ should be selected.

Similarly, if the delay time difference δ13 between the data D and the data D is 5/12T≦δ13≦1)/12
It can be seen that in the case of T, D3o should be selected, and in other cases, D3o should be selected. The selection criteria for N22 can be obtained in the same manner. As described above, once the selection criteria are obtained, data is selectively output using the phase discriminator explained above with reference to FIG. 7; and the 2*1 selection switch explained with an example shown in FIG. be able to. In the example of Figures 7 and 9,
When the delay time difference δ between data is T/4≦δ≦3/4T,
Data row for those not affected by delays. was selected and output. Therefore, in the case of N=3 in this example, in the phase comparison between Dl and D20, a delay of τ (=τ-i) (1l-1 in Fig. 10) is added to the TT clock C1 in advance, and a delay is added to the data signal D1. By giving , the phase discriminator 10 shown in FIG. 7 can be used as is.

Next, a case where there are N systems of PCM signal input will be described.

FIG. 17 shows data D1 and auxiliary clock c, lc:+.
....

C:..., shows the time relationship of CC.

As is clear from the figure, the auxiliary clock C of data D
The time t1, which is the middle point of the OFF period in 1), is the center of the period T of the data Dl, that is, T/2, and is given by the following equation.

N+2i-2 t1=2NT(l=1,2....,[,...,N)
...(1) Fig. 18 illustrates various cases of delay time difference δl between data D1 and data Di. Dio is selected because the 1→0 conversion point of Diπ overlaps at the timing time (time ji), and conversely, in case (4), the 1-0 conversion point of Dio overlaps, so Diπ This is the case when selecting.

(3) in the figure is an intermediate state between (2) and (4), and Di
The time difference δl from the 1-0 conversion point of o to time ti and the time difference δ from time t1 to the 1-0 conversion point of Diπ.

is very close (・case, and of course 3g〉δ.

In the case of , Dio is selected, and in the opposite case, D1π is selected. Here, the value of δ1 when δe=δr is,
It is obtained from the formula (2+, (3)).

From equation (2,), +3+, if we set δg=δr, δ1)
is δ1. =i, →:1. +: Three (i=2.3...,
Alliance, ...N) ...(4). Therefore 1. 1. ≦2T+work...In (5),
Dio may be selected, and in the opposite case, D1π may be selected.

Next, (5) in the same figure is the opposite case to 13) in the same figure, and the time difference δ from time t1 until the 1-0 conversion point of Dio arrives.
p and the time difference δq from the IMO conversion point of D1π to time ti, then of course Dlo is selected when δp>δ9.

The value of δ12 when δp=δq is expressed by the equations (61, (71
More demanded.

Formula +51. From (6), δ1□ where δp=δq holds true
is δ1□=nuT++T...(8
). Therefore, δ12≧−, I T + +T −(
9), just select Dio, and in the opposite case, Diπ
Select. Note that there are cases where the values of δ1) and δ,2 are larger than the period T (δ,, δ1□>T), but δi
Considering that t and δ12 are functions of the period T,
The values of δ1 and δI2 are 0≦δ1. It is sufficient to replace it within the range of (δiz)≦T. Also, δ1)≧T or δ1
2≧T represents the start time of period T, and T is O
Conversely, since δi+≦T or δ12≦T represents the end of period T, T is used as is.

For example, N=4. If i=2 is substituted into equation (9), δ1□≧−L−Lr−14−r=T. but,
This replaces δ12≧0 as described above.

As described above, even if there are N systems of PCM signals, if the delay time δ1 satisfies conditional expressions (5) and (9) at the same time, DIo can be selected; It can be seen that when the time difference is δ1, Diπ (delayed by T/2) may be selected. Therefore, the formula (41
, (81, the delay time difference δth that becomes the threshold for Dio and Diπ selection is determined in advance, and the corrected delay amount (
In the case of N=3, the phase discriminator 10 in FIG. 7 can be used as is if the result of 1)-1.1)-2 in FIG. 10 is set to be X, +T. Can be done.

(Example 3) FIG. 19 shows another example of the present invention. In FIG. 5, since only the clock Ce is used as the clock for the multiplexing circuit, when the data De and the clock Ce disappear, the other data D is generated. cannot be output from the multiplexing circuit 5. FIG. 19 shows a configuration in which even if either the Ce or Co clock disappears, the multiplexing circuit 5 can be operated by the remaining clock and data from one can be output. Reference numeral 13 in FIG. 19 is a clock disconnection detection circuit that determines whether or not the clock Ce exists, and its output determines whether the 2×1 selection switch 1
4 and selects either input clock Ce or C8. That is, if there is no clock Ce, the clock C
By configuring it so that it outputs 6 and outputs Ce if the clock Ce exists, even if any of the clocks disappears, the remaining clock can be supplied to the multiplexing circuit and any of the remaining data can be output. be able to. Here, the clock interruption detection circuit 13 can be easily realized by, for example, dividing the clock signal into two and inputting it into a two-man AND circuit, extracting the DC component of the output, and then identifying it with an identification circuit. Further, the dual/1 selection switch 14 is the ninth
This can be realized using the circuit explained using the example shown in the figure.

(Example 4) FIG. 20 shows another example of the present invention. This basic operation is the same as the embodiment shown in FIG. 5, but more practical operation is taken into consideration.

Since the clock signal input to the phase discriminator actually contains jitter, the jitter appears as noise in the output of the DC component extraction circuit within the phase discriminator, causing the subsequent discriminator to malfunction with a certain probability. When the time relationship between the two systems of PCM signals De and Do is, for example, in the state shown in FIG. 21 (al, (bl), the multiplexing signal is shown in FIG. However, if Do is selected by mistake, multiplexing will not be possible correctly.Therefore, as shown in figure [f], a signal delayed by T/2 with respect to De is reproduced from the selection switch output. If the multiplexing circuit input is used, the above problem is solved.In addition, in Fig. 21(d), Ce and Ce of tel are the clock signal accompanying the signal De and its inverted signal.For De, T/ The output of the selection switch 12 is guided to a D-type flip-flop (D-FF) circuit n, and the clock Ce is delayed by 3T/4 as shown in Fig. m (Fig. 21). (g)). However, data selection in this case is different from that in the example shown in FIG.
4≦δ≦3T/4. The phase margin ε is obtained by choosing a block in the other case. , ε, is output. Note that δ=0. At T/2, respectively, Do
, Do7c should be selected, but if the data is selected by mistake, D-FF in Figure m.

At n, O+-+1 conversion points of the data are pulled/pulled, and an identification error occurs. However, δ=0, T/
2, the S/N of the phase discriminator's discrimination is maximum, so the probability of incorrect data selection can be ignored.

That is, although the DC component extraction circuit 10-2 in FIG. 7 can be realized by a low-pass filter, noise due to jitter can be suppressed if the cutoff frequency is selected to be sufficiently small.

On the other hand, when δ=T/4.3T/4, the DC component extraction circuit 1
The average value of the 0-2 output is set to E/4, which is equal to the threshold of the discriminator in the subsequent stage. At this time, the data selection of Do and Doπ is completely random. At this time, no matter which data is selected, there is no problem with multiplexing, but D
- When sampling Doπ with the FF22, it is necessary to avoid double reading and reading of data. FIG. 22 explains this. In the same figure, (al is the data D, and (C) is the data D.π which is delayed by T/2. Also, (dl is the clock Ce by 3T
/4 delay, and the rise time of the waveform is
It is written about various values of the delay time difference δ between two data.

(D, or 7 is sampled at the rising time shown in di. From the same figure, for example, when δ = T/4, if (al, It can be seen that reading and skipping occur.In order to avoid this, as shown in the same figure (bl),
When ≦δ≦T/2, delay Do by T and T/2
When ≦δ≦T, it is sufficient to create a waveform D' that passes Do through. To do this, as shown in Fig. The circuit may be configured to control the selection switch 12' to select the path with a delay of 0 T.

Next, when the time of OH1 conversion of the output of the phase discriminator 10 and the sampling time of the signal obtained by delaying the clock Ce by 3T/4 overlap, a discrimination error occurs at the time of sampling in the D-FF 22 in FIG. This is the phase difference discriminator 10
A signal obtained by delaying the output Ce by T/4, D-F'F2
This can be avoided by reading using 1.

Although the embodiment has been described above in consideration of the actual operation, the basic operation is the same as that of the embodiment shown in FIG.

(Effects of the Invention) As described above, according to the present invention, components such as the phase discriminator 10, the delay circuit 1), and the selection switch 12 can operate at high speed, so that the phase difference between input data changes over time. It becomes possible to automatically and correctly multiplex N systems of high-speed data. The multiplexing device according to the present invention can be used not only as a multiplexing terminal for signal transmission (but also as a signal combining device for a PCM network whose basic function is branching and combining of signals, so its effects are extremely high). It's a dog.

[Brief explanation of the drawing]

FIGS. 1 to 4 are explanatory diagrams regarding a conventional multiplexing device,
5 to 9 are explanatory diagrams in the case where there are two input data systems in an embodiment of the multiplexing device according to the present invention, and FIGS. 10 to 1
FIG. 6 shows an embodiment of the present invention in which the input data is three systems, FIGS. 17 to 18 show an embodiment of the present invention in which the input data is N systems, and FIG. 19 shows another embodiment of the present invention. FIG. 1 to FIG. 4 are diagrams showing still other embodiments of the present invention. ■...Phase difference detector, 2...Calculation circuit, 3.
...Delay circuit, 4..Negation (inversion) circuit, 5,
18... Multiplexing circuit, 6.9.15-1 to 15-
3...Data string input terminal, 7, 8.16-1 to 16
-3... Clock signal input terminal, 10... Phase discriminator, 10-1... NOR circuit, 10-2...
DC component extraction circuit, 10-3... discriminator, 1).
...Delay circuit (T/2), 1)-1...Delay circuit (,T/6), 1)-2...Delay circuit (5/6T)
, 1)-3... Fixed delay circuit (δ), 1)-4.
・Fixed delay circuit (, T/3), ■2...2×1 selection switch, 12-5.12-7...AND circuit,
12-6... Inversion circuit, 13... Clock disconnection detection circuit, 14... 2×1 selection switch, 17... Auxiliary clock generation circuit, 19... Multiplexed output terminal,
20...OR circuit.

Claims (2)

[Claims] (1) N systems with synchronized bit repetition frequency (N
is a natural number of 2 or more) in a PCM signal multiplexing method that multiplexes PCM signals bit by bit.
One of the M signals is used as a reference PCM signal, and the reference PCM signal is
means for creating N systems of clock pulses from a CM signal; and means for determining a delay time difference between the reference PCM signal and each system's PCM signal; If so, the PC of that type
A PCM signal characterized in that after giving a relative delay time of T/2 (T is a bit period of the PCM signal) to the M signal, N systems of PCM signals are multiplexed using the clock pulse. Multiplexing method. (2) For each of the N systems of PCM signals, a priority is determined to be the reference PCM signal, and
When the signal is disconnected, the reference PCM
2. The PCM signal multiplexing method according to claim 1, wherein the PCM signal multiplexing method selects a signal.