JPS61137343A - multilayer wiring - Google Patents

Abstract

PURPOSE:To obtain multilayer interconnection of high reliability by setting the selection ratio of an etching velocity for an interlayer insulating film of upside of a wiring layer to an interlayer insulating film of downside to approx. 1.5 or more. CONSTITUTION:Aluminum wirings 14 are formed through an interlayer insulating film 13 of a quartz sputter to aluminum wirings 12 on an Si substrate 11, and aluminum wirings 15 are formed through an interlayer insulating film 15. The film 15 is formed of an Si3N4 film 15a, a superposed film 15b of a glass rotatably coating film and a PSG by a plasma CVD method. In this configuration, the selection ratio of etching velocity of the film 15 to the film 13 can be set to approx. 1.5-2, and when the quantity of O2 to be added to CF4 and pressure are selected, the ratio can be readily approached to 2. Thus, even if the connecting hole 18 of the film 15 is displaced, the film 13 is not overetched, the wirings 18 are not shortcircuited with the wirings 12, the reliability is improved, wiring pitch is reduced, and an IC can be highly integrated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to multilayer interconnects for semiconductor devices and the like, and particularly to multilayer interconnects designed to prevent electrical short circuits between upper layer interconnects and lower layer interconnects.

[Actual view technology]

As shown in FIG. 3, an SiQ film (hereinafter referred to as quartz sputtered film) formed by sputter deposition is used as an interlayer insulating film for multilayer wiring in semiconductor devices, particularly large-scale integrated circuits (hereinafter referred to as LSI). ing. In the same figure,
1 is a semiconductor substrate, a first layer of AI wiring 2 is deposited on this semiconductor substrate 1, a first layer of interlayer insulating film 3 is deposited on this human wiring 2, Furthermore, the second
A layer of AI wiring 4 is deposited.
Above, a third layer of AI is placed through a second layer of interlayer insulating film 5.
A wiring 6 is deposited, and in the case of a three-layer wiring, a passivation film (not shown) is deposited thereon.

Here, as the interlayer insulating films 3 and 5 of the first layer and the second layer, χ
A quartz sputtered film is used.

However, as shown in the figure, even if the second layer A wiring 2 is well connected to the first layer AJ wiring 2 via the through hole 7, the third layer A! Wiring 6 and 21st i-th A!
Delivery #! When the etching position of the through-hole 8 for connecting with the wiring 4 is removed from the second cut A/wiring 4, as shown in the figure, there is over-etching during dry etching of the through-hole 13. Membrane 3 is etched. In this case, quartz sputtered films are used as the second interlayer insulating film 5 and the #1 #th interlayer insulating film 3, and the interlayer insulating film of the second interlayer insulating film 5 is ll
! When the etching rate selectivity to lI3 is 1, the amount of overetch when etching the interlayer insulating film 5 is 30 to 50% of the thickness of the interlayer insulating film 5 (for example, 1.5 μm).
When the distance between the first layer AI wiring 2 and the second layer AI wiring 4 is, for example, 1.5 μm or less, k corresponds to the distance between the third layer AJ wiring 6 and the first layer AI wiring 6 as shown in the figure. The distance between the eye and the AJ wiring 2 becomes smaller in the A section, and the dielectric strength voltage between the AI wiring 6 and the AI wiring 2 cannot be ensured. And A!
Wiring 6 and AI! ja! 2 will be electrically short-circuited.

Therefore, even if the position where the through hole 8 should be etched shifts, the through hole 8 will be etched! The layout rule is such that there is a margin of 2 μm as shown in FIG.

However, with such a layout rule,
This becomes an obstacle in reducing the wiring pitch.

In particular, the inability to reduce the wiring pitch is a major obstacle in achieving miniaturization and higher integration of integrated circuits.

In addition, regarding the multi-layer wiring technology, please refer to [Sem1 con-
ductor World J Press Journal Co., Ltd., 1
It is described in October 1984 issue, pages 116-137.

[Object of the Invention] An object of the present invention is that even if the position of a connection hole for connecting an upper layer wiring to a lower layer wiring deviates from a predetermined position on the lower layer wiring, the upper layer wiring can be connected to the lower layer wiring. It is an object of the present invention to provide a multilayer wiring which prevents electrical short-circuiting with other lower-layer wiring that should not be connected through the connection hole, and improves the reliability of the wiring.

Another object of the present invention is to provide a multilayer wiring that can relax the layout rules for connection holes for connecting upper-layer wiring to lower-layer wiring and the lower-layer wiring, and reduce the wiring pitch. Our goal is to provide the following.

Another object of the present invention is to provide a multilayer wiring that can reduce chip size and significantly reduce costs in the case of integrated circuits such as LSIs.

Another object of the present invention is to provide a multilayer wiring that enables miniaturization and high integration in integrated circuits such as LSIs.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, in a multilayer wiring structure in which an interlayer insulating film is interposed between the wirings, and the upper layer wiring and the lower layer wiring are connected via a through hole, the upper layer wiring and the lower layer wiring The interlayer insulation I11 under the lower wiring of the interlayer insulation film between them! In order to obtain a large etching rate selectivity (for example, at least approximately 1.5 or more), a phosphorous silicate glass film and a plasma CVD (Chemical Vapor
By using a stacked film in which a spin-on glass film is interposed between silicon nitride films by the ur deposition method, and by using a quartz sputtered film as the latter interlayer insulating film, the etching position of the through hole can be adjusted to the If the through hole deviates from the position according to the predetermined layout rule on the lower layer wiring, the interlayer insulating film under the lower layer wiring is hardly etched during etching of the through hole. There is no electrical short circuit between the through hole and the lower layer wiring, which should not occur, and the reliability of the wiring (for example, LSI arrangement 11) can be improved, and the layout rules for the through hole and the lower layer wiring can be improved. It is possible to reduce the wiring pitch. Particularly in the case of LSIs, the chip size can be reduced by reducing the wiring width and, therefore, the wiring pitch, thereby making it possible to achieve significant cost reductions, miniaturization, and high integration. be.

〔Example〕

FIG. 1 shows an embodiment of multilayer wiring according to the present invention, and particularly shows a case where the invention is applied to multilayer wiring of LSI. below,
The present invention will be explained using FIGS. 1 and 2.

In FIG. 1, a first layer of human wiring 12 is deposited on a semiconductor substrate 11, and a first layer of interlayer insulating film 13 made of a quartz sputtered film is deposited on this AJ wiring 112.
Furthermore, a second layer A! is formed on this interlayer insulating film 13. Placement 111
4 is deposited. A second layer interlayer insulating film 15 is deposited on this AJ wiring 14 at a temperature of 15°C. This second interlayer insulating film 15 consists of a silicon nitride film 15a formed by plasma CVD and a spin-on glass (SO2) film formed thereon.
G) A layered film 15b formed by integrating a film and a phosphorous silicate glass (psG) film formed on the SOG film. Here, as the interlayer insulating film 15, a silicon nitride film 15a formed by plasma CVD is used as the lower layer, and P is used as the upper layer.
Although the SG film 15b is used, the lower layer KPSG film is used,
A silicon nitride film formed by plasma CVD may be used as the upper layer. Therefore, the interlayer insulating film 15 may be one in which a spin-on glass film is interposed between a silicon nitride film and a PSG film formed by plasma CVD. The etching rate selection ratio of such an interlayer insulating film 15 to the interlayer insulating film 13 made of a quartz sputtered film can be approximately 1.5 to 2. By changing the amount and pressure of oxygen (0,) added to CF or CHF used as the etching gas, the selection ratio can be easily made close to 2.

Furthermore, a third layer of Al wiring 16 is deposited on the interlayer insulating film 15, and in the case of a three-layer wiring, a passivation film is deposited on this, although not shown. The A) wire @14 in the second layer is connected to the Al wiring 12 in the first layer via a through hole 170 formed in the interlayer insulating film 13 in the first layer. Further, the third layer Al wiring 16 is connected to the second layer Al wiring 14 to be connected via a through hole 18 opened in the second layer interlayer insulating film 15.

Here, the through hole 18 is formed on the AJ layout @ 14, but due to mask alignment errors, the position where the through hole 18 is formed is on the AI to be connected as shown in the figure.
Even if it deviates from the predetermined position on the wiring 14, the selectivity of the dry etching rate of the second layer interlayer insulating film 15 with respect to the first layer interlayer insulating film 13 under the second layer KL wiring 14 is determined as described above. As you can see, it can be made close to 2, so
Due to overetching, the first layer of interlayer insulation Igl! 13 is hardly etched. Therefore, as described in the background art, the third layer Al wiring 1tJ16 is not electrically short-circuited with the first layer AI wiring 12, which is not the wiring to be connected, and the LS
The reliability of I wiring is improved. It is most preferable that the selection ratio is approximately 2 or more, but if it is at least approximately 1.5 or more, even if overetching is performed, the overetching weight will be slight and the dielectric strength voltage between the Al wiring 16 and the AJ wiring 12 cannot be ensured.・The electrodes are not etched, and by changing the pressure during etching and the amount of oxygen added (0,), the selection ratio can be easily made close to 2 (2), and the electrical short circuit can be reduced. In this way, even if the through hole 18 is removed from the A7 wiring 14, there will be no electrical short circuit with other lower layer wiring that should not be connected, so there is no need to worry about the It is no longer necessary to provide a 2 μm margin for the layout rule of the hole 18 as in the past (see Figure 4), and a 1 μm margin is sufficient as shown in Figure 2.Moreover, through-hole 1
8 is shifted by 1/3 to 1/2 from the AI wiring 14, the third layer A wiring M16 and the second layer Il wiring 14 can be electrically connected sufficiently, and the Interlayer insulation film 13
Since it is hardly etched, no problem occurs. Therefore, the layout rules for the through holes 18 and the AI wiring 14 can be relaxed, and the wiring pitch can be reduced from the conventional 8 μm, for example.
The thickness can be reduced from 6 μm (see FIG. 4) to 6 μm (see FIG. 2), thereby reducing the LSI chip size and significantly reducing costs. Furthermore, it is possible to cope with miniaturization and high integration of LSI.

(1) Even if the position of a connection hole (through hole, etc.) for connecting the upper layer wiring to the lower layer wiring deviates from a predetermined position on the lower layer wiring, the interlayer insulating film under the lower layer wiring Since the upper layer wiring is hardly etched, it is possible to prevent an electrical short circuit between the upper layer wiring and the lower layer wiring that should not be connected through the connection hole, thereby improving the reliability of the wiring. Improvements can be made.

(2) According to 1 above, the upper layer wiring is connected to the lower layer wiring alc.
Since the position of the connection hole for connection may be partially off from above the lower layer wiring, a sufficient margin should be provided in the width of the lower 1 side wiring so that the connection hole does not come off from above the lower layer wiring. It is no longer necessary to hold the connection hole and the lower layer wiring, and the layout rules for the connection hole and the lower layer wiring can be relaxed, and the wiring pitch can be reduced.

(3) Since the wiring pitch can be reduced compared to the above-mentioned 21C, in the case of integrated circuits such as LSI, the chip size can be reduced and costs can be significantly reduced.

(From 41 onwards, miniaturization in integrated circuits such as LSI,
It can contribute to high integration.

Above, the invention made by the present inventor has been specifically explained based on the examples, but it should be noted that the present invention is not limited to the above examples and can be modified in various ways without departing from the gist thereof. Not even. For example, in FIG. 3, the second interlayer insulating film 15 is a layered film in which an SOG film is interposed between a silicon nitride film and a PSG film formed by plasma CVD, but A stacked film formed by interposing an SOG film between a silicon nitride film and a Sho film produced by plasma CVD (in this case, either the silicon nitride film or the SiQ film may be the lower layer or the upper layer; in short, the SOG film The IC8OG film may be interposed between the PSG film and the SiQ film formed by plasma CVD (in this case, the film may be formed between the PSG film and the SiO film). , which may be the lower layer or the upper layer, as long as the SOG film is formed in the middle) may be used, and furthermore, only the PSG film or the Siσ film formed by plasma CVD may be used alone. In this case, the etching rate selectivity of dry etching of P S Ga (second interlayer insulating film) to the quartz sputtered film (first interlayer insulating film) is 1.
5th place, selection of etching speed of dry etching for SiQ film and quartz sputtered film (first interlayer insulating film) K of each layered film (second interlayer insulating film) by other plasma CVD methods. The ratio can be set at 1.5 to 2, and when the etching gas is, for example, CF or CHF, the selectivity can be set at 2 by changing the pressure and the amount of oxygen (02). If the selection ratio is 2nd, the first interlayer insulating film 13 will hardly be etched even if overetched, but if it is at least approximately 1.5 or higher, the amount of overetching will be extremely small, AA! A sufficient dielectric strength voltage between the wiring 16 and the wire 2 can be ensured, and the problem of electrical short circuit does not occur, and the same effects as in the present embodiment are achieved.

[Application field]

The above explanation mainly describes the invention made by the present inventor, which is the field of application for which the invention was made,
Although the case where it is applied to SI semiconductor devices has been described, it is not limited thereto, and can be applied to integrated circuit devices using multilayer wiring, general semiconductor devices in general, and even general multilayer wiring. .

[Brief explanation of the drawing]

FIG. 1 is a sectional view of essential parts showing an embodiment of multilayer wiring according to the present invention, FIG. 2 is a schematic diagram showing a layout rule according to the present invention taken corresponding to FIG. 1, and FIG. 3 is a cross-sectional view of the present invention. FIG. 4 is a simplified diagram showing a layout rule to be adopted corresponding to FIG. 3. 11... Semiconductor substrate, 12... First layer AI wiring, 13... First layer interlayer insulating film (quartz sputtered film)
, 14... Second layer AI wiring, 15... Second layer interlayer insulating film (silicon nitride film 1 by plasma CVD method)
5a and PSG film with SOG interposed between them)
, 15a... silicon nitride film by plasma CVD method,
15b...Layered film with KPSG formed on SOG, 16
...3rd layer AI wiring, 17.18... through hole. Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Scope of Claims] 1. In a multilayer wiring structure formed by multilayer wiring with an interlayer insulating film interposed between the wirings, and in which the upper layer wiring and the lower layer wiring are connected through connection holes, the upper layer side The insulating materials forming the respective interlayer insulating films are selected so as to have a high etching rate selectivity of the interlayer insulating film between the wiring and the lower wiring with respect to the interlayer insulating film under the lower wiring. Multilayer wiring featuring 2. The multilayer wiring according to claim 1, wherein the selection ratio is at least approximately 1.5 or more. 3. As an interlayer insulating film between the upper layer side wiring and the lower layer side wiring, a stacked film in which a spin-on glass film is interposed between a phosphorus silicate glass film and a silicon nitride film formed by plasma CVD method is used, and the lower layer side 3. The multilayer wiring according to claim 1, wherein a silicon dioxide film formed by sputter deposition is used as an interlayer insulating film under the wiring. 4. As an interlayer insulating film between the upper wiring and the lower wiring, a stacked film is used in which a spin-on glass film is interposed between a silicon monoxide film formed by plasma CVD and a silicon nitride film formed by plasma CVD. 3. The multilayer wiring according to claim 1 or 2, wherein a silicon dioxide film formed by sputter deposition is used as an interlayer insulating film under the lower wiring. 5. A silicon monoxide film formed by plasma CVD is used as an interlayer insulating film between the upper wiring and the lower wiring, and a silicon dioxide film formed by sputter deposition is used as an interlayer insulating film under the lower wiring. A multilayer wiring according to claim 1 or 2, characterized in that: