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JPS61136290A - Repair for multilayer printed wiring board - Google Patents

Repair for multilayer printed wiring board

Info

Publication number
JPS61136290A
JPS61136290A JP25870884A JP25870884A JPS61136290A JP S61136290 A JPS61136290 A JP S61136290A JP 25870884 A JP25870884 A JP 25870884A JP 25870884 A JP25870884 A JP 25870884A JP S61136290 A JPS61136290 A JP S61136290A
Authority
JP
Japan
Prior art keywords
hole
printed wiring
multilayer printed
wiring board
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25870884A
Other languages
Japanese (ja)
Inventor
新 隆士
大貫 秀文
浅野 智明
鳥山 孝三
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP25870884A priority Critical patent/JPS61136290A/en
Publication of JPS61136290A publication Critical patent/JPS61136290A/en
Pending legal-status Critical Current

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は多層印刷配線板の修復方法に関し、特にスルホ
ール導体層と内層パターンの短絡不良の修復方法に関す
る1、 〔従来の技術〕 近年、成子デバイスの高集積化に伴い、印刷配線板に対
する高密度化要求が顕著になっている。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a method for repairing a multilayer printed wiring board, and in particular to a method for repairing a short-circuit defect between a through-hole conductor layer and an inner layer pattern. 2. Description of the Related Art As devices become more highly integrated, there is a growing demand for higher density printed wiring boards.

このため多層印刷配線板が多用されてきている。For this reason, multilayer printed wiring boards have come into widespread use.

従来、多層印刷配線板の一般的な製造方法では、まず、
鋼張積層板の銅層に内層パターンとしての信号パターン
あるいは電源グランドパターンを印刷・エツチング工程
により形成して、内層基板を製作する。次いで内層基板
と片面の銅張積層板を外層基板としてグリプレグと重ね
合わせ加熱加圧して一体化成形する。
Conventionally, in the general manufacturing method of multilayer printed wiring boards, first,
An inner layer board is manufactured by forming a signal pattern or a power ground pattern as an inner layer pattern on the copper layer of a steel clad laminate by a printing/etching process. Next, the inner layer substrate and the single-sided copper-clad laminate are used as an outer layer substrate and are superimposed on Gripreg and heated and pressed to form an integral molding.

次に貫通孔を穿設した後、電気めりきによや貫通孔内壁
を含む全面に導体層を形成、更に外層パターンを印刷・
エツチング工程により形成して多層印刷配線板を製作し
ている。
Next, after drilling a through hole, a conductive layer is formed on the entire surface including the inner wall of the through hole using electroplating, and an outer layer pattern is printed/printed.
A multilayer printed wiring board is manufactured by forming it using an etching process.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかしながら、上述の従来の多層印刷配線板の内層基板
製作には次のような問題点がある。
However, the manufacturing of the inner layer substrate of the conventional multilayer printed wiring board described above has the following problems.

すなわち、鋼張積層板の鋼層を印刷・エツチング工程に
より内層パターンを形成する際、エツチングレジストの
残渣等によりエツチングされるべき鋼層部分に局部的な
非エツチング部(以後エツチング残りと呼ぶ)が発生す
る場合があり、そのitの状態で多層印刷配線板を製作
したときには、スルホール導体層と内層基板のエツチン
グ残抄が接触して短絡不良となる場合がある。このため
、内層基板製作都階での検査が重要になるが、この検査
に一般には目視検査しかなく、完全にエツチング残りを
検出することは難しく、ある程度の見逃しはさけられな
かった。また多層印刷配線板製造後にスルホール導体層
と内層パターンの短絡不良は、その不良発生箇所が判明
しても内層位置であるがため修復は不可能とされ廃棄さ
れている。
That is, when an inner layer pattern is formed on the steel layer of a steel clad laminate by a printing/etching process, local non-etched areas (hereinafter referred to as etching residues) may occur in the steel layer parts that should be etched due to etching resist residue, etc. When a multilayer printed wiring board is manufactured in that state, the through-hole conductor layer and the etching residue of the inner layer board may come into contact, resulting in a short circuit failure. For this reason, inspection at the production stage of the inner layer substrate is important, but this inspection generally involves only visual inspection, and it is difficult to completely detect etching residues, so some oversights are inevitable. Furthermore, even if the defective short-circuit between the through-hole conductor layer and the inner layer pattern is found after the multilayer printed wiring board is manufactured, it is impossible to repair the defect because it is located in the inner layer, and the board is discarded.

特に、最近の多層印刷配線板の高多層化要求に対してこ
の短絡不良は重要な問題点となってきている。
In particular, this short-circuit failure has become an important problem in response to the recent demand for a higher number of layers in multilayer printed wiring boards.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の目的は、このような従来の問題点であるスルホ
ール導体層と内層パターンとの短絡不良を解決する多層
印刷配線板の修復方法を提供することKある。
An object of the present invention is to provide a method for repairing a multilayer printed wiring board that solves the conventional problem of short-circuiting between the through-hole conductor layer and the inner layer pattern.

すなわち、本発明によれば短絡不良のスルホール孔をス
ルホール孔より大なる径を有し、かつ正常位置の内層パ
ターンが露出しない範囲の外径を有するドリルで第1の
貫通孔を穿設する工程と、上記第1の貫通孔内に熱硬化
性樹脂を充填して加熱硬化する工程と、上記熱硬化性樹
脂の充填孔に初めのスルホール孔と同一径のドリルで第
2の貫通孔を穿設する工程と、上記第2の貫通孔の内壁
および表裏ランドを除いて無電解めっき用レジスト被膜
を形成する工程と、上記無電解めっき用レジスト被膜を
形成した多層印刷配線板全体に無電解めりき用触媒層を
形成する工程と、上記表面の無電解めりき用触媒層を除
去した後、第2の貫通孔内壁および表裏ランドに無電解
めっきにより導体層を形成する工程と、上記無電解めっ
き用レジスト被膜を溶解除去する工程とからなることを
特徴とする多層印刷配線板の修復方法が得られる。
That is, according to the present invention, the step of drilling a first through-hole in a through-hole having a short-circuit defect with a drill having a diameter larger than that of the through-hole and having an outer diameter within a range that does not expose the inner layer pattern in the normal position. a step of filling the first through hole with a thermosetting resin and curing it by heating; and drilling a second through hole in the thermosetting resin filling hole with a drill having the same diameter as the first through hole. forming a resist film for electroless plating except for the inner wall of the second through hole and the front and back lands; and applying electroless plating to the entire multilayer printed wiring board on which the resist film for electroless plating has been formed. a step of forming a catalyst layer for electroless plating, and a step of forming a conductor layer by electroless plating on the inner wall of the second through hole and the front and back lands after removing the catalyst layer for electroless plating on the surface, and A method for repairing a multilayer printed wiring board is obtained, which comprises a step of dissolving and removing a plating resist film.

〔実施例〕〔Example〕

以下、本発明の実施例を4層構成の多層印刷配線板によ
り図面を参照して説明する。
Hereinafter, embodiments of the present invention will be described using a four-layer multilayer printed wiring board with reference to the drawings.

第1図(A)はスルホール導体層と内層パターンの短絡
不良適所を示す4層構成の多層印刷配線板の断面図であ
り、ガラス繊維入りエポキシ樹脂等の絶縁板1の内部に
、2層パターンとして電源層2および3層パターンとじ
てグランド層3を有し、絶縁板10表裏面のパターン4
,5を鋼めっき等によるスルホール導体層6で接続して
いる。
FIG. 1(A) is a cross-sectional view of a multilayer printed wiring board with a four-layer structure showing short-circuit defects between the through-hole conductor layer and the inner layer pattern. It has a power layer 2 and a ground layer 3 as well as a three-layer pattern, and a pattern 4 on the front and back surfaces of the insulating plate 10.
, 5 are connected by a through-hole conductor layer 6 made of steel plating or the like.

この場合のスルホール導体層6は本来、内層の電源層2
およびグランド層3には接続しない箇所のスルホールで
あるが、グランド層3のエツチング残り7により内層パ
ター/のグランド層3と短絡してしまりている。
In this case, the through-hole conductor layer 6 is originally the inner layer power supply layer 2.
Although the through hole is not connected to the ground layer 3, it is short-circuited with the ground layer 3 of the inner layer pattern due to the etching residue 7 of the ground layer 3.

この状態を第1図(A)のA −A’  線上で輪切り
にした平断面図を第1図(B)に示すと、スルホール導
体層6に対するグランド層3の円形の逃げパターン(以
後クリアンスと呼ぶ)内のエツチング残り7によりグラ
ンド層3とスルホール導体層6が短絡している。このよ
うな短絡部分を有する多層印刷配線板を、まず第1図(
C)に示すように、スルホ、−ル導体層6の外径より大
で、かつグランド層3のクリアランスの径より小さい直
径のドリルによりスルホール導体層6を再び孔あけしス
ルホール導体層6とスルホール導体層6に沿った絶縁板
1の一部を除去した貫通孔8をあける。
FIG. 1(B) is a plan cross-sectional view of this state taken along the line A-A' in FIG. 1(A). The ground layer 3 and the through-hole conductor layer 6 are short-circuited due to the etching residue 7 in the inner layer 7. First, a multilayer printed wiring board having such a short-circuited portion is constructed as shown in Figure 1 (
As shown in C), the through-hole conductor layer 6 is re-drilled using a drill whose diameter is larger than the outer diameter of the through-hole conductor layer 6 and smaller than the clearance diameter of the ground layer 3. A through hole 8 is formed by removing a portion of the insulating plate 1 along the conductor layer 6.

次に貫通孔8内にエポキシ樹脂等の絶縁性および耐熱性
を有する熱硬化性樹脂9を充填し温度80〜150℃で
30〜90分加熱硬化する(第1図(D))。
Next, a thermosetting resin 9 having insulation and heat resistance, such as epoxy resin, is filled into the through hole 8 and cured by heating at a temperature of 80 to 150° C. for 30 to 90 minutes (FIG. 1(D)).

次いで、第1図(E) K示すように熱硬化性樹脂9を
充填した貫通孔8に初めのスルホール導体層6の内径と
同一の径のドリルにより再び貫通孔10をあけ内壁に熱
硬化性樹脂9の被膜を残す。
Next, as shown in FIG. 1(E)K, a through hole 10 is made again in the through hole 8 filled with thermosetting resin 9 using a drill having the same diameter as the inner diameter of the first through-hole conductor layer 6, and the inner wall is filled with thermosetting resin. A film of resin 9 is left.

次に例えばデュポン製バークレル168などのドライフ
ィルムタイプの無電解めっき用レジストをラミネート・
露光・現偉の工程で順次処理し絶縁板1表裏面のパター
ン4.5がランド状に露出するよう逆ランド状に逃げを
設けて無電解めりき用レジスト被膜11を形成する(第
1図(F))。
Next, a dry film type electroless plating resist such as DuPont Berkrel 168 is laminated.
The resist film 11 for electroless plating is formed by providing relief in the form of a reverse land so that the pattern 4.5 on the front and back surfaces of the insulating plate 1 is exposed in the form of a land through successive processes of exposure and development (Fig. 1). (F)).

次に貫通孔10を導体化するために多層印刷配線板全体
を鋼金属コロイド水溶液などの非金属コロイド水溶液の
無電解めっき触媒水溶液に浸漬して、貫通孔10の内壁
を含む全面を触媒活性化する無電解めりき用触媒層12
を形成する(第1図(G))。
Next, in order to make the through holes 10 conductive, the entire multilayer printed wiring board is immersed in an electroless plating catalyst aqueous solution of a non-metal colloid aqueous solution such as a steel metal colloid aqueous solution, and the entire surface including the inner wall of the through hole 10 is catalytically activated. Catalyst layer 12 for electroless plating
(Fig. 1 (G)).

次いで、表面をスポンジ等を用いて水洗研磨し表面の無
電解めっき用触媒層12を除去して、無電解めっき用触
媒層12を貫通孔10の内壁の熱硬化化性樹脂9のみに
残存させる(8g1図(H))。
Next, the surface is washed and polished using a sponge or the like to remove the catalyst layer 12 for electroless plating on the surface, so that the catalyst layer 12 for electroless plating remains only on the thermosetting resin 9 on the inner wall of the through hole 10. (Figure 8g1 (H)).

次に、液温的70℃の無電解鋼めっき液に浸漬して、貫
通孔10の内壁および表面に露出した導体層6aのみに
無vt解銅めっき導体層を形成し初めのスルホール導体
層6と同様にスルホール導体層13を復元形成する(第
1図(1))。
Next, the through-hole conductor layer 6 is immersed in an electroless steel plating solution at a liquid temperature of 70° C. to form a VT-free copper plating conductor layer only on the inner wall of the through hole 10 and the conductor layer 6a exposed on the surface. Similarly, the through-hole conductor layer 13 is restored and formed (FIG. 1(1)).

次に表裏面の無電解めりき用レジスト被膜11を塩化メ
チレン等の溶剤で溶解除去して本発明の多層印刷配線板
を得る(第1図(J))。
Next, the resist coatings 11 for electroless plating on the front and back surfaces are dissolved and removed using a solvent such as methylene chloride to obtain a multilayer printed wiring board of the present invention (FIG. 1 (J)).

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明には次の効果がある。 As explained above, the present invention has the following effects.

(1)スルホール導体層と内層パターンとの短絡不良箇
所が除去されて修復されるので、多層印刷配線板の廃棄
による再製造が不要となる。
(1) Since the defective short-circuit between the through-hole conductor layer and the inner layer pattern is removed and repaired, there is no need to remanufacture the multilayer printed wiring board by discarding it.

(11)修復箇所のスルホール内壁は絶縁性および耐熱
性を有する熱硬化性樹脂で被覆さ几ているので高い信頼
性が維持できる効果がある。
(11) Since the inner wall of the through hole at the repaired location is coated with a thermosetting resin having insulation and heat resistance, high reliability can be maintained.

なお、本実施例では4層構成の多層印刷配線板について
説明したが、より層数の多い多層印刷配線板に対しても
適用できることは勿論である。
In this embodiment, a multilayer printed wiring board with a four-layer structure has been described, but it goes without saying that the present invention can also be applied to a multilayer printed wiring board with a larger number of layers.

また、本実施例では内層のクリアランス内のエツチング
残りについて説明したが、内層基板と外l#基板をプリ
プレグを介して一体化成形する積層する際に内層のクリ
アランス内への導電性の異物が混入した絶縁不良等につ
いても本発明を適用することができる。
In addition, in this example, the etching residue within the inner layer clearance was explained, but when the inner layer board and the outer l# board are integrally molded via prepreg and laminated, conductive foreign matter may be mixed into the inner layer clearance. The present invention can also be applied to insulation defects and the like.

【図面の簡単な説明】 第1図(A)〜(J)は本発明の多層印刷配線板の修復
方法を工程順に示す断面図および平面図である。 1・・・・・・絶縁板、2,3,4.5・・・・・・導
体層、6,6L。 13・・・・・・スルホール4体層、7・・・・・・エ
ツチング残り、8.10・・・・・・(ドリルによる)
貫通孔、9・・・・−・熱硬化性樹脂、11・・・・−
・無電解めっき用レジスト被膜、12・・・・・・(無
電解めっき用)触媒層。 代理人 弁理士  内 原   晋″−第1図 (βジ 第1図 第1図
BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A to 1J are a cross-sectional view and a plan view showing the method for repairing a multilayer printed wiring board according to the present invention in the order of steps. 1... Insulating plate, 2, 3, 4.5... Conductor layer, 6, 6L. 13...Through hole 4 layers, 7...Etching remaining, 8.10...(by drilling)
Through hole, 9...-Thermosetting resin, 11...-
- Resist film for electroless plating, 12... Catalyst layer (for electroless plating). Agent: Susumu Uchihara, Patent Attorney - Figure 1 (Fig. 1)

Claims (1)

【特許請求の範囲】 次の工程を有することを特徴とする多層印刷配線板の修
復方法。 (ア)スルホール導体層と内層パターンの短絡不良のス
ルホール孔を前記スルホール孔より大なる径を有し、か
つ正常位置の内層パターンが露出しない範囲の外径を有
するドリルで第1の貫通孔を穿設する工程; (イ)前記第1の貫通孔内に熱硬化性樹脂を充填し加熱
硬化する工程; (ウ)前記熱硬化性樹脂で充填された第1の貫通孔に前
記スルホールの下孔径と同一径のドリルで第2の貫通孔
を穿設する工程; (エ)前記第2の貫通孔の内壁および表裏ランドを除い
て無電解めっきレジスト被膜を形成する工程; (オ)前記無電解めっきレジスト被膜を形成した多層印
刷配線板に無電解めっき用触媒層を形成する工程; (カ)前記多層印刷配線板の表面の無電解めっき用触媒
層を除去した後、前記第2の貫通孔の内壁および表裏ラ
ンドに無電解めっきにより導体層を形成する工程; (キ)前記無電解めっきレジスト被膜を溶解除去する工
程。
[Scope of Claim] A method for repairing a multilayer printed wiring board, comprising the following steps. (a) Drill the first through-hole with a drill that has a larger diameter than the through-hole hole and an outer diameter within a range that does not expose the inner layer pattern in the normal position. (a) Filling the first through-hole with a thermosetting resin and curing it by heating; (c) Filling the first through-hole with the thermosetting resin under the through-hole. A step of drilling a second through hole with a drill having the same diameter as the hole; (d) A step of forming an electroless plating resist film except for the inner wall of the second through hole and the front and back lands; (e) Forming a catalyst layer for electroless plating on a multilayer printed wiring board on which an electrolytic plating resist film has been formed; (f) After removing the catalyst layer for electroless plating on the surface of the multilayer printed wiring board, forming the second through-hole A step of forming a conductor layer on the inner wall of the hole and the front and back lands by electroless plating; (g) A step of dissolving and removing the electroless plating resist film.
JP25870884A 1984-12-07 1984-12-07 Repair for multilayer printed wiring board Pending JPS61136290A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25870884A JPS61136290A (en) 1984-12-07 1984-12-07 Repair for multilayer printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25870884A JPS61136290A (en) 1984-12-07 1984-12-07 Repair for multilayer printed wiring board

Publications (1)

Publication Number Publication Date
JPS61136290A true JPS61136290A (en) 1986-06-24

Family

ID=17323989

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25870884A Pending JPS61136290A (en) 1984-12-07 1984-12-07 Repair for multilayer printed wiring board

Country Status (1)

Country Link
JP (1) JPS61136290A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04348595A (en) * 1991-05-27 1992-12-03 Hitachi Ltd How to repair multilayer printed circuit board
CN104111047A (en) * 2013-04-22 2014-10-22 北大方正集团有限公司 Calibration assisting device, correction method, inspection method and verification method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04348595A (en) * 1991-05-27 1992-12-03 Hitachi Ltd How to repair multilayer printed circuit board
CN104111047A (en) * 2013-04-22 2014-10-22 北大方正集团有限公司 Calibration assisting device, correction method, inspection method and verification method

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