JPS61136135A - Detecting circuit for external bus error - Google Patents

Abstract

PURPOSE:To detect an external bus error easily in real time by an extremely simple circuit by adding a circuit which compares the data delivered to an external bus with the data supplied from said bus in a data output mode. CONSTITUTION:An external bus error detecting part 1-0 consists of an output buffer 2, input buffer 3 and a comparator 4. The comparator 4 receives supply of a signal d0 and an output signal of the same logical value as a signal D0 sent from the buffer 3. The logic values of these signals are compared with each other, and a comparison result signal P0 of the logical value ''1'' is delivered when no coincidence is obtained from said comparison. The signal D0 has the same logical value as the signal d0 when an external bus is normal. When the logical value of the signal D0 is different from that of the signal d0, it is known that an external bus error occurs. Then the signal P0 of the logical value ''1'' shows that the external bus error is detected.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an external bus error detection circuit that detects all errors on an external bus in a microcomputer/pieta system.

(Prior Art) The output signal of a device connected to an external bus may change due to the influence of the external bus by being connected to the external bus kC. Conventionally, various code addition methods and parity check methods have been used to detect all errors on the external bus.

Among code addition methods, for example, in the error detection method using a Hamming code, it is necessary to add a check code with a certain degree of redundancy, and the number of bits of the bus is large (if the number of check code bits to be added is n) In other words, it is necessary to install not only a bus for data transfer, but also a signal line for transmitting and receiving check codes in parallel with the bus.In addition, on the data transmission side to the bus, Hamming code generation A Hamming code analysis circuit is required on the receiving side.

As another sign addition method? There is also a complete cyclic code system, but like the Hamming code system, it requires circuits for cyclic code generation and analysis, and it is necessary to add a full word of cyclic code to each of a plurality of data words.

As described above, dedicated complicated additional circuits are required for both transmitting and receiving data connected to the bus using the code addition method.

The parity check method is simpler than the above method and
However, in the horizontal parity check method, a parity bit generation port is required for both transmitting and receiving all data to obtain the parity of all bits of a data word, and a parity bit is added to the data word, and a parity bit is generated in parallel with the bus. , parity pit t--requires parity bit ry/l-to send and receive. The vertical parity check method requires a parity generation circuit t which takes parity for each of a plurality of data words, and it is necessary to add a parity word to each of a plurality of data words.

(Problems to be Solved by the Invention) As described above, conventional bus error detection methods of this type require complicated additional circuits, and depending on the method, a dedicated signal wire for detecting data errors running in parallel with the bus is also required. However, there was a problem.

An object of the present invention is to provide an external bus error detection circuit that can detect errors on an external bus with a simple circuit that simultaneously monitors all external buses when outputting data to an external bus without using complicated circuits. It's about doing.

(Means for Solving All Problems) The device of the present invention includes an output buffer connected to an external bus for supplying input data to the external bus, and an output buffer connected to the external bus VC from the output buffer to the external bus. and a comparison means that compares the input data to the output buffer with the output data from the input buffer and generates a mismatch signal when they do not match. be done.

(Example) Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. The external bus error detection circuit shown in FIG. 1 includes eight external bus error detection units 1-0 to 1-7, an OR gate 5, and an
It is composed of Toro.

This embodiment is inserted between the output of a device connected to an external bus and the external bus, and in FIG. 1, the device 1 connected to the external path Vc@ and the external bus are omitted. , do-dγ shown in FIG. 1 indicates each digit of data output from a device connected to the external bus (8-bit case is shown as an example).
-D7 is the above d.

.about.d is output on the external bus via this embodiment.

8 external bus errors detected! All of I5I-0 to 1-7 have the same configuration, and each one is responsible for one digit of data. As an example, external bus error detection unit 1-0
I will explain about it.

It is composed of an external bus error detection section 1, an OH output buffer 2, an input buffer 3, and a comparison circuit 4. This circuit is only for eliminating the influence on the input do due to the connection of the output buffer 2 to the external bus. Similarly, the input buffer 3 is connected to the external bus.

This circuit is only used to eliminate the influence of the comparator circuit 4 on the output buffer 2 and the input buffer 3. Therefore, the logical value of the input signal and the logical value of the output signal of both the output buffer 2 and the input buffer 3 are equal if the external bus is normal. This is a control signal which causes all of the external bus error detection units 1-0 to be activated when the signal is at logic 11', and is inactivated when the signal is at logic @O''.

Next, the operation of the external bus error detection section 1-0 will be explained.

In response to the supply of the signal A of logic @1', the output buffer 2 is activated, and in response to the supply of the signal do, the output buffer 2 is activated.
If the external bus is normal, the output signal Do has the same logical value.
The input buffer 3 receives the signal Do on the external bus and supplies the same output signal to the comparison circuit 4.

The comparator circuit 4 is supplied with the signal cto, the signal Do from the input buffer 7, and the output signal of the same logical value, and compares these logical values, and when they are different, outputs a comparison result signal of the logical value "bi". Outputs Po. Signal.

is the same logical value as the signal dO when the external bus is normal, but the fact that it is different from the signal cto means that an external bus error has occurred, and the comparison result signal of the logical value Po indicates O where all external bus errors have been detected.

The same operation is performed in other external bus error detection sections, and the comparison result signals Po-Py are supplied to the OR gate 5, and at least one of the comparison result signals Po-P is the logical In the case vc, the output of the OR gate 5 becomes logic (direct 1 bit), and this signal is supplied to the A/To Gatero iC. The other input signal of the A/To Gatero is the signal A, and the logic value '''1 is given, so at least one of the above comparison result signals Po, -, and Py of the output signal QU of the A/TO GETRO has a logic value "1", that is, when an error on the external bus occurs, the logic value " This will notify that all 9 external bus errors (1") have been detected.

FIG. 2 shows a circuit diagram of the output buffer 20, in which the output buffer includes a NAND gate 21, a NOR gate 22, an I/P transistor 23, a P channel MOS transistor 24,
It is composed of a channel MOS transistor 25.

When the signal is at the logical value @O'', the P-channel MOS transistor 24Vc is supplied with a signal of logical value 1 bit regardless of the signal do, and the N-channel MOS transistor 25 is supplied with a signal of the logical value ffL@O''. As a result, both MOS transistors have high I/P/S, which affects the external bus.

When the signal A has a logic value @1', the Nant gate 21
and NOR gate 4 both open their gates, and both transistors/registers are supplied with a signal that has a different logic value from the signal do, and both transistors/registers invert the logic value, resulting in a signal with the same logic value as the signal do. the law of nature.

is output.

FIG. 3 shows a circuit diagram of the input buffer 3, which includes the iP channel MOS transistor 31 and the N
It consists of a channel MO8 transistor/register 32↑ and an inverter 33.

The logic value of the input signal R is inverted by the double-edged tiger/rasters 31 and 32, and further inverted again by the I/raster 33, and as a result, the main buffer is inverted.

An output signal with the same logical value as is supplied to the outside.

FIG. 4 shows a circuit diagram of the comparator circuit 4, which is composed of an Ai exclusive OR gate. This circuit is supplied with a signal Po of logical value 10# when the two input signals have the same logical value, and a signal Po of logical value "1" when the two input signals have different logical values. do.

As described above, in this embodiment, when an external bus error occurs in which the logical value is inverted due to the influence of the external bus,
It is possible to easily detect and report a crash.

In this embodiment, the input to the output buffer (No. 3) was compared with the output signal from the input buffer, but the present invention is not limited to this, and logically when the external bus is normal, the same - You may compare two signals at arbitrary locations that are logical values.For example, the output signal of the at gate 21 or the NOR gate 22 in FIG. You can also use it as

(Effects of the Invention) By adding a circuit 7 that compares the data output to the VCI external bus and the data input from the external bus at the time of data output, the external bus
Detection can be easily carried out in real time using an extremely simple circuit, which has the effect of improving the reliability of the micro combinator system.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG.
Figures 3 and 4 are circuit diagrams of the input buffer and comparison circuit of the 717 outputs in Figure 1. 1-0.1-1 to 1-7... External bus error detection section, 2... Output buffer % 3...
Input puffer, 4... Comparison circuit, 5...
・Or Gate, 6...At Gate, 21...
...Nant Gate, 22...Noah Gate,
23.33... Inverter, 24.31...
...P-channel MOS transistor, 25.32 Agent Patent Attorney Uchihara Ppar' 11 Figure 1

Claims (1)

[Scope of Claims] An output buffer that is connected to an external bus and supplies input data supplied to the external bus; and an output buffer that is connected to the external bus and uses data supplied from the output buffer to the external bus as input data. An external bus error detection circuit comprising: an input buffer; and comparison means for comparing input data to the output buffer and output data from the input buffer and generating a mismatch signal when they do not match.