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JPS61135141A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS61135141A
JPS61135141A JP25865084A JP25865084A JPS61135141A JP S61135141 A JPS61135141 A JP S61135141A JP 25865084 A JP25865084 A JP 25865084A JP 25865084 A JP25865084 A JP 25865084A JP S61135141 A JPS61135141 A JP S61135141A
Authority
JP
Japan
Prior art keywords
wiring layer
film
aluminum wiring
nitride film
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25865084A
Other languages
Japanese (ja)
Inventor
Takeshi Shinohara
剛 篠原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP25865084A priority Critical patent/JPS61135141A/en
Publication of JPS61135141A publication Critical patent/JPS61135141A/en
Pending legal-status Critical Current

Links

Landscapes

  • Local Oxidation Of Silicon (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To enable the prevention of breakage of a final passivation film by baking the substrate in a vacuum once after spatter etching. CONSTITUTION:On a wafer substrate 1, a passivation PSG film 2, the first layer aluminum wiring layer 3, and a nitride film 4 are formed. On an interlaminar nitride film 4, the second layer aluminum wiring layer 5 is formed by photolithography and spatter etching. As a spattering gas sticks into the interlaminar nitride film 4 at spatter etching, the pressure inside the device is reduced to a vacuum subsequently after spatter etching and the temperature under the predetermined value is held for a few quarters of an hour and baking is done. A spattering gas is exhausted and a final passivation film 6 is formed followed by final heat treatment to obtain the desired semiconductor device. The partial swelling of the second layer aluminum wiring layer and accordingly the partial breakage of the final passivation film can be prevented and also simplification of a baking process can be contrived.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は半導体装置の製造方法に関し、特に2層配線
を有する半導体装置の製造方法に係るものである。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device having two-layer wiring.

〔従来の技術〕[Conventional technology]

従来例方法でのこの種の2層配線を有する半導体装置に
おける最終製造工程の概要構成を第2図(a)、(b)
に示す、すなわち、これらの各図において、符号lはウ
ェハ基板、2はウェハ基板l上のパッシベーションPS
G@、 3はPSGl12上の第1層アルミニウム配線
層、4は層間絶縁膜としての窒化膜、5は層間窒化膜4
上の第2層アルミニウム配線層、6はこれらの上を覆う
ファイナルパッシベーション膜である。
Figures 2(a) and 2(b) show a schematic configuration of the final manufacturing process for a semiconductor device having this type of two-layer wiring using a conventional method.
That is, in each of these figures, the symbol l is the wafer substrate, and 2 is the passivation PS on the wafer substrate l.
G@, 3 is the first aluminum wiring layer on the PSGl 12, 4 is a nitride film as an interlayer insulating film, 5 is an interlayer nitride film 4
The upper second aluminum wiring layer 6 is a final passivation film covering these layers.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかして前記構成での半導体装置においては、その第2
層アルミニウム配線層3の形成工程で。
However, in the semiconductor device with the above configuration, the second
In the step of forming layer aluminum wiring layer 3.

スパッタエツチングをなすが、このエツチング時にあっ
て、スパッタガスであるアルゴンガスが暦間窒化膜喀に
突きさ\ることになる。そしてその後1次段以降の工程
を行ない、かつ最終熱処理を施して第2図(a)の構造
を得るのであるが、この最終熱処理時にあって1層間窒
化膜4に突きさ−ったアルゴンガスが、密度の小さい第
2層アルミニウム配線層3の下側に集まり、その圧力に
よってこの第2層アルミニウム配線層3が持ち上げられ
、これによって同図(h)に示すように、ファイナルパ
ッジベージ、ンIfI8に部分的な破壊を生じて、装置
自体の信頼性を低下させるという不都合があった。
Sputter etching is performed, and during this etching, argon gas, which is a sputter gas, penetrates into the nitride film layer. Thereafter, the steps from the first stage onwards are carried out, and a final heat treatment is performed to obtain the structure shown in FIG. 2(a). The particles gather under the second aluminum wiring layer 3, which has a low density, and the pressure lifts the second aluminum wiring layer 3, thereby causing the final pad page to rise as shown in FIG. There was an inconvenience that partial destruction of IfI8 occurred, reducing the reliability of the device itself.

この発明方法は、従来方法でのこのような問題点に鑑み
、最終的にファイナルパッジベージ望ン膜に破壊を生ず
ることのない半導体装置の製造方法を提供することを目
的とする。
In view of the above-mentioned problems with the conventional method, it is an object of the method of the present invention to provide a method for manufacturing a semiconductor device that does not ultimately cause damage to the final padding film.

〔問題点を解決するための手段〕[Means for solving problems]

この発明に係る半導体装置の製造方法では、スパッタエ
ツチング後に、一旦、真空中でベーキングをなすことに
より、スパッタエツチング時に居間窒化膜に突きさ−っ
たアルゴンガスを抜き取るようにしたものである。
In the method of manufacturing a semiconductor device according to the present invention, baking is performed in a vacuum after sputter etching to remove the argon gas that penetrates the nitride film during sputter etching.

〔作   用〕[For production]

従ってこの発明方法の場合には、スパッタエツチング時
に居間窒化膜に突きさ\つだアルゴンガスを、ベーキン
グにより抜き取った後に、次段以降の処理を施すように
したから、最終熱処理に際して第2層アルミニウム配線
層の部分的な浮き上りを防止できるのである。
Therefore, in the case of the method of this invention, the argon gas that penetrates the nitride film during sputter etching is removed by baking, and then the subsequent processes are performed. This makes it possible to prevent partial lifting of the wiring layer.

〔実 施 例〕〔Example〕

以下この発明に係る半導体装置の製造方法の一実施例に
つき、第1図(a)、(b)を参照して詳細に説明する
An embodiment of the method for manufacturing a semiconductor device according to the present invention will be described in detail below with reference to FIGS. 1(a) and 1(b).

第1図(a)、(b)はこの実施例方法を適用した半導
体装置の製造工程を順次に表わしており、これらの第1
図(a)、(b)実施例方法において、前記第2図(a
)、(b)従来例方法と同一符号は同一または相当部分
を示している。
FIGS. 1(a) and 1(b) sequentially show the manufacturing process of a semiconductor device to which this embodiment method is applied.
Figures (a) and (b) In the example method, the above-mentioned Figure 2 (a)
), (b) The same reference numerals as in the conventional method indicate the same or corresponding parts.

この実施例方法においても、前記従来例方法と同様に、
ウェハ基板1上にパフシベーションPSG膜2.第1層
アルミニウム配線層3.窒化膜4をそれぞれに形成し、
また居間窒化膜4上に通常の写真製版法、およびスパッ
タエツチング法を利用して第2層アルミニウム配線層5
を形成(第1図(a))するが、こへでもスパッタエツ
チングに際し、スパッタガスであるアルゴンガスが居間
窒化膜4に突きさ覧った状態となる。
In this example method, as well as in the conventional example method,
A puffivated PSG film 2 on a wafer substrate 1. First layer aluminum wiring layer 3. A nitride film 4 is formed on each,
Further, a second aluminum wiring layer 5 is formed on the living nitride film 4 by using a normal photolithography method and a sputter etching method.
(FIG. 1(a)), but even here, during sputter etching, argon gas, which is a sputter gas, penetrates into the living room nitride film 4.

そこでこの実施例方法では、前記したスパッタ装置内で
のスパッタエツチングに連続して、そのま−同装置内を
IX 1G−5tarr程度の真空に減圧すると共に、
所定温度下に数十分間保持してベーキングさせ、スパッ
タガスであるアルゴンガスを層間窒化fi4から抜き取
り、その後、ファイナルパッシベーション1118を形
成し、ついで最終熱処理を行なって、目的とする半導体
装置を得る(同図(b))のである。
Therefore, in this embodiment method, immediately after the sputter etching in the sputtering equipment described above, the inside of the equipment is immediately reduced to a vacuum of about IX 1G-5 tarr, and
Baking is performed by holding at a predetermined temperature for several tens of minutes, and argon gas, which is a sputtering gas, is extracted from the interlayer nitriding fi4.Final passivation 1118 is then formed, and then final heat treatment is performed to obtain the intended semiconductor device. ((b) in the same figure).

従ってこの実施例方法の場合には、スパッタエツチング
時に居間窒化膜に突きさ−ったアルゴンガスを、ベーキ
ングにより抜き取った後に、次段以降の処理を施し、か
つ最終熱処理を行なうようにすることで、第2層アルミ
ニウム配線層の部分的な浮き上り、ひいてはファイナル
パッジベージ璽ン膜の部分的な破壊を防止できるのであ
り、また併せてスパッタ装置内でめスパッタエツチング
に引き続いて、同装置内での真空減圧下におけるベーキ
ングをなすことで、ベーキング工程の簡略化をも噛り得
るのである。
Therefore, in the case of this embodiment method, the argon gas that penetrated the nitride film during sputter etching is removed by baking, and then the subsequent processes are performed and the final heat treatment is performed. , it is possible to prevent partial lifting of the second layer aluminum wiring layer and, by extension, partial destruction of the final padding film. By performing baking under vacuum and reduced pressure, the baking process can also be simplified.

〔発明の効果〕〔Effect of the invention〕

以上詳述したようにこの発明方法によれば、2暦配線の
形成に際し、第2層アルミニウム配線層形成のためのス
パッタエツチング後に、一旦、真空中でベーキングをな
して、スパッタエツチング時に居間窒化膜に突きさへっ
たアルゴンガスを抜き取るようにしたから、最終熱処理
時での、第2層アルミニウム配線層の部分的な浮き上り
、ひいてはファイナルパッシベーション膜の部分的な破
壊を防止でき、結果的に半導体装置の信頼性を格段に向
上し得るものである。
As described in detail above, according to the method of the present invention, when forming two-layer wiring, after sputter etching for forming the second layer aluminum wiring layer, baking is performed in a vacuum once, and the nitride film is removed during sputter etching. By extracting the argon gas stuck in the wafer, it is possible to prevent the partial lifting of the second aluminum wiring layer and the partial destruction of the final passivation film during the final heat treatment. This makes it possible to significantly improve the reliability of semiconductor devices.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(1)、(b)はこの発明に係る半導体装置の製
造方法の一実施例を工程順に示すそれぞれ断面図であり
、また第2図(a)、(b)は同上従来例での半導体装
置の製造方法を工程順に示すそれぞれ断面図である。 
   ′ l・・・・ウェハ基板、3・・・・第1層アルミニウム
配線層、4・・・・層間窒化膜、5・・・・第2層アル
ミニウム配m層、8・・・・ファイナルパッシベーショ
ン膜。 第1図 (b) 第2図 (b) 手続補正書(自発) 1、事件の表示   特願昭59−258650号2、
発明の名称 半導体装置の製造方法 3、補正をする者 5、補正の対象 明細書の発明の詳細な説明の欄 6、補正の内容 (1)  [B書2頁10.18及び19行の「配線層
3」を「配線層5」と補正する。 (2)同書5頁1行のrIXlo  torrJを「1
X 10  torr Jと補正する。 以  上
1(1) and 1(b) are cross-sectional views showing an embodiment of the method for manufacturing a semiconductor device according to the present invention in the order of steps, and FIGS. 2(a) and 2(b) are sectional views showing the conventional example of the same. FIG. 3 is a cross-sectional view showing a method for manufacturing a semiconductor device in the order of steps;
'l... Wafer substrate, 3... First layer aluminum wiring layer, 4... Interlayer nitride film, 5... Second layer aluminum wiring layer, 8... Final passivation. film. Figure 1 (b) Figure 2 (b) Procedural amendment (spontaneous) 1. Indication of case Patent application No. 59-258650 2.
Title of the invention: Method for manufacturing a semiconductor device 3, Person making the amendment 5, Detailed description of the invention in the specification subject to the amendment 6, Contents of the amendment (1) [Book B, page 2, lines 10.18 and 19, “ "Wiring layer 3" is corrected to "Wiring layer 5". (2) rIXlo torrJ on page 5, line 1 of the same book as “1
Correct as X 10 torr J. that's all

Claims (1)

【特許請求の範囲】[Claims]  ウェハ基板上にパッシベーションPSG膜、第1層ア
ルミニウム配線層、窒化膜をそれぞれに形成し、また層
間窒化膜上に通常の写真製版法、およびスパッタエッチ
ング法を利用して第2層アルミニウム配線層を形成した
後、ベーキングさせ、ついでファイナルパッシベーショ
ン膜形成、ならびに最終熱処理を施す工程を含むことを
特徴とする半導体装置の製造方法。
A passivation PSG film, a first aluminum wiring layer, and a nitride film are formed on the wafer substrate, and a second aluminum wiring layer is formed on the interlayer nitride film using ordinary photolithography and sputter etching. 1. A method of manufacturing a semiconductor device, comprising the steps of forming a semiconductor device, baking it, forming a final passivation film, and subjecting it to final heat treatment.
JP25865084A 1984-12-05 1984-12-05 Manufacture of semiconductor device Pending JPS61135141A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25865084A JPS61135141A (en) 1984-12-05 1984-12-05 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25865084A JPS61135141A (en) 1984-12-05 1984-12-05 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS61135141A true JPS61135141A (en) 1986-06-23

Family

ID=17323205

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25865084A Pending JPS61135141A (en) 1984-12-05 1984-12-05 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS61135141A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01220677A (en) * 1988-02-29 1989-09-04 Ricoh Co Ltd Paper stacking device for copying machine or the like
US5164339A (en) * 1988-09-30 1992-11-17 Siemens-Bendix Automotive Electronics L.P. Fabrication of oxynitride frontside microstructures

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01220677A (en) * 1988-02-29 1989-09-04 Ricoh Co Ltd Paper stacking device for copying machine or the like
US5164339A (en) * 1988-09-30 1992-11-17 Siemens-Bendix Automotive Electronics L.P. Fabrication of oxynitride frontside microstructures

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