JPS61131554A - Mounting process of semiconductor device - Google Patents
Mounting process of semiconductor deviceInfo
- Publication number
- JPS61131554A JPS61131554A JP59253507A JP25350784A JPS61131554A JP S61131554 A JPS61131554 A JP S61131554A JP 59253507 A JP59253507 A JP 59253507A JP 25350784 A JP25350784 A JP 25350784A JP S61131554 A JPS61131554 A JP S61131554A
- Authority
- JP
- Japan
- Prior art keywords
- plating
- plated
- solder
- leads
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 16
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 238000007747 plating Methods 0.000 claims abstract description 49
- 229910000679 solder Inorganic materials 0.000 claims abstract description 25
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 24
- 238000005452 bending Methods 0.000 claims description 12
- 229910052759 nickel Inorganic materials 0.000 claims description 5
- 229910000881 Cu alloy Inorganic materials 0.000 claims description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 2
- 238000004806 packaging method and process Methods 0.000 claims description 2
- 238000006056 electrooxidation reaction Methods 0.000 abstract description 4
- 229910000765 intermetallic Inorganic materials 0.000 abstract description 3
- 229910052802 copper Inorganic materials 0.000 abstract description 2
- 238000005538 encapsulation Methods 0.000 description 3
- 239000012634 fragment Substances 0.000 description 3
- 230000007257 malfunction Effects 0.000 description 3
- 229910000851 Alloy steel Inorganic materials 0.000 description 2
- BZHJMEDXRYGGRV-UHFFFAOYSA-N Vinyl chloride Chemical compound ClC=C BZHJMEDXRYGGRV-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49582—Metallic layers on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、銅合金リードフレームで作られた半導体装置
の外装めっきに関し、特に、高信頼度が期待できる外装
めっき方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to exterior plating of a semiconductor device made of a copper alloy lead frame, and particularly to an exterior plating method that can be expected to be highly reliable.
従来、鋼合金リードフレームを用いた場合の半導体装置
の外装めっき方法としては、３通り上げられる。■：銅
合金リードフレームの全面にニッケル（Ｎｉ）めっきを
施こしマクント、ボンディング、封入等の工程を経た後
、Ｎｉめつき上に生成した酸化膜をエツチングしＳｎめ
つきまたは半田めっきを行う方法。■：錫（Ｓｎ）めっ
きまたは半田めっきを行う直前にＮｉめつきを行う方法
。■：ＮｉめっきをＳｎめりきまたは半田めっきの下地
として入れず直接Ｓｎめつきまたは半田めっきを行う方
法である。Conventionally, there are three methods for plating the exterior of a semiconductor device using a steel alloy lead frame. ■: A method in which nickel (Ni) plating is applied to the entire surface of a copper alloy lead frame, and after going through processes such as masking, bonding, and encapsulation, the oxide film formed on the Ni plating is etched and Sn plating or solder plating is performed. . ■: A method in which Ni plating is performed immediately before tin (Sn) plating or solder plating. (2): This is a method of directly performing Sn plating or solder plating without using Ni plating as a base for Sn plating or solder plating.
上述した従来の■、■の方法としては、鋼合金とＳｎめ
っきまたは半田めっきの中間層にかたいＮｉめっきがあ
るためプラスチックパッケージ等のリード曲げ工程にお
いて曲げ部にクラックが込り電気化学的コロ−ジョンの
原因となったりときには、めっき層の破片がリード等の
端子に付着し、回路の誤動作を引き起こすという欠点が
あった。In the conventional methods (2) and (3) mentioned above, since there is a hard Ni plating in the intermediate layer between the steel alloy and the Sn plating or solder plating, cracks form in the bent part during the lead bending process for plastic packages, etc., resulting in electrochemical corrosion. - In some cases, fragments of the plating layer adhere to terminals such as leads, causing malfunction of the circuit.
一方、■の方法としては、銅合金とＳｎめっきまたは半
田めっきとの間にバリア層となるＮｒ めっきが込って
いないため、半導体装置実装時の高温やその後の年月の
経過で銅とＳｎの金属間化合物層を作る。金属間化合物
層には、例えばオーリン社製の１９４ＡＬＬＯＹｔｙ）
場合ｎ層（ＣｕｓＳｎ＋ｓ）相当なものと、ξ層（Ｃｕ
ｓＳｎ）相当なものが生成し、特にξ層相当な化合物層
は、硬度が高くもろい性質があり、小さな振動等で半田
接合部の電気的な接続が失なわれるという欠点があった
。On the other hand, method (2) does not include Nr plating, which acts as a barrier layer, between the copper alloy and Sn plating or solder plating. Create an intermetallic compound layer. For the intermetallic compound layer, for example, 194ALLOYty manufactured by Olin Co., Ltd.
In this case, the n layer (CusSn+s) and the ξ layer (Cu
In particular, the compound layer corresponding to the ξ layer has high hardness and brittle properties, and has the disadvantage that the electrical connection of the solder joint is lost due to small vibrations.
本発明の外装方法は、リードを曲げる屈曲部には、Ｎｉ
めっきを行なわずかつ半田付けされるリード部にはＮｉ
めっきを施こしてＳｎめっきまたは半田めっきをするこ
とで半導体装置の信頼性を高めようとするものである。In the packaging method of the present invention, the bending portion where the lead is bent is made of Ni.
Ni is applied to the lead parts to be plated and soldered.
The purpose is to improve the reliability of semiconductor devices by performing plating, such as Sn plating or solder plating.
以上説明したように本発明は、半田で接合され嶌
る部分にはＮｉめ９きを下地とレア施し、リー
、。As explained above, the present invention is applicable to solder bonded parts.
The parts that are coated with nickel are coated with 9mm nickel as a base and rare.
が曲、げられる屈曲点にはＮｉめりきを施こさないこと
により曲げ部すなわち屈曲点にクラックが生じ電気化学
的コロージッンの原因となったりクラックが生じたため
にめっき層の破片ができそれがリード等の端子に付着し
回路の誤動作を引き起こしたり、Ｎｉめっきによるバリ
アがないため、銅とＳｎとのもろい金属間化学物層を作
って、半田、−接合部の電気的な接続が失なわれること
なく高信頼性の半導体装置を提供できる効果がある。If Ni plating is not applied at the bending point where the metal is bent, cracks may occur at the bending point, which may cause electrochemical corrosion, or cracks may cause fragments of the plating layer, which can lead to cracks. etc., causing malfunction of the circuit, and since there is no barrier provided by Ni plating, a brittle intermetallic chemical layer between copper and Sn may be formed, causing electrical connection between the solder and the joint to be lost. This has the effect of providing a highly reliable semiconductor device without any problems.
次に、本発明について図面を参照して設明する。 Next, the present invention will be explained with reference to the drawings.
第１図は、本発明の一実施例を示すデエアルインパッケ
ージの断面図である。実装時に半田で接合される部分Ａ
にはＮｉめりき８を施し、リードが曲げられる屈曲点Ｂ
にはＮｉめりき８を施こさないでＳｎめっきあるいは半
田めっき９の外装めりき９を行う。したがって、リード
が曲げられる屈曲点ＢにはＮｉめっき８を施こさないこ
とにより屈曲点Ｂにクラックが生じ電気化学的コロ−ジ
ョンの原因となったりクラックが生じたためにめっき層
の破片ができそれがリード７等の端子に付着し回路の誤
動作を引き起こすたりすることはない。FIG. 1 is a sectional view of an air-in package showing an embodiment of the present invention. Part A that is joined with solder during mounting
Ni-plated 8 is applied to the bending point B where the lead is bent.
Exterior plating 9 of Sn plating or solder plating 9 is performed without Ni plating 8. Therefore, if the Ni plating 8 is not applied to the bending point B where the lead is bent, cracks may occur at the bending point B, causing electrochemical corrosion, or cracks may cause fragments of the plating layer. will not adhere to terminals such as the lead 7 and cause malfunction of the circuit.
また、実装時に半田で接合される部分Ａには、Ｎｉめっ
き８を下地としてＳｎめっきまたは半田めりき９を行う
ので半導体装置の実装時の高温やその後の年月の経過に
よる鋼とＳｎの金属間化合物層が生成しないのでプリン
ト板、と半導体装置の実装状態が劣化することはないた
めに半導体装置が組み込まれた装置本体から発生、する
小さな振動等で半田接合部の電気的な接続が失なわれた
りすることもない。In addition, since Sn plating or solder plating 9 is applied to the portion A that is joined with solder during mounting, Ni plating 8 is used as a base, so the steel and Sn metal may be damaged due to the high temperature during the mounting of the semiconductor device or the subsequent passage of time. Since no intermediate compound layer is generated, the printed circuit board and the mounting condition of the semiconductor device will not deteriorate. Therefore, the electrical connection of the solder joint will be lost due to small vibrations generated from the device body in which the semiconductor device is installed. There is no need to worry.
第２図は本発明の製造方法の例を表わした平面図で、封
入後不用な部分を除いたリードフレームを表わす。リー
ドフレーム５１に塩化ビニール等の絶縁物２でリードが
曲げられ今屈曲点Ｂまでマスクし、半田で、接合される
部分ＡはマスクしないでＮｉめっき８を施し次にＳｎめ
っきまたは半田めっき９を行い、リード７を所定の形状
に曲げ半導体装置は完成する。FIG. 2 is a plan view showing an example of the manufacturing method of the present invention, and shows a lead frame with unnecessary parts removed after encapsulation. The lead is bent on the lead frame 51 with an insulator 2 such as vinyl chloride, and the bending point B is masked, and the part A to be joined with solder is coated with Ni plating 8 without being masked, and then Sn plating or solder plating 9 is applied. The semiconductor device is completed by bending the leads 7 into a predetermined shape.
第１図は本発明の実施例を示すデエアルラインパッケー
ジの断面図、第２図は本発明の実施例を実現する為の製
造方法を表わした平面図で、封入後不用な部分を除いた
リードフレームに塩化ビニール等の絶縁物でリードが曲
げられる屈曲点までマスクをしたことを示す。
１・・・・・・リードフレーム、２・・・・・・絶縁物
、３・・・・・・樹脂、４・・・・・・半導体素子、５
・・・・・・Ａｕワイヤ、６・・・・・・半導体素子搭
載部、７・・・・・・リード、８・・・・・・Ｎｉめっ
き、９・・・・・・Ｓｎめりきまたは半田めっき、Ａ・
・・・・・実装時に半田が接合される部分、Ｂ・・・・
・・リードが曲げられる屈曲点、。Fig. 1 is a cross-sectional view of a de-air line package showing an embodiment of the present invention, and Fig. 2 is a plan view showing a manufacturing method for realizing an embodiment of the present invention, with unnecessary parts removed after encapsulation. Indicates that the lead frame is masked with an insulating material such as vinyl chloride up to the bending point where the lead is bent. 1... Lead frame, 2... Insulator, 3... Resin, 4... Semiconductor element, 5
...Au wire, 6...Semiconductor element mounting part, 7...Lead, 8...Ni plating, 9...Sn plating Or solder plating, A.
... Part where solder is joined during mounting, B...
...the bending point at which the lead is bent.
Claims (1)
曲げられる屈曲点にはニッケルめっきをせず、半田でリ
ードが接合される部分にはニッケルめっきを下地として
施し、錫めっきまたは半田めっきを行うことを特徴とす
る半導体装置の外装方法。In lead frames made of copper alloy, nickel plating is not applied to the bending points where the leads are bent, and nickel plating is applied as a base to the parts where the leads are joined with solder, followed by tin plating or solder plating. A featured method for packaging semiconductor devices.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59253507A JPS61131554A (en) | 1984-11-30 | 1984-11-30 | Mounting process of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59253507A JPS61131554A (en) | 1984-11-30 | 1984-11-30 | Mounting process of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61131554A true JPS61131554A (en) | 1986-06-19 |
Family
ID=17252335
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59253507A Pending JPS61131554A (en) | 1984-11-30 | 1984-11-30 | Mounting process of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61131554A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0416141A (en) * | 1990-05-08 | 1992-01-21 | Mai Planning:Kk | How to make frozen bread dough |
-
1984
- 1984-11-30 JP JP59253507A patent/JPS61131554A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0416141A (en) * | 1990-05-08 | 1992-01-21 | Mai Planning:Kk | How to make frozen bread dough |
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