JPS61128632A - Viterbi decoder - Google Patents

Abstract

PURPOSE:To improve the performance of a Viterbi decoder without a large-scale majority decision circuit by applying majority arithmetic to m sets of outputs extracted optionally from 2<k-1> sets of bus memory outputs of the Viterbi decoder of restricting length K. CONSTITUTION:The Viterbi decoder 1 of restricting length L calculates inputs I and Q in outputs obtained by demodulating a convolution code at the transmission side to generate an output to the 2<k-1> bus memories. The majority decision circuit 2 extracts m sets of outputs optionally out of the 2<k-1> bus memory outputs to take majority decision. Thus, an output comprising codes improved for an error rate is obtained as an output of the circuit 2. Further, a bus memory output of the decoder 1 is grouped and with respect to the result obtained by the majority decision, further majority decision is obtained to get a decoding output. Thus, the performance of the Viterbi decoder by the majority decision is realized without lowering the operating speed with a small scale circuit.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an improvement of a Viterbi decoder, and particularly to a Viterbi decoder in which a majority circuit is added to the path memory output of the Viterbi decoder to improve the error rate. It is.

[Conventional technology]

In the Viterbi decoder, outputs are obtained in the number of path memories determined by its constraint length K, and when the error rate of the input code is small, the outputs of each path memory are correct and the same, so any path memory output of llll1g A commonly used method is to extract the data and use it as the decoded output. If the error rate is relatively high and the error rate is relatively high, the number of incorrect codes output to each pass memory output will gradually increase as the correction capacity exceeds the limit, and eventually the number of erroneous codes will increase to "1" and " A state is reached in which almost the same number of O'' is output. Therefore, when used in such a state where the error rate is high, the error rate can be improved by using a plurality of path memory outputs and taking a majority vote to obtain the decoded output.

It is well known that the number of path memory outputs of a Viterbi decoder is two when the code constraint length is K. Therefore, for example, when the constraint length is 4, the number of path memory outputs is 8, so the majority circuit that performs majority calculation processing is relatively small-scale, and the majority circuit is used to improve the error rate in the Viterbi decoder. It is also easy. Such a majority circuit with eight inputs is already known, for example, from Japanese Patent Application No. 59-182075 "Majority Circuit" filed by the present applicant.

However, as the constraint length increases, the number of path memory outputs increases exponentially. For example, when =7, the number of path memory outputs is 64, and the circuit scale of the majority circuit becomes enormous, and the processing speed decreases significantly as the number of gate stages used increases. , it will no longer have any practical value.

On the other hand, the performance improvement (usually evaluated by coding gain) due to the addition of a majority circuit is originally 0.3 dB.
It's just a small amount, but not that big. Therefore, improving the performance of the Viterbi decoder by using a majority circuit is meaningless unless it can be realized with a small-scale circuit.

[Problem that the invention seeks to solve]

Improving the performance of the Viterbi decoder by adding a majority circuit to the path memory output has not been used in the past because the circuit size becomes large when the code constraint length is long.The present invention solves these problems of the conventional technology. The purpose of the present invention is to provide a Viterbi decoder that can perform majority voting on path memory outputs in a large-scale Viterbi decoder with a relatively long code constraint length using a small-scale circuit and at high speed. It is something.

[Means for solving problems]

In the Viterbi decoder of the present invention, m outputs are arbitrarily extracted from the two path memory outputs of the Viterbi decoder with a constraint length of −l, and a majority operation is performed on the extracted m(rM outputs). , this output is the decoded output of the Viterbi decoder, and the constraint length is 21 of the Viterbi decoder.
The output of the fixed path memory is arbitrarily divided into n equal parts, and a majority operation is performed on each group to generate the output.
The majority of the plurality of majority calculation outputs is taken as the decoded output of the Viterbi decoder.

[For production]

According to the Viterbi decoder of the present invention, the decoded output can be obtained by determining the majority vote for m outputs arbitrarily extracted from the path memory outputs, or the result of dividing the path memory outputs into groups and determining the majority vote for each. Furthermore, we obtain the decoded output by obtaining a majority vote, so
The performance of the Tabi decoder can be improved by using a majority circuit with a small-scale circuit and without reducing the operating speed.

〔Example〕

FIG. 1 shows an embodiment of the Viterbi decoder of the present invention,
This figure shows how to obtain a decoded output with an improved error rate by arbitrarily extracting some outputs from a huge number of path memory outputs and taking a majority vote on a small number of extracted representative outputs.

In FIG. 1, 1 is a Viterbi decoder, and for example, the constraint length is set to 7. As is well known, the Viterbi decoder 1
Calculations are performed from the (1) input and Q input in the output of the demodulated convolutional code on the transmitting side, and outputs are generated in two path memories. Therefore, when K=7, the number of path memory outputs is 64. The majority decision circuit 2 arbitrarily extracts 8111 outputs from among the 64 path memory outputs of the Viterbi decoder 1 and takes a majority decision. As the second configuration of the majority circuit, the circuit configuration disclosed in Japanese Patent Application No. 59-182075 mentioned above can be used.

This makes it possible to obtain an output from the majority circuit 2 consisting of a code with an improved error rate.

In the Viterbi decoder shown in Figure 1, 8 of the 64 path memory outputs are extracted and a majority vote is taken. On the other hand, if there are too many, it will increase the circuit scale and reduce the operating speed, making it difficult to implement, so the above-mentioned number of about eight is considered appropriate.

FIG. 2 shows another embodiment of the present invention, in which a large number of path memory outputs are arbitrarily divided into n equal parts, a majority vote is taken for each of the equal parts, and a further majority vote is taken for each majority output. shows the decoding output with improved error rate.

In FIG. 2, numeral 1 is a Tavi decoder similar to that in FIG. 1, and the constraint length is set to 7, for example, and 64 path memory outputs are generated. 11-1 to 11-8 are majority decision circuits each powered by eight people, and the Viterbi decoder 1
The path memory output of 8 is divided into 8 equal parts, and each of the 8 path memory outputs is inputted and a majority vote is determined. 12
is an 8-person majority circuit, and each majority circuit 11-1
-11-8 are input, the majority vote is taken, and a decoded output is generated. Therefore, as the output of the majority circuit 12, a decoded output consisting of a code with an improved error rate can be obtained.

In the method of the present invention, the overall path memory output is divided and a majority vote is taken for each result, so the degree of error rate improvement is limited to 64 path memories by one majority decision circuit. It is expected that almost the same, but not necessarily the same, result will be obtained compared to the case of taking a majority vote of the outputs.

In the case of this embodiment, a large number of path memory outputs are equally divided into n groups. In this case, if the number of divisions n is large, the circuit scale of the majority circuit in the subsequent stage becomes large, and conversely, if the number of divisions n is small, the circuit scale of the subsequent stage The scale of the majority circuit becomes smaller, but the scale of each preceding stage majority circuit increases. Therefore, it is most economical to make the number of majority circuits at the front stage approximately equal to the number of inputs to the majority circuit at the rear stage. Especially when the constraint length is 7, n=8
In this case, it is convenient that the system of the present invention can be realized by an eight-person majority circuit 9 IrM having the same configuration.

According to the method of this embodiment, when applied to a Viterbi decoder with a constraint length of 6 to 7, majority arithmetic processing can be performed with a small-scale circuit configuration, and high-speed operation can also be achieved.

〔Effect of the invention〕

As explained above, according to the Viterbi decoder of the present invention,
It is possible to improve the performance of a Viterbi decoder using a majority circuit without requiring a large-scale majority circuit and without reducing operating speed.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 and FIG. 2 are diagrams each showing an embodiment of a Viterbi decoder of the present invention.

Claims (2)

[Claims] (1) Means for arbitrarily extracting m outputs from 2^K^-^1 path memory outputs of a Viterbi decoder with constraint length K, and performing majority operation on the extracted m outputs and outputting them. A Viterbi decoder comprising: a majority circuit that generates a signal, and an output of the majority circuit is used as a decoded output of the Viterbi decoder. (2) A plurality of pre-stage majority circuits that perform majority calculations on the outputs of each group obtained by arbitrarily dividing the 2^K^-^1 path memory output of the Viterbi decoder with constraint length K into n equal parts and generate outputs. and a latter-stage majority circuit that performs a majority operation on the outputs of the plurality of preceding-stage majority circuits to generate an output, and the output of the latter-stage majority circuit is used as the decoded output of the Viterbi decoder. Viterbi decoder.