JPS61125138A - Manufacture of sealed electron part - Google Patents
Manufacture of sealed electron partInfo
- Publication number
- JPS61125138A JPS61125138A JP24766484A JP24766484A JPS61125138A JP S61125138 A JPS61125138 A JP S61125138A JP 24766484 A JP24766484 A JP 24766484A JP 24766484 A JP24766484 A JP 24766484A JP S61125138 A JPS61125138 A JP S61125138A
- Authority
- JP
- Japan
- Prior art keywords
- electronic component
- recess
- sealing resin
- circuit pattern
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 claims abstract description 29
- 229920005989 resin Polymers 0.000 claims abstract description 27
- 239000011347 resin Substances 0.000 claims abstract description 27
- 238000007789 sealing Methods 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 238000002347 injection Methods 0.000 claims description 3
- 239000007924 injection Substances 0.000 claims description 3
- 239000012212 insulator Substances 0.000 claims 1
- 238000005452 bending Methods 0.000 abstract description 3
- 230000035939 shock Effects 0.000 abstract 1
- 230000017525 heat dissipation Effects 0.000 description 10
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 239000004033 plastic Substances 0.000 description 5
- 239000011810 insulating material Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 239000003822 epoxy resin Substances 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000003780 insertion Methods 0.000 description 2
- 230000037431 insertion Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- LNEPOXFFQSENCJ-UHFFFAOYSA-N haloperidol Chemical compound C1CC(O)(C=2C=CC(Cl)=CC=2)CCN1CCCC(=O)C1=CC=C(F)C=C1 LNEPOXFFQSENCJ-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 229920000306 polymethylpentene Polymers 0.000 description 1
- 239000011116 polymethylpentene Substances 0.000 description 1
- 238000004382 potting Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- BFKJFAAPBSQJPD-UHFFFAOYSA-N tetrafluoroethene Chemical group FC(F)=C(F)F BFKJFAAPBSQJPD-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
この発明は、封止樹脂で電子部品素子が封止され、保護
されている封止電子部品の製法に関する〔背景技術〕
近年のエレクトロニクスの進展は、低電力、低発熱素子
を開発する一方で、素子の高集積化が計られ、そのため
、集積化された素子の発熱量が全体として太き(なり、
その結果、高放熱性のパッケージの開発が要求されてき
ている。また、電源回路等のIC化に伴い、パワートラ
ンジスタ、サイリスタ等にはさらに大電力用素子として
の要望が強く、この分野でも高放熱性のパッケージの開
発が要求されてきている。[Detailed Description of the Invention] The present invention relates to a method for producing a sealed electronic component in which an electronic component element is sealed and protected with a sealing resin. As devices were being developed, devices were becoming more highly integrated, and as a result, the amount of heat generated by integrated devices increased (as a whole).
As a result, there has been a demand for the development of packages with high heat dissipation. Furthermore, as power supply circuits and the like are increasingly integrated into ICs, there is a strong demand for power transistors, thyristors, and the like as devices for higher power, and there is also a demand for the development of packages with high heat dissipation in this field.
従来、放熱手段を必要とする素子、例えば、コンピュー
タ用素子には放熱フィンが取り付けられ、パワートラン
ジスタ、サイリスタ等のプラスチックモールド品には放
熱板が設けられていた。プラスチックモールド品に用い
られている放熱板は、素子が装着されているリードフレ
ームと一体成形された金属板であり、プラスチックでモ
ールドされた部分から外部に突出させられていた。この
ように、プラスチックモールド品やセラミックモールド
品において、プラスチックモールドやセラミックモール
ドの熱伝導率を向上させて放熱性を確保するには一定の
限界があり、金属類を放熱手段として使わざるを得なか
った。Conventionally, elements that require a heat dissipation means, such as computer elements, have been provided with heat dissipation fins, and plastic molded products such as power transistors and thyristors have been provided with heat dissipation plates. The heat sink used in plastic molded products is a metal plate that is integrally molded with the lead frame on which the element is mounted, and protrudes from the plastic molded part. In this way, in plastic molded products and ceramic molded products, there are certain limits to improving the thermal conductivity of plastic molds and ceramic molds to ensure heat dissipation, and metals have no choice but to be used as heat dissipation means. Ta.
しかし、そのようにしたとしても、この方法では、素子
に対する放熱板面積をあまり大きくすることができず、
仮に、面積を大きくすれば素子が大型化して、プリント
基板への高密度実装の妨げとなっていた。However, even if this method is used, it is not possible to increase the area of the heat sink for the element very much.
If the area were increased, the device would become larger, which would hinder high-density mounting on printed circuit boards.
この欠点を克服するために、金属基板の加工性を利用し
、素子を凹部に加工した部分に埋め込む方法が、この出
願人により、開発された。In order to overcome this drawback, the applicant has developed a method of embedding an element in a recessed portion by utilizing the workability of a metal substrate.
ところが、金属基板の加工が手間どる上に、基板加工の
際に基板上の回路パターンが切断するという問題をかか
えていた。However, there were problems in that processing the metal substrate was time-consuming and the circuit pattern on the board was cut during board processing.
他方、従来のトランスファー封止法では、樹脂封止する
際に、圧力をかけて成形するために、ボンディングワイ
ヤの断線不良がしばしば起こっていた。これを避けるた
めになされるポツティング法では、型を別に必要とする
という問題もあった。On the other hand, in the conventional transfer sealing method, bonding wires often break due to pressure being applied during resin sealing. The potting method used to avoid this problem also requires a separate mold.
以上の点に鑑みて、この発明は、電子部品素子を樹脂封
止する際に起こるボンディングワイヤの断線不良をなく
し、ボッティング型を必要とせず、放熱性の高い封止電
子部品を簡単に製作することを可能とさせる封止電子部
品の製法を提供することを目的とする。In view of the above points, this invention eliminates the disconnection failure of bonding wires that occurs when electronic component elements are sealed with resin, and easily produces sealed electronic components with high heat dissipation without the need for a botting mold. The purpose of the present invention is to provide a method for manufacturing sealed electronic components that makes it possible to do so.
前記の目的を達成するために、この発明は、基板表面に
回路パターンを有する回路基板が折曲されて凹部が形成
され、この凹部内に前記回路パターンと電気的に繋がれ
ている電子部品素子が装着されている電子部品素子付き
回路基板の前記凹部内に封止樹脂を注入し、前記電子部
品素子を覆うようにする封止電子部品の製法をその要旨
とするこの発明における電子部品素子とは、IC,LS
l、l−ランジスタ、ダイオード等の能動素子、および
、抵抗、コンデンサ、コイル等の受動素子などをいう。To achieve the above object, the present invention provides an electronic component element in which a circuit board having a circuit pattern on the surface thereof is bent to form a recess, and an electronic component element is electrically connected to the circuit pattern within the recess. An electronic component element according to the present invention, the gist of which is a method for producing a sealed electronic component, in which a sealing resin is injected into the recess of a circuit board with an electronic component element mounted thereon so as to cover the electronic component element. is IC,LS
l, l - Refers to active elements such as transistors and diodes, and passive elements such as resistors, capacitors, and coils.
以下に、この発明をその一実施例をあられす図面に基づ
いて詳しく説明する。Hereinafter, one embodiment of the present invention will be described in detail with reference to the accompanying drawings.
第1図に電子部品素子が装着された回路基板の一例を示
す。図にみるように、基板表面にエツチング加工により
回路パターント・・が形成された回路基板2の表面に電
子部品素子(この例ではパワートランジスタ素子)5が
装着されている。FIG. 1 shows an example of a circuit board on which electronic component elements are mounted. As shown in the figure, an electronic component element (power transistor element in this example) 5 is mounted on the surface of a circuit board 2 on which a circuit pattern is formed by etching.
回路基板2は、通常は、アルミニウムまたは鉄からなる
金属板3上にエポキシ樹脂からなる薄い絶縁層4が設け
られたものである。回路パターント・・と電子部品素子
5は、ボンディングワイヤ6・・・ (通常、金ワイヤ
−)で電気的に繋がれている。この例では、回路パター
ン1はエツチング加工により形成されているが、これに
限定されず、例えば、アディティブ法により形成されて
もよい。また、回路パターンと電子部品素子を電気的に
繋ぐ方法は、ワイヤボンディング方式に限定されず、フ
ェースダウンのフィリップチップ方式%式%
このような回路基板lを第1図中に示す一点鎖線に沿っ
て折り曲げて、第2図(a)〜(d)にみるように凹部
7を形成するようにする。このとき、凹部7内に電子部
品素子5が実装されるように折り曲げる。折り曲げ後の
形状は第2図(a)〜(dlに限定されない。第2図(
8)のように三角柱状に折り曲げる場合には、回路パタ
ーン1間の絶縁を保つために、すなわち、凹部7の入口
部において凹部の面が接しないようにするために、絶縁
物質8を挟むようにすることが好ましい。絶縁物質の材
料としてはゴム類が好ましい。絶縁物質8は、凹部7の
入口部を完全に塞ぐようにして挟む必要はないが、後述
するように、凹部7に樹脂を封止する際に、樹脂が入口
部より流出しない程度に塞ぐことが好ましい。The circuit board 2 is usually a metal plate 3 made of aluminum or iron, on which a thin insulating layer 4 made of epoxy resin is provided. The circuit pattern . . . and the electronic component element 5 are electrically connected by bonding wires 6 . . . (usually gold wires). In this example, the circuit pattern 1 is formed by etching, but is not limited to this, and may be formed by, for example, an additive method. Furthermore, the method of electrically connecting the circuit pattern and the electronic component element is not limited to the wire bonding method, but also the face-down Philips chip method. and bend it to form a recess 7 as shown in FIGS. 2(a) to 2(d). At this time, it is bent so that the electronic component element 5 is mounted in the recess 7. The shape after bending is not limited to those shown in FIGS. 2(a) to (dl).
8), in order to maintain the insulation between the circuit patterns 1, that is, to prevent the surfaces of the recesses from coming into contact with each other at the entrance of the recesses 7, the insulating material 8 is sandwiched between the circuit patterns 8 and 8). It is preferable to Rubber is preferred as the material for the insulating substance. The insulating material 8 does not need to be sandwiched so as to completely block the entrance of the recess 7, but as will be described later, when sealing the resin in the recess 7, it should be closed to the extent that the resin does not flow out from the entrance. is preferred.
電子部品素子5は、回路基板2を折り曲げる前に回路基
板2に装着してもよいし、回路基板2を折り曲げた後に
装着するようにしてもよい。The electronic component element 5 may be attached to the circuit board 2 before the circuit board 2 is bent, or may be attached after the circuit board 2 is bent.
第2図中、第1図と同じものには第1図と同じ番号を付
している。以下の図面もこれと同じようにする。In FIG. 2, the same parts as in FIG. 1 are given the same numbers as in FIG. Do the same for the drawings below.
このようにして折り曲げられた電子部品素子付き回路基
板に実装された電子部品素子5を衝撃および湿気から保
護するために樹脂封止を行う。The electronic component elements 5 mounted on the electronic component element-attached circuit board thus bent are sealed with resin to protect them from impact and moisture.
つぎに、樹脂封止の方法について説明する。Next, a resin sealing method will be explained.
その第1の方法として、第3図(alおよび(b)にみ
るような方法がある。図にみるように、この方法は、下
板9上に電子部品素子付き回路基板を置き、凹部7の両
側開口部の一方を下板9で塞ぎ、他方の開口部を注入口
として、その部分より封止樹脂10を注入するようにす
る。第3図fb)の場合には、凹部7の人口部を塞ぐた
めに蓋1)が必要である。通常、封止樹脂にはエポキシ
樹脂を用いるため、下板9の材料はエポキシ系の樹脂に
対し離型性の良いもの、例えば、四弗化エチレン樹脂。As a first method, there is a method as shown in FIGS. One of the openings on both sides is closed with the lower plate 9, and the other opening is used as an injection port, and the sealing resin 10 is injected from that part.In the case of FIG. A lid 1) is required to close the area. Since epoxy resin is usually used as the sealing resin, the material for the lower plate 9 is a material that has good mold releasability compared to epoxy resins, such as tetrafluoroethylene resin.
ポリメチルペンテン等が好ましい。封止樹脂がシリコン
系の樹脂である場合には何を用いてもよい。蓋1)は封
止樹脂が硬化した後に除去してもよいし、取り付けたま
まで使用してもよい。取り付けたままで使用する場合、
蓋1)の材質は絶縁物質である必要がある。Polymethylpentene and the like are preferred. When the sealing resin is a silicon-based resin, any resin may be used. The lid 1) may be removed after the sealing resin has hardened, or may be used with it attached. If you use it with it attached,
The material of the lid 1) must be an insulating material.
第2の方法として、第4図にみるような方法がある。図
にみるように、この方法は、凹部7の入口部を上に向け
るようにして電子部品素子付き回路基板を置き、凹部7
の両側開口部をそれぞれ蓋12.12で塞ぎ、凹部7の
入口部を注入口として、その部分より封止樹脂lOを注
入するようにする。蓋12.12は封止樹脂が硬化した
後に除去してもよいし、取り付けたままで使用してもよ
い。凹部内に充満するよう封止樹脂を充填する必要はな
く、蓋1)および蓋12.12は樹脂封止に必要な大き
さがあればよい。As a second method, there is a method as shown in FIG. As shown in the figure, in this method, a circuit board with an electronic component element is placed with the entrance of the recess 7 facing upward;
The openings on both sides are respectively closed with lids 12 and 12, and the inlet of the recess 7 is used as an injection port, from which the sealing resin 10 is injected. The lid 12.12 may be removed after the sealing resin has hardened, or may be used with it attached. It is not necessary to fill the recess with the sealing resin, and the lid 1) and the lid 12, 12 only need to have a size necessary for resin sealing.
以上は、凹部内に樹脂を注入する方法の一例であって、
これらの方法にだけ限定されるものではない。The above is an example of a method for injecting resin into a recess,
The method is not limited to these methods.
このようにして、樹脂封止された封止電子部品は、第5
図にみるように、回路パターンが形成された基板13上
にリフローはんだ付性によって取り付け、表面実装型と
して使ってもよいし、第6図にみるように、回路基板の
回路パターンが形成された部分にリード14を装着し、
リード挿入型として使ってもよい。In this way, the resin-sealed electronic component is
As shown in the figure, it may be mounted by reflow soldering on a board 13 on which a circuit pattern is formed and used as a surface mount type, or as shown in Fig. 6, a circuit board with a circuit pattern formed thereon may be used as a surface mount type. Attach the lead 14 to the part,
It can also be used as a lead insertion type.
この発明にかかる封止電子部品の製法は、回路基板を折
り曲げて凹部を形成するようにしているため、凹部形成
が容易にでき、さらに、その凹部内に封止樹脂を注入す
るようにしているため、従来のトランスファ封止法と比
べて、無圧で成形することができ、ボッティング法のご
とき型を必要とせず、ボンディングワイヤーの断線不良
を防止することができる。しかも、同じ専有面積の平坦
な形状の電子部品と比べて、放熱面積が広いため放熱性
を向上させることができる。また、従来のパワートラン
ジスタ、サイリスク等では放熱板を持つため、リード挿
入型がほとんどであったが、この発明の製法を用いれば
表面実装型の電子部品が容易に製作できる。In the method for manufacturing a sealed electronic component according to the present invention, since the circuit board is bent to form the recess, the recess can be easily formed, and furthermore, the sealing resin is injected into the recess. Therefore, compared to the conventional transfer sealing method, molding can be performed without pressure, a mold such as in the botting method is not required, and disconnection defects of the bonding wire can be prevented. Furthermore, compared to a flat-shaped electronic component that occupies the same area, the heat dissipation area is wider, so the heat dissipation performance can be improved. Additionally, conventional power transistors, SIRISK, etc. have heat sinks, so most of them are lead insertion type, but by using the manufacturing method of the present invention, surface mount type electronic components can be easily manufactured.
第1図は電子部品素子が実装された回路基板の一例をあ
られす斜視図、第2図(al〜Fdlは同上の回路基板
を折り曲げた後の状態の一例をあられす正面図、第3図
(al、 (b)および第4図はこの発明にがかる封止
電子部品の製法の一実施例をあられす斜視図、第5図は
この発明にがかる封止電子部品の基板への装着方法をあ
られす斜視図、第6図はリード装着状態をあられす断面
図である。
1・・・回路パターン 2・・・回路基板 5・・・電
子部品素子 7・・・凹部 8・・・絶縁物質 1o・
・・封止樹脂
代理人 弁理士 松 本 武 彦
第1図
第3図
(a) (b)
第5図
第6図
手続ネ甫正書(方式)
%式%
2、発明の名称
封止電子部品の製法
3、補正をする者
事件との関係 特許出願人
任 所 大阪府門真市大字門真1048番地
名 称(583)松下電工株式会社
代表者 代表取締役藤井貞夫
4、代理人
昭和60年 3月 6日(発送日60. 3. 26)
6、補正の対象
明細書および図面
7、補正の内容
(1)明細書第10頁第2行の「第4図は」と「この発
明」の間に、「それぞれ」を挿入する。
(2)添付図面中、第3図を別紙のとおりに訂正する。
第3図
(a) (b)Figure 1 is a perspective view of an example of a circuit board on which electronic component elements are mounted, Figure 2 (al to Fdl are front views of examples of the same circuit board after it is bent), Figure 3 (al, (b) and FIG. 4 are perspective views showing an embodiment of the method for manufacturing a sealed electronic component according to the present invention, and FIG. 5 is a perspective view showing a method for mounting a sealed electronic component on a board according to the present invention. Fig. 6 is a cross-sectional view of the lead attached state. 1...Circuit pattern 2...Circuit board 5...Electronic component element 7...Concave portion 8...Insulating material 1o・
...Encapsulating resin agent Patent attorney Takehiko Matsumoto Figure 1 Figure 3 (a) (b) Figure 5 Figure 6 Procedure Nefu official document (method) % formula % 2. Name of the invention Sealed electronic Parts manufacturing method 3, relationship with the amended case Patent applicant location 1048 Oaza Kadoma, Kadoma City, Osaka Name (583) Matsushita Electric Works Co., Ltd. Representative Director Sadao Fujii 4, agent March 1985 6th (Shipping date 60.3.26)
6. Description and drawings to be amended 7. Contents of amendment (1) Insert "respectively" between "Fig. 4" and "this invention" in the second line of page 10 of the specification. (2) In the attached drawings, Figure 3 is corrected as shown in the attached sheet. Figure 3 (a) (b)
Claims (3)
されて凹部が形成され、この凹部内に前記回路パターン
と電気的に繋がれている電子部品素子が装着されている
電子部品素子付き回路基板の前記凹部内に封止樹脂を注
入し、前記電子部品素子を覆うようにする封止電子部品
の製法。(1) A circuit with an electronic component element in which a circuit board having a circuit pattern on the surface of the board is bent to form a recess, and an electronic component element electrically connected to the circuit pattern is mounted in the recess. A method for manufacturing a sealed electronic component, comprising injecting a sealing resin into the recess of a substrate to cover the electronic component element.
角柱状に形成され、前記入口部に絶縁物が挟まれている
特許請求の範囲第1項記載の封止電子部品の製法。(2) The method for manufacturing a sealed electronic component according to claim 1, wherein the recess is formed into a triangular prism shape so that the surfaces of the recess do not touch each other at the entrance, and an insulator is sandwiched between the entrance.
て凹部の開口部を必要なだけ塞ぐ特許請求の範囲第1項
または第2項に記載の封止電子部品の製法。(3) The method for manufacturing a sealed electronic component according to claim 1 or 2, wherein when injecting the sealing resin into the recess, the opening of the recess is closed as necessary except for the injection port.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24766484A JPS61125138A (en) | 1984-11-22 | 1984-11-22 | Manufacture of sealed electron part |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24766484A JPS61125138A (en) | 1984-11-22 | 1984-11-22 | Manufacture of sealed electron part |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61125138A true JPS61125138A (en) | 1986-06-12 |
Family
ID=17166828
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP24766484A Pending JPS61125138A (en) | 1984-11-22 | 1984-11-22 | Manufacture of sealed electron part |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61125138A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2009093109A1 (en) | 2008-01-22 | 2009-07-30 | Nxp B.V. | Method for manufacturing a microelectronic package comprising at least one microelectronic device |
-
1984
- 1984-11-22 JP JP24766484A patent/JPS61125138A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2009093109A1 (en) | 2008-01-22 | 2009-07-30 | Nxp B.V. | Method for manufacturing a microelectronic package comprising at least one microelectronic device |
US8232628B2 (en) | 2008-01-22 | 2012-07-31 | Nxp B.V. | Method for manufacturing a microelectronic package comprising at least one microelectronic device |
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