JPS61120395A - Semi conductor storage device - Google Patents

Abstract

PURPOSE:To eliminate restrictions of the high integration of a sense amplifier part and perform high-speed operation by determining the pattern shape of a memory cell for one bit so that it is long in the prolongation directions of the 1st and the 2nd selection lines and short in the prolongation directions of the 1st and the 2nd bit lines. CONSTITUTION:Transistors (TR) Q1 and Q2 including areas 31 and 32a, and 33 are arrayed linearly in parallel to one side of the area of a triangular capacitor Cs, and their array direction cross the prolongation directions of bit lines BL and RBL or word lines WL and RWL slantingly. The pattern of the memory cell for one bit is long in the prolongation directions of the bit lines BL and RBL as shown by an area encircled with an alternate long and short dash line. Consequently, the width of the sense amplifier part is increased with the same degree of integration. Therefore, there is no restriction of the high integration of the sense amplifier part.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor memory device, and particularly to a dynamic readable programmable memory device that requires a refresh operation.

[Technical background of the invention and its problems] FIG. 3 is a circuit diagram showing the configuration of a typical conventional dynamic read/write (dynamic memory).

In the figure, MC1, MC2, . . . are memory cells, DCl, DC2 are dummy cells, BL, BL are bit lines, CB are bits IBL, B2, L1, . : Existing 11WI, WLl, 'WL2... are word lines, [)W
LI and DWL2 are dummy word lines, SA is a sense amplifier, SE is a sense amplifier enable line, TI and T2 are 5 MOs for column selection controlled by column selection signal CD.
The S transistor, DL, and OL are data lines, and 04JT is an output circuit that outputs data.

Each of the memory cells MC is composed of one capacitor C3 and one transfer gate MC8 transistor QM, and stores information at the "1P level" or "0" level depending on whether charge is stored in the capacitor Cs. It is something to remember. Similarly, each dummy cell D above
C is each composed of one capacitor CD and one transfer gate MOS transistor QD.

However, the charge accumulated in the capacitor C9 in the memory cell MC usually decreases over time due to leakage or the like. For this reason, it is necessary to read out the charge once and rewrite it before the charge completely disappears, thereby accumulating the charge again. Such an operation is called refresh, and dynamic RAM always requires this refresh. For example, a 256-bit dynamic RAM has the limitation that all cells must be refreshed once every 4 milliseconds.

FIG. 4 shows a timing chart when this refresh is performed periodically. In other words, set the normal period ■ and refresh period ■ for data access,
A refresh period (2) is inserted at regular intervals to perform a refresh operation, and normal data access cannot be performed during this refresh period (2). This is because, for example, when the capacitor Cs in the memory cell MC1 is being refreshed, the bit lines BL and 8L contain the data of this capacitor CB, and it is impossible to read data from other capacitors at this time. be.

Therefore, when refresh is performed periodically, even if an access request to this RAM occurs during the refresh period, it has to wait until the refresh is completed, resulting in the inconvenience that the access is equivalently longer. This is a problem because it is incompatible with increasing the speed of RAM.

FIG. 5 is a timing chart showing the operation of the conventional RAM shown in FIG. 3 above. In this RAM, address Add
changes or chip enable signal (not shown)
One cycle is started by activation of . At the beginning of this cycle, first, for example, the signal on the word line WL1 is set to 1'' level, and the corresponding memory cell MC1 is activated.Next, the activated memory cell MCI is connected to one bit line BL. Data is output.

At this time, the signal of dummy word IDWL1 is also set to the "1" level, and cell data is output from dummy cell DC1 to the other pit line 8m. This dummy cell D
Capacitor CD in CI stores in advance an amount of charge that is approximately intermediate between the charge corresponding to data "1" and the charge corresponding to data "OII" stored in cubasitor CB in memory cell MC. Next, sense amplifier enable line S
The signal on the word line WL1 is set to the ``1n level'', the sense amplifier SA is activated, and the potential difference generated between the bit lines 8L and B'L is amplified by the sense amplifier SA.At this point, the signal on the word line WL1 is still Since it is set at the "1" level, the amplified data is written into the original memory cell MCI from which the data was read, thereby performing refreshing.

On the other hand, when outputting data instead of refreshing, after outputting data from one memory cell MC to the bit lines BL, BL as described above, the column selection MOS transistors T1 and T2 are connected to the column selection signal. CD
The bit lines BL and BL are turned on by the bit lines BL and BL, and the data on the bit lines BL and BL are transmitted to the data lines DL and DL. After this, the output circuit OU
T Output $t data Dout. At this time, the output circuit OUT performs waveform shaping, etc., so the hit line 8m,
Data D is output quite late after data is output to BL.
OUT will be output.

Unlike the above case where refresh is performed at regular intervals, refresh in this case places a burden on the RAM user, such as constantly finding the timing, making dynamic RAM difficult to use. .

Therefore, in the course of the present invention, a dynamic RAM was developed that does not require consideration of refresh timing and can also sufficiently shorten access time. This RAM is based on the patent application No. 59-133795.
It is described in the specification and drawings attached to the application of No. 1, and a 1-bit memory cell is configured as shown in the circuit diagram of FIG. That is, the capacitor Cs stores data at the "1n level" and "0" level in a charge storage type, and the data storage node M to which one electrode is connected is connected to the data storage node M via the transfer gate MOS transistor Q1. It is connected to a bit line BL for data access.The gate of the transistor Q1 is connected to a word line WL for data access.Furthermore, the data storage node M is connected to another MOS transistor Q2 for a transfer gate. It is connected to a bit line RBL for data refresh via the data refresh bit line RBL.

The gate of the transistor Q2 is connected to a data refresh word line RWL. Further, the other electrode of the capacitor CB is connected to a predetermined potential, for example, a power supply voltage application point.

By providing two sets of bit lines and word lines for one memory cell in this way, even if one bit line BL is occupied by another memory cell for data access, the other bit line BL can be used for data access. Capacitor C8 can be accessed using bit line R8L. Therefore, at any time when capacitor CB in that memory cell is not being accessed, this capacitor can be refreshed using bit IIRBL and word line RWL.

Further, in the case where the capacitor Cs itself is being accessed, this access serves as a substitute for refreshing, so there is no need for refreshing.

FIG. 7 is a pattern plan view when the memory cell shown in FIG. 6 is actually integrated into an integrated circuit. This memory cell is constructed using, for example, a semiconductor substrate containing P-type impurities. In the figure, 11a, Ilb, and 11c are the transistors Q11. This is an N1 type semiconductor region containing N type impurities, which becomes the source and drain regions of Q2 and the region of the capacitor Cs.

A capacitor plate 12 of the capacitor Cs made of a first @th polycrystalline silicon layer is formed on the surface of the N+ type semiconductor region 11C via a relatively thin insulating film (not shown). This capacitor plate 12 is connected to a predetermined potential, such as a power supply voltage application point. Above N4″
The word line WL is formed by a second FJ-th polycrystalline silicon layer between the type semiconductor regions 11a and 11c,
Similarly, between the N+ type semiconductor regions 11C and 11b, the word line RW is formed by a second polycrystalline silicon layer.
L is formed. The word lines WL and RWL are formed to extend in the same direction, and furthermore, the word lines WL and RWL are formed to extend in the same direction.
The bit lines BL and RBL, which are made of a material such as aluminum or polycrystalline silicon, are formed in a direction intersecting the extending direction of L and RWL. The bit line E3L and the N+ type semiconductor region 11a are connected through a contact hole 13, and the bit line RBL and the N+ type semiconductor region 11a are connected to each other through a contact hole 13.
It is connected to the + type semiconductor region 11b through a contact hole 14. And a pattern similar to this is bit line B
They are arranged continuously in the extending direction of L and R8L.

In a memory cell having a pattern as shown in FIG. 7, two transistors Q1 and Q2 are arranged along the extending direction of bit lines 8L and RBL, and the pattern of the memory cell for one bit is similar to that of bit lines BL and RBL. The word line WL is long in the direction of extension of the word line WL.

It is designed to become shorter in the direction of extension of the RWL.

FIG. 8 is a circuit diagram of a dynamic RAM constructed using memory cells having a pattern as shown in FIG. 7. This RAM is provided with a plurality of memory cell groups 21, and between a pair of adjacent memory cell groups 21, sense amplifiers SA for data access and sense amplifiers R8A for refresh are alternately arranged. Each of the plurality of memory cell groups 21 includes a data storage capacitor Cs, two MOS transistors Q1 . Q2: Does it consist of two bit lines 8m and RBL or BL and RBL, and two word lines WL and RWI-? ! several memory cells MC, a capacitor Co, and two MOS transistors QD1. A dummy cell DC consisting of QD2, a capacitor OR, and a refresh dummy cell RC consisting of two MOS transistors QR1 and 0R2 are provided.

In each memory cell group 21, one end of one transistor QDI in the dummy cell DC is connected to the bit line BL, one end of the other transistor QD2 is connected to the ground potential application point, and the gate of the transistor QD1 is connected to the dummy word line DWLI. Furthermore, the gates of the transistors QD2 are respectively connected to the dummy word line DWL2. Furthermore, in this memory cell group 21, one end of one transistor QR1 in the refresh dummy cell RC is connected to the ground potential application point, one end of the other transistor QR2 is connected to the refresh bit line RBL, and the transistor QRI has one end connected to the ground potential application point. The gate of the transistor QR2 is connected to the word line RDWL2, and the gate of the transistor QR2 is connected to the dummy word line RDWLI.

The bit lines BL and 81 of a pair of adjacent memory cell groups 21 are connected to each sense amplifier SA, and each sense amplifier SA generates a signal between the bit lines based on a signal from a sense amplifier enable line SE. Data is detected by amplifying the potential difference. The data detected here is transmitted to the column selection MOS transistor T11. which is controlled by the column selection signal CD. Data lines DL and D via T12, respectively.
The signal is output to L and is roughly supplied to the output circuit OUT.

The bit lines RBL and RBL of a pair of adjacent memory cell groups 21 are connected to each refresh sense amplifier R8A, and each sense amplifier [[S△] The potential difference generated between the lines is amplified and output to both bit lines again. Note that CF3 and CR day are the parasitic capacitances existing in the bit line BL and the refresh bit line RBL, respectively.

In this way, in the RAM of FIG. 8, it is necessary to provide at least one sense amplifier SA and one refresh sense amplifier R8A for each column.

For this reason, word lines WL and RW of the pattern of the sense amplifier SA part and the refresh sense amplifier R8A part when such a RAM is actually integrated circuit.
The length in the extending direction of L must be equal to or less than the length in the extending direction of the word lines WL and RWL of the pattern of the memory cell MC portion, and when such a RAM is highly integrated. However, some problems arise. First, there are strong restrictions on the circuit configurations of the sense amplifier SA and the sense amplifier R3A for refresh. When integrated circuits are implemented, the word line WL of the sense amplifier portion.

The length of the RWL in the extending direction (hereinafter referred to as the pattern width) is determined by the pattern width of the memory cell portion. Therefore, when increasing the degree of integration by reducing the size of memory cells, the width of the pattern of the sense amplifier portion is also reduced accordingly. However, since the circuit configuration of the sense amplifier is more complicated than that of the memory cell, the limit of reduction in pattern width direction is determined by the sense amplifier.

Further, as shown in FIG. 7, in the vertically elongated memory cell pattern, the bit lines BL and BL are long, so that the bit lines BL and BL are long.

The value of the capacitance 1ift Cs parasitically generated in each BL becomes large, making it impossible to achieve high-speed operation of the sense amplifier SA.

Also, the sense margin at the time of data reading is the capacitor Cs in the memory cell MC and the bit $1i1BL,
BT's parasitic capacitance I CEl is determined by the ratio C8/CB, which is 1
．． If the bit lines BU and BL are long, this ratio Cs/C
As the value of e becomes smaller, the sense margin also becomes smaller.
This increases the possibility that malfunctions will occur.

[Object of the Invention] The present invention has been made with the above considerations in mind, and its purpose is to provide a semiconductor memory device that is not subject to the constraints of high integration due to the sense amplifier section and can realize high-speed operation. It is about providing.

[Summary of the Invention] In order to achieve the above object, in the semiconductor memory device of the present invention, one electrode of a capacitor that dynamically stores information is connected to a predetermined potential application point;
bit lines are arranged to extend in the same direction, and first and second selection lines are arranged to extend in a direction crossing the extension direction of the first and second bit lines, and the first MOS The source and drain of the transistor are inserted between the other electrode of the capacitor and the first bit line, the gate thereof is connected to the first selection line, and the source and drain of the second MOS transistor is inserted between the other electrode of the capacitor and the first bit line. is inserted between the other electrode of the capacitor and the second bit line, and its gate is connected to the second selection line to form a memory cell for one bit. The pattern shape of the memory cell is configured to be long in the extending direction of the first and second selection lines and short in the extending direction of the first and second bit lines.

[Embodiments of the invention] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

In the semiconductor memory device of the present invention, when a plurality of memory cells as shown in FIG. 6 are used to form an integrated circuit, the pattern shape is configured to be that in the pattern plan view shown in FIG. There is.

This memory cell is constructed using, for example, a semiconductor substrate containing P-type impurities. In the figure, a region 31 is N, which is one of the source and drain regions of the transistor Q1.
This is an N+ type semiconductor region containing type impurities. Further, the region 32a is an N1 type semiconductor region containing an N type impurity and serves as the other of the source and drain regions of the transistor Q1 and one of the source and drain regions of the transistor Q2, and is formed continuously with the region 32a. Territory! 43
2b is a triangular N+ type semiconductor region containing N type impurities and corresponding to the region of the capacitor C9. Further, the Ili region 33 contains N4, which is the other of the source and drain regions of the transistor Q2, and contains N-type impurities.
'' type semiconductor region. On the surface of the triangular N+ type semiconductor region 32b corresponding to the region of the capacitor Cs, a 1H polycrystalline silicon layer is formed with a relatively thin insulating film (not shown) interposed therebetween. A capacitor plate 34 of the capacitor CB is formed by the capacitor CB.The capacitor plate 34 is connected to a predetermined potential, for example, a power supply voltage application point.Between the N+ type semiconductor regions 31 and 328,
The word line WL is formed by a second layer of polycrystalline silicon, and similarly, the word line RWL is formed by a second layer of polycrystalline silicon between the N+ type semiconductor regions 32a and 33. has been done. The word lines WL and RWL are formed to extend in the same direction, and the bit line BL made of a material such as aluminum or polycrystalline silicon, RBL (or BL, RB
L) is formed. The bit line BL and the N+ type semiconductor region 31 are connected through a contact hole 35, and the bit line RBL and the N+ type semiconductor region 11!3
3 through a contact hole 36.

Then, a pattern similar to this is rotated alternately to the left and right by 120 degrees, for example, and the bit line B
They are arranged continuously in the extending direction of L and RBL (or 8L and RBL).

As shown here, the areas 31.32a and 3
3, said transistor Q1. Q2 is linearly arranged parallel to one side of the triangular capacitor CB region, and the arrangement direction is the bit lines BL, RBL (or BL, RBL) or the word lines WL and RWL. The direction is perpendicular to the direction of extension. The pattern size of the memory cell for one bit is short in the extension direction of the bit lines BL, RBL (or BL, RBL) and in the extension direction of the word lines WL, RWL, as shown in the area surrounded by the dashed line in the figure. It is made to be longer in the direction.

Therefore, when compared with the pattern in Figure 7 above,
The width of the sense amplifier portion can be increased for the same degree of integration. Therefore, in the case of high integration, the pattern of the sense amplifier part in the one shown in FIG. 7 is the bit line BL,
Even if it does not fit between RB'L (or BL, RBL), the one in FIG. 1 can sufficiently fit it.

By adopting such a pattern shape, the length of the bit lines BL, R8L (or BL, RBL) is inevitably shortened, and the parasitic capacitance Ic existing there is reduced.
The values of e and CRB become smaller.

Since the value of the capacitor Cs of a memory cell is almost proportional to the cell area, the ratio Cs/Ce or C3I/CRB 1ii (CB and 08th are almost the same value) is large for the same degree of integration. , this increases the sense margin during reading. Also, CB and CR
Since the value of B is small, the time required to charge and discharge the bit lines 8'L and RBL (or BL and RBL) is shortened, thereby realizing high-speed operation.

Furthermore, since the arrangement direction of transistors Q1 and Q2 is diagonal to the extending direction of bit lines BL, RB'L (or BL, ReL) or word lines WL and RWL, the gate lengths of these transistors can be increased. As a result, the sources of both transistors,
The withstand voltage between drains is increased and reliability is improved.

Furthermore, since the pattern size of the memory cell is made shorter in the extending direction of the bit lines BL, R8L (or BL, RBL) and longer in the extending direction of the word lines WL, RWL, the bit lines BL, RBL (or BL, RBL-) can be spaced apart, and as shown in the block diagram of the modified example in FIG. 2, the bit line BL'
, RBL (or BL, RBL) can be provided with another wiring SL made of aluminum or the like. If this wiring SL is used as a data line, data detected by a plurality of sense amplifiers SA for data access can be selectively supplied to the output circuit OUT via this data line SL for column division. This eliminates the need for extra area for data lines, allowing the chip size to be reduced by that amount. Note that the same effect can be obtained even if this wiring SL is used for another purpose.

[Effects of the Invention] As described above, according to the present invention, it is possible to provide a semiconductor memory device that is not limited by the high degree of integration due to the sense amplifier portion and can realize high-speed operation.

[Brief explanation of the drawing]

FIG. 1 is a pattern plan view showing the configuration of an embodiment of a semiconductor memory device according to the present invention, FIG. 2 is a block diagram showing the configuration of a modified example of the above embodiment, and FIG. A circuit diagram showing the structure of the RAM, Fig. 4 is a timing chart when refresh is performed periodically with this dynamic RAM, Fig. 5 is a timing chart showing the operation of the RAM shown in Fig. 3 above, and Fig. 6 is an improved version of the RAM. RA
A circuit diagram showing a memory cell for 1 bit of M, FIG. 7 is a pattern plan view during the process of this invention when actually integrating the memory cell shown in FIG. 6 above, and FIG. 8 is a circuit diagram of a dynamic RAM configured using memory cells having a pattern as shown in FIG. 7. FIG. Os...Capacitor, Ql, Q2...MoS transistor, BL, R''B L...Bit line, WL
, RWL...word line, 31.32a, 32b
, 33-N+ type semiconductor region, 34... Capacitor plate, 35.36... Contact hole. Applicant's agent Patent attorney Takehiko Suzue 3rd s 4th v! J Fig. 5 out Fig. 7

Claims (4)

[Claims] (1) A capacitor whose one electrode is connected to a predetermined potential application point and which dynamically stores information; first and second bit lines extending in the same direction; and the first and second bits. first and second selection lines extending in a direction crossing the line extension direction; a source and a drain are inserted between the other electrode of the capacitor and the first bit line; is connected to the first selection line, and a source and drain are inserted between the other electrode of the capacitor and the second bit line, and the gate is connected to the second selection line. A 1-bit memory cell is configured by a second MOS transistor connected to the 1-bit memory cell, and the pattern shape of the 1-bit memory cell is long in the direction of extension of the first and second selection lines and is long in the direction of extension of the first and second selection lines. A semiconductor memory device characterized in that the second bit line is configured to become shorter in the extending direction. (2) The first and second MOS transistors are arranged in a straight line, and the direction of the arrangement is relative to the extending direction of the first and second bit lines or the first and second selection lines. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is arranged in oblique directions. (3) The semiconductor memory device according to claim 1, wherein a signal line parallel to the first and second bit lines is provided between the first and second bit lines. (4) the pattern shape of the capacitor is triangular;
The first and second
2. The semiconductor memory device according to claim 1, wherein MOS transistors are arranged.