JPS61117635A - Virtual memory control method - Google Patents

Abstract

PURPOSE:To improve the processing speed by providing a dividing means which determines whether CPU information should be saved and restored to restart an instruction interruption point or an instruction should be executed again from the start when an exception of address conversion occurs. CONSTITUTION:An instruction executing part 1 is provided with an address conversion exception processing part 4, and the processing part 4 consists of an address conversion exception detecting part 5, a storage dividing part 6, etc. This dividing part 6 determines whether CPU information should be saved and restored or not in accordance with the position of the occurrence of the exception of address conversion or the number of accesses of the instruction to a main storage MS 20. A storage indication flag l22 is provided in a fixed area 21 of the MS 20, and the flag 22 is turned on if CPU information is saved and restored, and the flag 22 is turned off if this processing is omitted. Thus, the processing speed is improved to perform efficient control.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a virtual memory control method, particularly a virtual memory control method in a data processing device that employs a microprogramming control method. The present invention relates to a virtual memory control method that allows restarting to be performed efficiently depending on the type of instruction, etc.

[Conventional technology and problems]

FIG. 5 shows an example of processing using a conventional virtual storage control method.

In the case of the virtual memory control method, the segment table and page table are generally indexed in the process of converting a logical address to a real address, and if the corresponding entry in the table is invalid (invalid), the page is・
Generates an address translation exception program interrupt as a fault or segment 1-fault.

In the case of a central processing unit (CPU) that processes each instruction using a microprogramming control method, as shown in FIG. , the central processing unit is
Through process 71, information such as its own registers and address stack is stored in a predetermined fixed area on the 2MS. Then, through process 72, the program state word (PSW)
) turns on the instruction abort indication bit.

Causes a program interrupt.

When the PSW is changed by a program interrupt, the page management task runs, and the page management task first saves the contents of the MS fixed area to an area within the task in process 73. Thereafter, through process 74.

The page is rolled out and rolled in as necessary to enable the invalid display of the address related table, and in step 75, the information previously saved in the area within the task is doored to the MS fixed area. Then, a load PSW (LPSW) instruction is issued to return from the first interrupt.

When the instruction interrupt indication bit of successive psw among the psw instructions is on, processing 76 is performed.

The contents of the MS fixed area are reset to registers, address stacks, etc. in the CPU, and processing 77 is performed.

Turn off the PSW command interruption display focus. As a result, the instruction is resumed from where the instruction was interrupted. Processing 78
In the MS access in , since the table is valid, processing of the interrupted instruction can be continued.

By the way, in the case of instruction control using a microprogram,
One machine language instruction is processed by a series of microinstructions such as instruction fetch, address calculation, main memory read, and general register cent.

For example, in a long character string transfer command, etc.,
Microinstructions will be executed. Figure 5 Illustrated process 7
In No. 1, the CPU information is saved in a fixed area of the MS in order to avoid duplication of processing by restarting execution from unprocessed microinstructions.

However, according to the conventional power formula 1, even when a conversion exception occurs during instruction fetch, the process 71 shown in FIG.
．． Processing 73. CPU 11 by processing 75 and processing 76
This means that the process of saving and restoring fllli must be executed. In the case of instruction fetish, since the instruction processing has just started, the above series of CPUs
Saving/restoring information is unnecessary, and there is a problem in that the processing time required to restart from the interrupted point becomes long. Also,
Not only in the case of instruction fetch, but also when a conversion exception occurs in the first or second operand.

Depending on the type of instruction, it may be better to start over from the beginning of the instruction without saving/restoring the CPU information.

In some cases, processing speed may be improved.

Means for Solving Problem C] The present invention aims to solve the above problem. When an address translation exception occurs, it is better to save/restore CPU information and restart from the instruction interruption point, or By providing a means to determine whether it is better to re-execute the process from the beginning, the processing speed is improved. In other words, the virtual memory control method of the present invention is a virtual memory control method in which each instruction processed by a central processing unit is executed by microprogramming, and when an address translation exception is detected, information regarding the state of the central processing unit at that time is stored in the main memory. means for determining whether or not to store information in the above fixed area based on the interruption point of the instruction being executed and/or the instruction type; storage display means for storing information as to whether information is stored in the above fixed area; and address conversion. A command means for separating and transmitting the information to be moved by the storage and display means when moving the contents of the fixed area to another area in the main memory in interrupt processing due to exception detection; a command means for separating and transferring the information to be restored by the storage and display means when restoring the information to the fixed area; and a command means for indicating that the storage and display means has stored the information in the fixed area when the instruction is resumed after interruption. When the instruction is restarted according to the information regarding the state of the central processing unit stored in the fixed area, and when the storage display means indicates that no information is stored in the fixed area, the instruction is resumed from the beginning of the interrupted instruction. It is characterized by having the means.

[Effect]

In view of the shortcomings of the conventional method in which CPU information is typically stored in the MS fixed area, the present invention separates the first order (■) and (2), and thereby performs processing related to address translation exceptions that is optimal from the viewpoint of processing speed. I try to choose.

■ If the cause of the address translation exception is an instruction fetch, or if the type of instruction requires a small amount of access to the main memory, restart from the instruction fetch.

■ If an address conversion exception occurs in the first operand/second operand, and the instruction is a transfer or main memory comparison instruction,
If the number of accesses to the main memory is large, as in the conventional example, execute the CPU information save/restore process,
Resumes the instruction from the point where it left off.

That is, in the case of the present invention, it is determined whether or not to store CPU information in the MS fixed area when an address translation exception occurs.

9. For example, a storage display flag is provided on a fixed area, and when a process for saving CPU information is executed, this storage display flag is turned on. Also, when not executing, the storage display flag is turned off. When this flag is off.

By returning the instruction address (IA) of the current PSW to the instruction start address, execution starts from instruction fetch when restarting. Embodiments will be described below with reference to two drawings.

〔Example〕

FIG. 1 is a block diagram of the configuration of an embodiment of the present invention, FIG. 2 is a diagram explaining the processing of the address translation exception handling section shown in FIG. 1,
FIG. 3 is a diagram explaining the processing of the illustrated page management section in FIG. 1;
FIG. 4 is a diagram illustrating the processing of the instruction resuming unit shown in FIG. 1.

In the figure, 1 is an instruction execution unit that executes machine language instructions using a microprogram in the central processing unit;
2 is a program state word (PSW).

3 is an instruction interruption display bit provided in PSW2, 4 is an address translation exception handling unit that processes an address translation exception when it occurs, and 5 is a storage control unit (not shown).
6 is a storage section that determines whether or not to save CPU information. 7 is a storage section that stores CPU information in a fixed area of the MS. 8 is a storage display setting section that turns on or off the storage display flag; 9 is an interruption display section that turns on instruction interruption display bit 3;
10 is an interrupt generation unit that generates a program interrupt;
Reference numeral 1 denotes an instruction restart unit activated by the LPSW instruction upon return from an interrupt, 12 a storage display determination unit that determines on/off of a storage display flag, and 13 a CPU information restoration unit that reads CPU information from a fixed area of the MS and restores it. , 14
represents an instruction fetch unit that fetches instructions according to the instruction address held by PSW2.

Further, reference numeral 20 denotes a main memory (MS), 21 a fixed area in the main memory 20, 22 a storage display flag that is turned on when CPU information is stored in the fixed area and turned off when it is not stored, and 23 a CPU A CPU information storage section 24 in which information is saved is an intra-task area to which a unique space is allocated for each task.

30 is a page management unit that performs virtual memory control in the operating system; 31 is a storage display determination unit; 32 is an information transfer unit that transfers information from the CPU information storage unit 23 to the intra-task area 24; and 33 is a page of virtual memory. Paging processing unit that rolls in/rolls out 3
Reference numeral 4 represents an information restoration unit that transfers information from the intra-task area 24 to the CPU information storage unit 23, and 35 represents an external page storage unit provided in a magnetic disk device or the like.

In the present invention, information such as registers and address translation exceptions is stored in the CPU information storage unit 23.

C
It is possible to select whether or not to perform processing such as writing back information to the P IJ information storage unit 23, storing CPU information from the CPU information storage unit 23, etc., depending on the position where an address translation exception occurs and the type of instruction. It has become. Therefore 1
For example, a storage display flag 22 is provided in the fixed area 21,
When the CPU information saving/restoring process is performed, the storage display flag 22 is set to ON, and when the CPU information saving/restoring process is omitted, the storage display flag 22 is set to OFF.

The storage division section 6 determines whether or not to save/restore CPU information depending on the position where an address translation exception occurs or whether the instruction accesses the main memory 20 frequently. It is something that separates. When the CPU information is saved and the storage display flag 22 is turned on by the storage display setting section 8, the information transfer section 32 and the information restoration section 3
4 is.

Information is transferred between the CPU information storage unit 23 and the intra-task area 24. Further, the instruction restart unit 11.

The CPU information source section 13 stores the CPU information from the CPU information storage section 23, and resumes the interrupted instruction in the same manner as before.

When the storage section 6 determines that the processing by the CPU information saving section 7 is unnecessary, the storage display setting section 8
The storage display flag 22 is set to OFF. In this case, C
Information is not transferred from the PU information storage unit 23 to the intra-task area 24, and when the instruction is restarted, the instruction restart unit 11
The instruction is re-executed from the instruction start address set in SW2. That is, the instruction fetch unit 14 is activated.

Processing starts from instruction fetch.

FIG. 2 shows the processing of the address conversion exception handling unit 4 shown in FIG. 1 in the form of a flowchart.

When an invalidity of the address related table is detected in the MS access by the process 40 shown in FIG. 2, the address translation exception handling unit 4 is activated.

The address translation exception processing unit 4 first determines in process 41 whether a translation exception has occurred at the instruction fetch stage. If it is not an exception in instruction fetch, the process moves to step 42, and by referring to the instruction code, it is determined whether the instruction is an instruction that requires information storage. The necessity of storing information is determined in advance depending on the type of command.

If the instruction requires storing information, the information is saved in the CPU information storage section 23 shown in FIG. 1 in step 43. Then, in process 44, the storage display flag 22 is set on.

In the judgment of process 41, when an exception in instruction fetch is detected, or by process=12,
When it is determined that information storage is unnecessary, process 45
The instruction start address is set in the instruction address (IA) field of the PSW, and the storage display flag 22 is set in the process 46.
Turn off.

Finally, in step 47, the instruction interrupt display and node 3 in the PSW 2 shown in FIG. 1 are turned on to generate a program interrupt.

Due to a program interrupt, the illustrated page management section 30 in FIG.
is started. The page management unit 30 performs processing as shown in FIG. 3, for example.

In the present invention, for example, an instruction S for executing processes 50 to 52 illustrated in the third diagram, and an instruction R for executing processes 54 to 56 are provided.
are prepared in advance. The page management unit 30 first issues the command S. This instruction S performs the following processing. First, in process 50, it is determined whether the storage display flag 22 is on or off, and if it is on, information is transferred from the CPU information storage unit 23 to the intra-task area 24 in process 51. If it is off, the transfer in this process 51 is omitted. Then, in process 52, the storage display flag 22 is transferred to the area within the task.

Thereafter, in process 53, the page management unit 30 performs page rollout/rollin processing and allocates a real address to the page that includes the address that caused the conversion exception.

Next, when command R is issued, the following processing is performed by command R. In order 6R, first, in process 54, it is determined whether the storage display flag transferred to the area within the task in process 52 is on/off. When the flag is on, processing 55 transfers the information previously transferred to the area within the task.
It is returned to the CPU information storage section 23. This process 55 is not performed when the storage display flag is off. Then, through process 56, the storage display flag saved in the task is
The storage display flag 22 on the fixed area 21 is displayed on the helis door.

After that, if you issue the LPSW command.

Since the instruction interruption display bit 3 shown in FIG. 1 is on, the instruction restart unit 11 is activated.

The instruction resuming unit 11 performs two processes, for example, as shown in FIG. That is, first, in process 60, it is determined whether the storage display flag 22 is on or off. If it is on, processing 61 causes the CPU information storage section 23 to
Performs information storage. Then, in step 62, the instruction interruption indication bit 3 is turned off, and in step 63, the address where the address translation exception occurred is accessed. Since the table is made valid by assigning real addresses, processing of the interrupted instruction can be continued from the point of interruption. This processing route is.

This is substantially the same as before.

On the other hand, as determined by the process 60, the storage display flag 22
If it is detected that psw is off, the instruction interruption display bit 3 is turned off in step 64, and then the instruction indicated by psw is re-executed from the beginning.

〔Effect of the invention〕

As explained above, according to the present invention, processing time can be reduced by that amount for instructions that do not require saving/restoring CPU information to the MS fixed area and transferring information to the intra-task area. .

Further, processing time can be similarly expected to be shortened with respect to address translation exceptions that occur during instruction fetching. Therefore, according to the present invention, it is possible to provide a more efficient virtual storage control method than the conventional one by using relatively simple means.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the configuration of an embodiment of the present invention, FIG. 2 is a diagram explaining the processing of the address translation exception handling section shown in FIG. 1,
FIG. 3 is a diagram explaining the processing of the illustrated page management section in FIG. 1;
FIG. 4 is a diagram for explaining the processing of the instruction resuming unit shown in FIG. 1, and FIG. 5 shows an example of processing by the conventional virtual storage control system. In the figure, 1 is an instruction execution unit, 2 is a PSW, 3 is an instruction interruption display bit, and 4 is an address conversion exception handling unit. 6 is a storage section, 7 is a CPU information saving section, 8 is a storage display setting section, 11 is an instruction restart section, 12 is a storage display judgment section,
20 is a main memory, 21 is a fixed area, 22 is a storage display flag, 30 is a page management section, and 33 is a paging processing section. Patent applicant Fujitsu Co., Ltd. Representative Patent Attorney Hiroshi Mori 1) (1 other person) $ 2 Figure

Claims (1)

[Claims] In a virtual memory control method executed by microprogramming for each instruction processed by a central processing unit, when an address translation exception is detected, it is determined whether information regarding the state of the central processing unit at that time is stored in a fixed area on main memory. means for separating the instructions according to the interruption point and/or instruction type; storage and display means for storing information as to whether or not information has been stored in the fixed area; a command means for separating and transferring the information to be moved by the storage/display means when moving the information to another area in the main memory; a command means for separating and transferring information to be restored by the storage and display means, and a central processing unit that stores the information in the fixed area when the storage and display means indicates that the information has been stored in the fixed area when the instruction is resumed after interruption; and means for restarting the instruction from the beginning of the interrupted instruction when the storing and displaying means indicates that no information is stored in the fixed area. Virtual memory control method.