JPS61117476A - Signal synthesizer - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal synthesizer for generating pulses that simulate the characteristics of echo pulses generated during ultrasound scanning techniques.

Such pulses can be used to calibrate a device for processing the output of an ultrasound transducer.

According to the present invention, means for generating a high-frequency pulse train, means for generating an envelope having a rising edge, a falling edge and a flat area between these edges, and a rise timing of said edge of said envelope; means for selectively changing the fall timing; means for changing the duration of the envelope; multiplying the envelope by the high-frequency pulse train on the one hand and by a signal of substantially zero amplitude on the other; and means for combining said output signals to generate a calibration signal substantially unaffected by said transmitted component. .

Preferably, means are provided for shifting the phase of the pulse train with respect to the envelope.

As the multiplication means employed in the present invention, Analog Devices
A dual harmonic multiplier, such as the manufactured AD 539 device, can be used. By using elements such as those described above, it is possible to accurately perform multiplications that store high-frequency signals, and to ensure that the calibration signal is not affected by transmitted components without any filtering. .

Means for varying the amplitude of the calibration signal may be provided, for example attenuating means connected to the output of the coupling means, which are switched on and off.

The combining means may be a differential amplifier that subtracts the output of one multiplier from the other.

In the following, the invention will be described by way of example with reference to the drawings.

Please refer to FIGS. 1 and 2. Fixed frequency 20MHz
An oscillator 10 is connected to a counter 12. This counter 12 is connected to a shift register 14 and functions to generate four 5 MHz outputs 16. The four outputs are 90° phase shifted with respect to some other output. Any of the outputs 16 may be selected by a phase selection circuit 18, such as a manually scannable switch located in a control console. The selected output includes a buffer amplifier 20, an analog switch circuit 22 (e.g., a FET switch) and a 5MHz
The signal is input to a double multiplier (FIG. 1B) via a buffer/low-pass filter section 24 that blocks frequencies above .

The output of counter 12 is provided to driver chain 26. This driver chain 26 provides a gating pulse on line 28, which determines the gating period, on line 30.
Give three pulse trains on top. The three pulse trains are different divisions of the gating pulse, for example there are 1.2.4 pulses each within the gating period (see Figures 2A, 2B, 2C and 2D). ).

Figure 2A represents a gating pulse, and it can be seen that the other three waveforms are divisors of this gating pulse. The pulse train on line 30 determines whether the generated calibration signal simulates a single echo response or an element echo response, i.e. 1.2 or 4 in the illustrated embodiment. Controls whether echo is simulated.

Selection of single or multiple echo simulations
This is done by circuit 32. The circuit 32, which may be comprised of a plurality of manually operable switches, sends a signal on a selected one of the lines 30 to a circuit 34 to control the generation of the simulated pulse envelope.

2E, 2F and 2G illustrate the waveforms provided to circuit 34 according to the selection. Control circuit 34 also receives inputs from circuits 36.38.40. These inputs determine other parameters of the pulse envelope: the duration of the envelope (circuit 36), the pulse rise timing (circuit 38), and the pulse fall timing (circuit 40). Circuits 36, 38 and 40 each include manually settable switch means for adjusting each parameter.

In the illustrated embodiment, circuit 32 is also used to control the relative timing of the simulated echo pulses with respect to the leading edge of the gating pulse, i.e., to simulate echoes returning from targets at different locations. can do. In this regard, it can be seen that the tip of the pulse train on line 30 (see FIGS. 2B and 2D) divides the gating pulse (FIG. 2A) into one, two, or four. Therefore, the tip of the echo pulse increases the timing by 7 with respect to the tip of the gating pulse. However, improvements can be made to separate the pulse timing function from the single/multiple echo selection circuit 32.

The envelope' control circuit 34 has a charging and discharging capacitor that controls the rise timing and fall timing of the envelope. The circuit 38.40 can have multiple resistors (or combinations of resistors).

The plurality of resistors can be selectively coupled to the capacitor to change the charging/discharging CR time constant, thereby adjusting the rise and fall timing of the envelope. Circuit 36 generates a timing pulse having a duration that determines the duration of the flat portion of the envelope.

The output side of the capacitor is connected via a buffer section 44 to a double multiplier (FIG. 1B). Operation of the analog switch section 22 is controlled by the envelope control section so that the switch is closed only during the duration of the envelope. The envelope signal generated at the output of the circuit 34 is input to a comparator 46 . This comparator 46 is also connected to a potentiometer. Circuit 48 causes the amplitude of the envelope to be set to a selected fixed value.

In operation, only when envelope generation is initiated by a pulse from selection circuit 32, charging of the capacitor begins according to a conventional exponential curve, with a time constant determined by circuit 38. Therefore, the output of circuit 34 follows the voltage level of the capacitor, and this output is then compared by circuit 46 to a predetermined amplitude set by a potentiometer.

When the capacitor voltage level reaches a preset value, the capacitor is disconnected and prevented from further discharging. A pulse is then generated from circuit 36 and maintained in this state for the desired time. During this time the output of circuit 34 is maintained substantially constant at an amplitude value preset by circuit 48. After this time has elapsed, in response to the trailing edge of the pulse provided by circuit 36, capacitor 4
0, the capacitor begins discharging at a preset time constant. The dropped voltage level is compared to a zero reference level by circuit 46, and when the zero reference level is reached, comparator 46 generates an output to reset the envelope control circuit and prepare for the next cycle of envelope generation.

The envelope generated and fed to the multiplier must not be negative. This is ensured by buffer 44. As shown in FIG. 2H, the envelope can be seen to consist of a rising edge 50, a falling edge 52, and a flat portion 54 of constant amplitude. The rising and falling edges have an exponential nature, but the capacitor (
The rising and falling edges are essentially straight lines, since only the parts of the exponential curve associated with the resistance combination (and resistor combination) that do not have a significant effect are used.

The turning point 56 is generally of a discontinuous nature and is therefore a potential source of high frequency components during subsequent processing of the multiplier. It will be appreciated that FIG. 2M shows the waveform of a 5 MHz signal, which is limited by a control signal applied to the switching section via line 60 to a time corresponding to the duration of the envelope. right.

This is illustrated by the waveform shown in FIG.

This FIG. 21 illustrates the envelope of a 5 MHz signal without showing details of the high frequency signal.

Reference is now made to FIG. 2B. Line 62. The signal on 64 is applied to a dual harmonic multiplier 66.
It is composed of circuit components made by 1ces).

This multiplier has two sets of multiplication inputs: 68°70 and 72.
74 and an output cuff of 6.78.

Output cuff 6.78 gives the product of the signal applied to human power 68.70 and the signal applied to human cuff 2.74, respectively. The AD539 device has the ability to accurately multiply signals up to 60 MHz with signals up to 5 MHz. As shown, input 68.72 is 5
Can handle signals up to QMHz, human cuff 0.74
can handle signals up to 5MHz. In the illustrated embodiment, the envelope signal is applied to input cuff 0.74, the 5 MHz carrier signal is applied to human power 68, and human cuff 2 is connected to ground.

As mentioned above, the envelope (Figure 2H) has discontinuities. This discontinuity occurs during multiplication of significant and harmful high frequency transmission components. This high frequency transmission component is offset to some extent by the fact that the human cuff 0.74 can handle signals up to 5 MHz. Nevertheless, such harmful transmission components occur even in AD539 devices. Therefore, the fact is exploited that this element is a double harmonic multiplier that performs two multiplications: the desired multiplication and the multiplication of the envelope and the zero level signal. The multiplication of the envelope and the zero level signal is also affected by the transmitted component and therefore the desired product signal can be used to compensate by subtraction in circuit 80, for example a differential amplifier. This is illustrated in the waveforms of Figures 2J and 2L.

FIG. 2J represents the product signal at the output cuff 6.

It can be seen from this product signal that there is an undesired transmitted component 82. The same applies to the product signal of the output cuff 8.

Second, refer to the diagram. However, after the subtraction process, the resulting output is substantially unaffected by the transmitted component. 2nd L
See diagram. The waveform of Figure 2L can be used as an echo simulating calibration pulse and the timing for various parameters of the waveform of Figure 2L, such as pulse duration, rise time, fall time, and gating pulse, can be easily changed. will be understood. Furthermore, the phase relationship between the envelope and the carrier can vary.

[Brief explanation of drawings]

1A and 1B are both block circuit diagrams of one embodiment of the present invention, and FIGS. 2A to 2M illustrate the nature of signals generated in the circuits shown in FIGS. 1A and 1B. figure. 10...Oscillator, 12...Counter, 14...Shift register, 18...
... Phase selection circuit, 20 ... Buffer amplifier, 22 ... Analog switch circuit, 24 ...
...Buffer/low-pass filter section, 26...
Driver chain, 32...Single/multiple echo selection circuit, 34...
...Empelov' control N circuit, 36...
- Envelope duration selection circuit, 38...Pulse rising time selection circuit, 40...Pulse falling and falling timing selection circuit, 44...Buffer section, 46... ... Comparison section, 48 ... Amplitude level setting circuit, 66 ... Double multiplier,
80...Subtractor.

Claims (4)

[Claims] (1) Means for generating a high-frequency pulse train, means for generating an envelope having a rising end, a falling end, and a flat part between these ends, and the rise timing and fall of the end of the envelope. means for selectively varying the timing of the envelope, means for varying the duration of the envelope, said envelope being multiplied on the one hand by said high-frequency pulse train and on the other hand by a signal of substantially zero amplitude; A signal combiner comprising means for providing two outputs having superimposed transmitted components, and means for combining said output signals to generate a calibration signal substantially independent of said transmitted components. (2) Claim (1) further comprising means for shifting the phase of the pulse train with respect to the envelope.
). (3) The signal synthesizer according to claim 1 or 2, further comprising means for changing the amplitude of the calibration signal. (4) The signal according to claim (1), (2) or (3), wherein the coupling means is a differential amplifier that subtracts one multiplication output from the other multiplication output. Synthesizer.