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JPS61114998U - - Google Patents

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Publication number
JPS61114998U
JPS61114998U JP19717384U JP19717384U JPS61114998U JP S61114998 U JPS61114998 U JP S61114998U JP 19717384 U JP19717384 U JP 19717384U JP 19717384 U JP19717384 U JP 19717384U JP S61114998 U JPS61114998 U JP S61114998U
Authority
JP
Japan
Prior art keywords
pulse
phase
pulse motor
generating
basic clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP19717384U
Other languages
Japanese (ja)
Other versions
JPH0317596Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1984197173U priority Critical patent/JPH0317596Y2/ja
Publication of JPS61114998U publication Critical patent/JPS61114998U/ja
Application granted granted Critical
Publication of JPH0317596Y2 publication Critical patent/JPH0317596Y2/ja
Expired legal-status Critical Current

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  • Control Of Stepping Motors (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の実施例回路のブロツク線図、
第2図乃至第6図は第1図の本考案実施例回路の
動作説明図、第7図は本考案の他の実施例回路を
示すブロツク線図、第8図は第7図の本考案実施
例回路の動作説明図、第9図は本考案の他の実施
例回路のブロツク線図、第10図は従来回路のブ
ロツク線図、第11図は第10図に示す回路の動
作説明図である。 3……演算部、4……プログラマブル分周器、
5……相パルス発生器、7……ゲート回路、8…
…ドライバー回路、9……パルスモータ、10…
…リトリガブル無安定マルチバイブレータ、12
……リトリガブルワンシヨツトマルチバイブレー
タ、13……トリガー端子が2以上あるリトリガ
ブル・ワンシヨツトマルチバイブレータ、14…
…無安定マルチバイブレータ、15……ワンシヨ
ツトマルチバイブレータ。
FIG. 1 is a block diagram of an embodiment circuit of the present invention.
2 to 6 are explanatory diagrams of the operation of the circuit according to the embodiment of the present invention shown in FIG. 1, FIG. 7 is a block diagram showing another embodiment of the circuit according to the present invention, and FIG. 9 is a block diagram of another embodiment of the present invention, FIG. 10 is a block diagram of a conventional circuit, and FIG. 11 is an explanatory diagram of the operation of the circuit shown in FIG. 10. It is. 3... Arithmetic unit, 4... Programmable frequency divider,
5... Phase pulse generator, 7... Gate circuit, 8...
...Driver circuit, 9...Pulse motor, 10...
...Retriggerable astable multivibrator, 12
...Retriggerable one-shot multivibrator, 13...Retriggerable one-shot multivibrator with two or more trigger terminals, 14...
...Unstable multivibrator, 15...One shot multivibrator.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 制御すべきパルスモータの回転速度に応じた所
定の周期の基本クロツクパルスを発生する手段と
、前記基本クロツクパルスに基づき一定位相ずつ
ずれた複数のパルスを発生する相パルス発生手段
と、無安定マルチバイブレータと、この無安定マ
ルチバイブレータの出力によつてトリガーされる
ワンシヨツトマルチバイブレータと、前記相パル
ス発生手段からの各相バルスと前記ワンシヨツト
マルチバイブレータの出力パルスとの論理積をと
る複数のゲート回路と、これらゲート回路の出力
に基づき前記パルスモータの巻線に励磁電流を供
給する手段とを具備し、前記基本クロツクパルス
の周波数が低い低速域において、一定のオンオフ
デユーテイ比で前記パルスモータを駆動し、前記
クロツクパルスの周波数が高くなるにつれ、前記
オンオフデユーテユ比を増加し、高速域において
前記励磁電流に制限を付けずに前記パルスモータ
を駆動するようにしたことを特徴とするパルスモ
ータ駆動回路。
means for generating a basic clock pulse of a predetermined period according to the rotational speed of a pulse motor to be controlled; a phase pulse generating means for generating a plurality of pulses shifted by a constant phase based on the basic clock pulse; and an astable multivibrator. , a one-shot multivibrator triggered by the output of the astable multivibrator, and a plurality of gate circuits that take an AND of each phase pulse from the phase pulse generating means and the output pulse of the one-shot multivibrator. , means for supplying exciting current to the windings of the pulse motor based on the outputs of these gate circuits, and drives the pulse motor at a constant on-off duty ratio in a low speed range where the frequency of the basic clock pulse is low. The pulse motor drive is characterized in that as the frequency of the clock pulse increases, the on/off duty ratio is increased, and the pulse motor is driven without limiting the excitation current in a high speed range. circuit.
JP1984197173U 1984-12-25 1984-12-25 Expired JPH0317596Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1984197173U JPH0317596Y2 (en) 1984-12-25 1984-12-25

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1984197173U JPH0317596Y2 (en) 1984-12-25 1984-12-25

Publications (2)

Publication Number Publication Date
JPS61114998U true JPS61114998U (en) 1986-07-21
JPH0317596Y2 JPH0317596Y2 (en) 1991-04-12

Family

ID=30755276

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1984197173U Expired JPH0317596Y2 (en) 1984-12-25 1984-12-25

Country Status (1)

Country Link
JP (1) JPH0317596Y2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006132115A1 (en) * 2005-06-08 2006-12-14 Rohm Co., Ltd. Image pickup apparatus

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5691697A (en) * 1979-12-26 1981-07-24 Yokogawa Hokushin Electric Corp Controlling circuit of stepping motor
JPS59159700A (en) * 1983-03-03 1984-09-10 Toshiba Corp Drive control circuit for step motor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5691697A (en) * 1979-12-26 1981-07-24 Yokogawa Hokushin Electric Corp Controlling circuit of stepping motor
JPS59159700A (en) * 1983-03-03 1984-09-10 Toshiba Corp Drive control circuit for step motor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006132115A1 (en) * 2005-06-08 2006-12-14 Rohm Co., Ltd. Image pickup apparatus

Also Published As

Publication number Publication date
JPH0317596Y2 (en) 1991-04-12

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