JPS61111569A - Resin-sealed semiconductor device - Google Patents
Resin-sealed semiconductor deviceInfo
- Publication number
- JPS61111569A JPS61111569A JP59233751A JP23375184A JPS61111569A JP S61111569 A JPS61111569 A JP S61111569A JP 59233751 A JP59233751 A JP 59233751A JP 23375184 A JP23375184 A JP 23375184A JP S61111569 A JPS61111569 A JP S61111569A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- semiconductor device
- sealing
- less
- sealing resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
- H01L23/556—Protection against radiation, e.g. light or electromagnetic waves against alpha rays
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Physics & Mathematics (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は樹脂封止半導体装置、！Ｆｆには２５６に−１
Ｍビットダイナミックランダムアクセスメモリーのよう
な超ＬＳＩのソフトエラー８′防止し。[Detailed Description of the Invention] (Industrial Application Field) The present invention provides a resin-sealed semiconductor device! -1 to 256 for Ff
Prevents soft errors 8' in VLSIs such as M-bit dynamic random access memory.
かつ樹脂応力による半導体素子の特性変動を防止するよ
うにした樹脂封止半導体装置に関するものである。The present invention also relates to a resin-sealed semiconductor device that prevents variations in characteristics of semiconductor elements due to resin stress.
（従来の技術〕
近年−ランダムアクセスメモリーとされる半導体装置は
封止樹脂中に含まれる放射性物質から放出されるα粒子
によってランダムアクセスメモリーの蓄積した情報が反
転して誤動作が生ずるという問題が生じ、高集積化の実
現と共に大きな問題とされている。(Prior Art) In recent years, semiconductor devices that are used as random access memories have encountered the problem that alpha particles emitted from radioactive substances contained in the sealing resin invert the information stored in the random access memory, causing malfunctions. , has become a big problem with the realization of high integration.
そのため、この種の半導体装置については第３図に示し
たように半導体素子ＩＩの表面なポリイミド樹脂やシリ
コーン樹脂などのような有機口Ｂ旨１２で被覆するか、
この種の樹脂フィルムで被覆し、ボンディングワイヤー
４．リードフレーム１３と共に封止樹脂１５で封止する
という方法が採られており、封止樹脂１５からのα線を
防止するためには有機樹脂１２の皮膜厚を３０μｍ以上
とすることが必要とされるのであるが、３０μｍ以上の
膜厚で均一に素子表面を被覆することは非常に難しく、
３０μｒＩＬ以上の膜厚でシリコーン樹脂やエポキシ樹
脂で覆った場合にはこれらの樹脂は膨イ
張係数が大きいのでボンディグワイヤー４が切断されや
すいという不利があＩ】−この素子表面にこれらの樹脂
フィルムな粘着剤などで被着させたときには封止樹脂に
よる封止の際にはがれたり、変形してしまうという欠点
があった。Therefore, for this type of semiconductor device, as shown in FIG.
Covered with this kind of resin film and bonding wire 4. A method is adopted in which the lead frame 13 is sealed with a sealing resin 15, and in order to prevent alpha rays from the sealing resin 15, the film thickness of the organic resin 12 must be 30 μm or more. However, it is extremely difficult to uniformly coat the device surface with a film thickness of 30 μm or more.
When covering with silicone resin or epoxy resin with a film thickness of 30μrIL or more, there is a disadvantage that the bonding wire 4 is easily cut because these resins have a large expansion coefficient. When it is adhered with a film adhesive or the like, it has the disadvantage that it peels off or becomes deformed when it is sealed with a sealing resin.
また、このα線放射対策としては、上記した被覆用の樹
脂１２を全く使用せず、第４図に示し定ようにα線発生
源である封止樹脂組成物中の無機質充填剤なウランやト
リウムの含有量の極めて少ない合成ンリカなどとした封
止樹脂１５で半導体素子１ｍボンダイングワイヤ＋４．
リードフレーム１３を封止するという方法も知られてお
り、これには樹脂１２による被覆がないのでボンディン
グワイヤ１４の切断という不利は解決されるけれども、
素子の大型化に伴なう温度サイクルテスト時に素子表面
に加わる内部応力の増大によってパシベーションクラッ
クが発生したり、アルミニウム配線の移動による特性の
劣化など従来は考えられなかった不利が発生するという
欠点がある。In addition, as a countermeasure against alpha ray radiation, the above-mentioned coating resin 12 is not used at all, and as shown in FIG. Semiconductor element 1m bonding wire +4.
A method of sealing the lead frame 13 is also known, although this eliminates the disadvantage of cutting the bonding wire 14 since there is no coating with the resin 12.
As the size of the device increases, the internal stress applied to the device surface increases during temperature cycle tests, which causes passivation cracks, and the movement of aluminum wiring causes deterioration of characteristics, which are disadvantages that were previously unthinkable. be.
（発明の構成）
本発明はこのような不利を解決した樹脂封止半導体装置
に関するものであり、これは半導体素子表面な膜厚３０
μｍ以下の有機樹脂で被覆したのち、ウランおよびトリ
ウムの含有量が１ｐｐｂＪ２を下である封止用樹脂で封
止してなることを特徴とするものである。(Structure of the Invention) The present invention relates to a resin-sealed semiconductor device that solves the above-mentioned disadvantages.
It is characterized in that it is coated with an organic resin of micrometer or less, and then sealed with a sealing resin with a uranium and thorium content of 1 ppbJ2.
すなわち１本発明者らは従来法による不利、欠点を除去
することのできる樹脂封止半導体装置について種々検討
した結果−半導体素子を有機樹脂で被覆し、ついでこれ
を封止樹脂で封止する場合に、この封止樹脂をウランお
よびトリウムの含有量が１ｐｐｂ以下のものとすれば半
導体素子を被覆する有機樹脂層は特Ｔｌｃ３０μｍ以上
とする必要はなく−また封止樹脂の封止に伴なう半導体
素子に与えられる内部応力に対してはこの有機樹脂層が
有効に作動することを見出し、この有機樹脂層と封止樹
脂との組合せについての研究を進めて本発明を完成させ
た。Namely, as a result of various studies by the present inventors on resin-sealed semiconductor devices that can eliminate the disadvantages and drawbacks of conventional methods - a case in which a semiconductor element is coated with an organic resin and then sealed with a sealing resin. In addition, if the uranium and thorium content of this sealing resin is 1 ppb or less, the organic resin layer covering the semiconductor element does not need to have a Tlc of 30 μm or more. They discovered that this organic resin layer effectively acts against the internal stress applied to a semiconductor element, and completed research on the combination of this organic resin layer and a sealing resin, thereby completing the present invention.
本発明の半導体装置に使用される有機樹脂としては、シ
リコーン樹脂、ポリイミド樹脂−シリコーン・ポリイミ
ド共重合体、シリコーン・エポキシ共重合体、ポリブタ
ジェン、エポキシ樹脂などが例示されるが、この有機樹
脂層（工α線防御のためではなく封圧樹脂からの応力防
止を主目同とするものであるので、適度の弾性をもつも
のとすることがよく、この観点からはポリイミド樹脂−
シリコーン樹脂、シリコーンポリイミド共重合体を選択
することがよい。また、この有機樹脂はエアロジル、合
成シリカ粉などを充填剤として含有するものであっても
よいが、この充填剤は本発明の目η上からウラン、トリ
ウムの含有量が１ｐｐｂａ下−好ましくはｏ、５ｐｐｂ
以下のものとすることがよい。Examples of the organic resin used in the semiconductor device of the present invention include silicone resin, polyimide resin-silicone polyimide copolymer, silicone epoxy copolymer, polybutadiene, and epoxy resin. Since the main purpose is to prevent stress from the sealing resin, not to protect against polyimide resin, it is best to use a material with appropriate elasticity.From this point of view, polyimide resin
Silicone resins and silicone polyimide copolymers are preferably selected. Further, this organic resin may contain Aerosil, synthetic silica powder, etc. as a filler, but this filler has a uranium and thorium content of 1 ppba or less, preferably o ,5ppb
The following should be used.
この有機樹脂による半導体素子の被覆は封止樹脂からの
応力防止のためのものであるということから従来法のよ
うに３０μｒｒＬ以よとする必要はな（−３０μｍ以下
例えば３〜２０μｍの範囲とすることが好ましく、この
有機樹脂による被覆工程は例えばポリイミドを全面塗布
した後ヒドラジンなどのエツチング液でエツチングする
フォトリソグラフィー法などのように従来法にくらべて
簡易化することができろ。Since the purpose of coating the semiconductor element with this organic resin is to prevent stress from the sealing resin, it is not necessary to cover the semiconductor element with a thickness of 30 μrr or less as in the conventional method (for example, it should be less than -30 μm in the range of 3 to 20 μm). Preferably, the process of coating with this organic resin can be simplified compared to conventional methods such as photolithography, in which polyimide is applied over the entire surface and then etched with an etching solution such as hydrazine.
本発明の半導体装置は上記のように厚さ３０μｒＩＬ以
下の有機樹脂で被覆したのち、ついでこれ乞封止用樹脂
で封止するのであるが、この封止用樹脂は公知のもので
よく、これにはエポキシ系樹脂、シリコーン系樹脂、エ
ボキ７変性シリコーン系樹脂が例示される。しかし、こ
の封止用樹脂はつ２ン、トリウムなどの放射性物質含有
量が１ｐｐｂ以下、好ましくは０．５ｐｐｂ以下α）も
のとする必要があるので、この組成物を構成する無機質
充填剤としてはエアロジル、合成石英などのようなもの
とする必要があり、この封止用樹脂としては低応力樹脂
がより好ましいものとされるが。The semiconductor device of the present invention is coated with an organic resin having a thickness of 30 μrIL or less as described above, and then sealed with a sealing resin, and this sealing resin may be a known one. Examples include epoxy resins, silicone resins, and epoxy-7 modified silicone resins. However, since this sealing resin needs to have a content of radioactive substances such as chlorine and thorium of 1 ppb or less, preferably 0.5 ppb or less, the inorganic filler constituting this composition must be It is necessary to use a material such as Aerosil or synthetic quartz, and a low stress resin is considered to be more preferable as the sealing resin.
この封止は常法によるトランスファー成形などで行えば
よい。This sealing may be performed by conventional transfer molding or the like.
つぎに本発明の半導体装置を添付の図面にもとづいて説
明する。第１図、第２図はいずれも本発明の半導体装置
の縦断面要因を示したものであり。Next, the semiconductor device of the present invention will be explained based on the attached drawings. Both FIG. 1 and FIG. 2 show factors in the longitudinal section of the semiconductor device of the present invention.
第１図における半導体装置をエポンディングバット部以
外を有機樹脂２で被覆した半導体素子１を銀ペーストあ
るいは共晶でリードフレーム３の上にとイ
リつけたのち、ボンデングワイヤ４で半導体素子１とリ
ードフレーム３とを接続し、ついでウラン。In the semiconductor device shown in FIG. 1, a semiconductor element 1 whose parts other than the eponding butt part are covered with an organic resin 2 is irrigated on a lead frame 3 with silver paste or eutectic, and then bonded with a bonding wire 4. Connect lead frame 3, then uranium.
トリウムの含有量が１ｐｐｂ以下とされた封止用樹脂５
で封止したものであり一第２図の半導体装置は半導体素
子１をリードフレーム３に取りつけたのち、ボンディン
グワイヤ４で半導体素子ｌとリードフレーム３とを接続
し一ついで有機樹脂２で半導体素子ｌの表面を被覆し、
つぎにこれらをウラン−トリウムの含有量が１ ｐｐｂ
以下とされた封止用樹脂５で封止したものであるが、こ
れらはいずれも封止用樹脂がウラン、トリウムなどの放
射線物質含有量が１１）ｐｂ以下とされているのでα線
放射によるソフトエラーが発生するおそれはなく、また
これは有機樹脂で被覆されているので封止樹脂による内
部応力によって素子特性の劣化することもな（、シたが
ってパシベーションクラック、アルミニウム配線の移動
などの事故発生もないという有利性が与えられる。Sealing resin 5 with thorium content of 1 ppb or less
In the semiconductor device shown in FIG. 2, a semiconductor element 1 is attached to a lead frame 3, and then the semiconductor element 1 and the lead frame 3 are connected with bonding wires 4, and then the semiconductor element is sealed with an organic resin 2. coat the surface of l,
Next, the content of uranium-thorium is 1 ppb.
These are sealed with the following sealing resin 5, but since the content of radioactive substances such as uranium and thorium in the sealing resin is 11) pb or less, alpha radiation is There is no risk of soft errors occurring, and since it is coated with organic resin, there is no possibility of deterioration of element characteristics due to internal stress caused by the sealing resin (therefore, accidents such as passivation cracks and aluminum wiring movement) This gives the advantage of no occurrence.
つぎに本発明の実施例をあげる。Next, examples of the present invention will be given.
実施例
２５６Ｗラムの半導体シリコンチップ表面に回転被覆法
でポリイｉ）″樹脂な膜厚５μ扉で被覆したσＪち、こ
れを１６ピンのＩＣフレームに搭載し一金線を用いてリ
ード部とチップを接続した。Example 2 The surface of a semiconductor silicon chip of a 56W RAM was coated with a polyurethane resin film (5 μm thick) using a rotational coating method, and this was mounted on a 16-pin IC frame, and the lead portion and the chip were coated using a gold wire. connected.
ついで−これをウランおよびトリウムの含有量がそれぞ
れｏ、１ｐｐｂ以下である合成石英粉１７０重ｔ％とシ
リコーン系の可撓性付与剤を含有するフェノール硬化型
のエポキシ樹脂を用いて。This was then treated using a phenol-curable epoxy resin containing 170% by weight of synthetic quartz powder with a uranium and thorium content of 0 and 1 ppb or less, and a silicone-based flexibility imparting agent.
１７５℃−７ＯＫｆ／ｉの条件のトランスファー成′形
で封止したＱ】ち、さらにエポキシ樹脂の反応を確実に
するために１８０℃で４時間ボストキュア１行なった。It was sealed by transfer molding under the conditions of 175 DEG C. and 7 OKf/i.Furthermore, in order to ensure the reaction of the epoxy resin, a post cure was performed at 180 DEG C. for 4 hours.
つぎにこのようにして得られにプラスチック封止２５６
蔀ラムの特性を評価するために、これを−６０℃７３０
分〜１５０℃／３０分のヒートサイクルを５００サイク
ル行なったのちのリーク電流をチェックしたところ、こ
のヒートサイクル後においても特性不良は全く認められ
なかった。The plastic seal 256 thus obtained is then
In order to evaluate the properties of yam rum, it was heated to -60℃730
When the leakage current was checked after 500 heat cycles of 150 DEG C./30 minutes, no characteristic defects were observed even after the heat cycles.
しかし、比較のためによ起におけるポリイミド樹脂の被
覆を行なわずにこのドラム！直接上記したエポキシ樹脂
で封止して得たものについて上記と同様のヒートサイク
ルテストを行なったところ。However, for comparison, this drum was produced without the polyimide resin coating! A heat cycle test similar to the above was conducted on a sample obtained by directly sealing with the epoxy resin described above.
これには特性変動（リーク電流の増加）が認められたの
で、この封止樹脂を除去してチップ表面をしろべたとこ
ろ、このものはチップの周辺部にパッシベーション膜の
クラックが観察されたほか。A characteristic change (increase in leakage current) was observed, so when the sealing resin was removed and the chip surface was examined, cracks in the passivation film were observed around the chip.
アルミニウム配線の変位も観察された。Displacement of the aluminum wiring was also observed.
なお、これらのドラムのα線によるソフトエラーに関し
てはいずれのものも１，０ＯＯＦＩＴ以下であった。Note that the soft errors caused by alpha rays in these drums were all below 1,0 OOFIT.
第１図、第２図は本発明の樹脂封止半導体装置の縦断面
要因−第３図、第４図を工従来公知の樹脂封止半導体装
置の縦断面要因を示しにものである。
１．１１・・・半導体素子−
２、Ｉ２・・・亘機樹脂層。
３．１３・・・リードフレーム−
４，１４・・・ポンディングワイヤ、
５．１５・・・封止樹脂層。
第１図
第２図FIGS. 1 and 2 show factors in a longitudinal section of the resin-sealed semiconductor device of the present invention, while FIGS. 3 and 4 show factors in a longitudinal section of a conventionally known resin-sealed semiconductor device. 1.11...Semiconductor element-2, I2...Wataru resin layer. 3.13...Lead frame-4,14...Ponding wire, 5.15...Sealing resin layer. Figure 1 Figure 2
Claims (1)
覆したのち、ウランおよびトリウムの含有量が１ｐｐｂ
以下の封止用樹脂で封止したことを特徴とする樹脂封止
半導体装置。 ２、有機樹脂がシリコーン樹脂、ポリイミド樹脂、シリ
コーン・ポリイミド共重合体、ブタジエン、エポキシ樹
脂から選択されたものである特許請求の範囲第１項記載
の樹脂封止半導体装置。 ３、封止用樹脂がエポキシ系樹脂またはシリコーン系樹
脂である特許請求の範囲第１項記載の樹脂封止半導体装
置。[Claims] 1. After the surface of the semiconductor element is coated with an organic resin with a film thickness of 30 μm or less, the content of uranium and thorium is 1 ppb.
A resin-sealed semiconductor device characterized by being sealed with the following sealing resin. 2. The resin-sealed semiconductor device according to claim 1, wherein the organic resin is selected from silicone resin, polyimide resin, silicone-polyimide copolymer, butadiene, and epoxy resin. 3. The resin-sealed semiconductor device according to claim 1, wherein the sealing resin is an epoxy resin or a silicone resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59233751A JPS61111569A (en) | 1984-11-06 | 1984-11-06 | Resin-sealed semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59233751A JPS61111569A (en) | 1984-11-06 | 1984-11-06 | Resin-sealed semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61111569A true JPS61111569A (en) | 1986-05-29 |
Family
ID=16960003
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59233751A Pending JPS61111569A (en) | 1984-11-06 | 1984-11-06 | Resin-sealed semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61111569A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01206656A (en) * | 1988-02-15 | 1989-08-18 | Nitto Denko Corp | semiconductor equipment |
| JPH04335556A (en) * | 1991-05-10 | 1992-11-24 | Murata Mfg Co Ltd | Hybrid integrated circuit |
| JP2002337170A (en) * | 2001-05-21 | 2002-11-27 | Honda Motor Co Ltd | Two-liquid mixing and discharging method |
| JP2010118429A (en) * | 2008-11-12 | 2010-05-27 | Denso Corp | Electronic apparatus and manufacturing method for the same |
| JP2013197531A (en) * | 2012-03-22 | 2013-09-30 | Sharp Corp | Semiconductor device and manufacturing method of the same |
-
1984
- 1984-11-06 JP JP59233751A patent/JPS61111569A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01206656A (en) * | 1988-02-15 | 1989-08-18 | Nitto Denko Corp | semiconductor equipment |
| JPH04335556A (en) * | 1991-05-10 | 1992-11-24 | Murata Mfg Co Ltd | Hybrid integrated circuit |
| JP2002337170A (en) * | 2001-05-21 | 2002-11-27 | Honda Motor Co Ltd | Two-liquid mixing and discharging method |
| JP2010118429A (en) * | 2008-11-12 | 2010-05-27 | Denso Corp | Electronic apparatus and manufacturing method for the same |
| JP2013197531A (en) * | 2012-03-22 | 2013-09-30 | Sharp Corp | Semiconductor device and manufacturing method of the same |
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