JPS61107177A - Apparatus for displaying trouble location of radar equipment - Google Patents

Abstract

PURPOSE:To make it possible to easily perform the inspection of the presence of absence of trouble and the confirmation of a trouble place on the surface of a panel at a necessary time, by forming a code signal corresponding to a trouble diagnosis signal and displaying the trouble place by a figure. CONSTITUTION:In a memory device 4, a series of the arrangements of trouble diagnosis signals form trouble code signals and the position of each bit corresponds to the discrimination number of a preset functional block. The output of this memory device 4 is always supplied to a trouble judge circuit and the trouble code signal is inputted thereto. Logical operation is performed on the basis of this trouble code signal and the presence or absence of the trouble in each bit is judged. Corresponding to this judge result, the number of the functional block having gotten out of order is displayed on a figure display part 1 by a figure.

Description

[Detailed Description of the Invention] [Field of Application of Tojo] The present invention has a fault diagnosis circuit for diagnosing a fault for each functional block inside the RT bag, and an image display unit for displaying an image on a display unit. The present invention relates to a failure location display device that is applied to a radar device having a display unit and a numeric display unit that displays numerical information such as a distance marker, and that displays a failure location inside the radar device using a failure diagnosis signal from the failure diagnosis circuit.

[Background Art] In recent years, radar devices have become more complex and multifunctional as their performance has improved. The circuit parts related to these functions are divided into blocks for each function and mounted on the printed circuit board.

In the event that such high-performance radar equipment fails.

In this case, if the iJ! .

In order to perform quick and accurate repairs, service personnel must know the location of the failure in advance and prepare necessary parts, tools, etc. in a well-organized manner. In particular, in the case of marine radars, the berth time is often limited, so prompt repairs are required, and such consideration is required.

In order for service personnel to know the location of a failure in advance, a radar operator such as a ship's crew member must notify the service personnel of the location of the failure. This is almost impossible as circuits are becoming more multi-functional and complex.

Therefore, conventionally, this type of radar device is provided with a fault diagnosis device corresponding to each functional block mounted on a printed circuit board, and the diagnosis results of the fault diagnosis device are analyzed.

The structure is such that an attached light emitting element (for example, a light emitting diode) blinks to indicate whether or not there is a failure in the block.

That is, this fault diagnosis device checks whether the output signal of the function block in question maintains a normal magnitude by comparing it with a preset reference value, and if it is normal, it turns "on".
, outputs an "off" diagnostic signal if there is an abnormality. This signal is supplied to the light emitting element and acts to drive the light emitting element, such as turning on the light for normal operation and turning off the light for failure.

Therefore, by checking the lighting state of the light emitting elements, it is possible to discover the failure location in each functional block.

However, the failure display in this conventional failure diagnosis apparatus has the following problems.

[Problem that the invention seeks to solve]

What is the fault display in this conventional fault diagnosis device?

This is done on a printed circuit board that has each function installed, so when inspecting it or checking for failure locations,
Radar? It is necessary to remove the panel for the circuit section, and if necessary, pull out the rack that holds the printed circuit board and check the lighting status of the light emitting elements. Therefore,
The disadvantage is that it takes a lot of time to check the location of the failure.

Furthermore, even if you find a printed circuit board with a light-emitting element turned off, it is difficult to accurately notify service personnel of the location of the failure among the large number of printed circuit boards by telephone, etc.
This is not always easy, especially when a plurality of functional blocks are mounted on the same board, and since a plurality of light emitting elements are arranged, it becomes even more difficult to identify the failure location.

As a result, service personnel are unable to accurately identify the location of the failure in front of the vehicle, and are therefore unable to prepare the necessary repair parts, resulting in time-consuming repairs or excessive preparation, resulting in waste. The disadvantage is that it takes a lot of effort.

The present invention provides numerical display of failure locations.

It is an object of the present invention to provide a failure point display device for a radar device that allows a radar operator to easily check the presence or absence of a failure and recognize the failure location on a panel surface whenever necessary.

[Means for Solving the Problems] Means for solving the above problems will be explained with reference to FIG. 1.

Main application cylinder 1. The invention of flR2 was developed as a radar device, which has a variable distance marker display,
It is constructed with attention paid to the fact that, in addition to the video display section, a numeric display section 1 for numerically displaying the azimuth angle and the like of the electronic cursor line display is provided.

That is, the cylinder 1 of the present invention and the second invention are inside the device.

A fault location display device is provided with a fault diagnosis circuit (not shown) for diagnosing a fault in each functional block, and displays a fault location inside a radar device using a fault diagnosis signal from the fault diagnosis circuit, and has the following configuration. It is characterized by having requirements.

A first aspect of the present invention includes, firstly, a storage device 4 that receives a diagnostic signal from the fault diagnostic circuit to form a fault code signal that indicates a fault location of the radar device, and that temporarily stores the fault code signal. have.

Second, it has a clear signal generator 5 that generates a clear signal that resets the contents of the memory 4 at predetermined intervals.

Third, the numeric information sent from the numeric information generating means 3 and the fault code signal sent from the storage device 4 are switched in response to a switching command signal from the outside, and the numeric information sent out from the numeric information display section 1 is switched. It is equipped with a switch 2 for input.

On the other hand, the second invention provides, in addition to the first to third constituent features,
As a fourth component, a failure determination circuit 7 is provided which extracts the failure code signal from the storage device 4, determines the presence or absence of a failure, and displays the result.

The numeric display unit l installed in the radar device to which the present invention is applied is composed of, for example, one light emitting diode, a liquid crystal, etc.
It has a segment number display element or a dot matrix number display element, a drive circuit that drives the number display element, and a decoder that decodes code information such as a failure code signal to be described later and converts it into a number display signal. It is composed of

The storage device 4 is configured, for example, by a series of a plurality of flexible flop circuits, or by a parallel-in/parallel-out register, and has a storage area of a plurality of bits corresponding to the number of functional blocks. Ru. The storage area of the memory 4 is connected to the output of the fault diagnosis circuit of each functional block corresponding to each bit. Then, in response to the high/low of the diagnostic signal from the corresponding fault diagnostic circuit,
l'' or 0'' is set in each bit of the storage area.

This memory device 4 makes the spatial arrangement of the series of information set in the storage area as described above correspond to the number of each functional block, and uses it as a failure code signal.

In addition, when the above-mentioned failure diagnosis circuit is constituted by a microcomputer and the diagnosis signals from each functional block are serially transferred, the memory 4 is constituted by a serial-in/parallel-out type register.

”1 The memory device 4 has a reset terminal R.

The output of the clear signal generator 5 is input to this terminal R. The clear signal generator 5 includes, for example, a clock pulse generator and a frequency divider that divides the frequency of the clock pulse, and outputs a clear signal E at a constant period T.

This signal causes the memory 4 to be reset.

The switch 2 is, for example, a logic switch element combining an AND gate circuit and an OR gate circuit, or a 0MO5
) A plurality of analog switch elements using transistors are provided corresponding to the numerical information of the numerical information generating means 3 and the bits of the storage area of the memory device 4, and one of the inputs of each switch element is provided with the above-mentioned fault code. Input the signal, and input the above numerical information on the other side. The number of switch elements of this switch 2 is matched to the number of bits of information, whichever is the numerical information generating means 3 or the memory 4.

Further, this switch 2 is provided with a switching control terminal Cs that is commonly connected to each of the above-mentioned switch elements, and a switching command signal is inputted to this terminal Cs from the outside. This switching command signal is formed by turning the switch 6 on and off, for example.

The failure determination circuit 7 is composed of a logic operation section consisting of, for example, a Nant gate circuit, and a display element consisting of one light emitting diode or the like. This failure determination circuit 7 inputs each output of the memory 4 and performs logical calculations such as logical product negation,
Determine and display the presence or absence of a failure.

Note that the determination result of the failure determination circuit 7 can also be inputted to the switching device 4 as a switching command signal.

[Operation J The operation of the solution means of the present invention configured as described above will be explained with reference to the above-mentioned FIGS. 1 and 2.

In applying the present invention, each functional block is assigned an identification number, and the input of the fault diagnosis signal to each bit of the storage area of the memory device 4 is arranged in the order of the identification number.

First, it is assumed that the switch 2 is in a normal display mode, that is, a state in which numerical information is displayed. In this state, the switch 6 that forms the switching command signal is off.

The numeric display section 1 is connected to the numeric information generating means 3 via the switch 2.
is connected to. The numerical information generating means 3 sends out a numerical code signal corresponding to the distance of the variable distance marker by counting, for example, reference clock pulses, and displays the variable distance on the numerical display section 1.

Next, when the radar operator turns on SWEE and CIRRO, a switching command signal is input to the switching device 2, and the mode becomes the failure diagnosis location display mode. That is, the a-shaped representation section 1 is connected to the memory device 4. Number display 5 is,
A fault code signal is input from the memory 4, and the number of the functional block corresponding to the code is displayed as the fault *m location.

Now, for example, the trigger a1 and the videos bl and cl, which are the output signals of each stage of the video system, are stored in the memory 4.

It is assumed that failure signals from each functional block of unblanking d1 are input. Note that this memory device 4 is periodically cleared by a clear signal E from a clear signal generator 5 and brought to an initial state.

In one section T1 in FIG. 2, all bits in the storage area are cleared by the clear signal E and are at low level. Here, when the trigger a1 is input to the storage device 4, 'l'' is set in the corresponding bit of the storage area, and its output becomes the trigger a2.Similarly, the video bl
, cl and unblanking d1 are input to the memory 4, these corresponding bits are set to 1'', and their outputs are video b2.c2 and unblanking d1.
It becomes 2.

In this case, a series of set states of the storage area of the storage device 4 are as follows:
"l 111", indicating that all functional blocks are normal.

The above-mentioned series of set conditions are sent to the numeric display section 1 via the switch 2 as a failure code signal.

In this case, since none of the blocks is faulty, the decoder (not shown) of the number display section l decodes it as O, and displays 0.

Next, in section T2, the trigger al, the video bl
If a fault diagnosis signal is input for unblanking DI and no diagnosis signal is input for video CL, the bit corresponding to video C1 in the storage area of memory 4 is set to ``1n is not set, and ``0 is not set. ” status. Therefore.

The series of set states of the memory device 4 becomes "1101".

According to this fault code signal, the lower 2nd bit is “0”.
'', so by the decoder on number display section 1,
It is decoded as 2 and 2 is displayed.

That is, it is displayed that the failure location is the functional block with identification number 2.

Thus, in one aspect of the present invention, a series of arrangements of fault diagnosis signals stored in the memory 4 form a fault code signal, and one spatial position of the storage area, that is, the digit of each bit, is predetermined. Since it corresponds to the set identification number of the functional block, the number displayed on the number display section 4 becomes the number of the failed functional block. Therefore, using this number as a clue, service personnel can easily determine the location of the failure.

Next, the operation of the failure determination circuit 7 included in the constituent features of the second invention of the present application will be explained.

The output of the memory 4 is always connected to the failure determination circuit 7, and the above-mentioned failure code signal is input thereto. The failure code signal input to the failure determination circuit 7 is subjected to a logical operation, for example, logical AND NOT, and it is determined whether any bit has a failure.

If the fault code signal is l L 11” mentioned above,
The logical product negation becomes “ON”, and it is determined that there is no failure location.On the other hand, the failure code signal is “1101” mentioned above.
If so, the logical product negation is 01'', and it is determined that there is a failure.

These determination results are displayed by lighting the light emitting element or the like. That is, if there is a failure, one light emitting element lights up, and if there is no failure, one light emitting element remains off. However, the correspondence relationship between turning on and turning off the light emitting element depending on the presence or absence of a failure may be the opposite of the above relationship.

Since this failure determination circuit 7 operates independently of whether the switch 6 is turned on or off, a radar operator such as a ship's crew can always grasp the presence or absence of a failure without impairing the function of variable distance marker display, for example. can do. Therefore,
To recognize the location of a failure, it is sufficient to turn on the switch only when a failure occurs.

[Example] Embodiments of the present invention will be described with reference to the drawings.

Configuration of the First Embodiment> The first embodiment of the present invention shown in FIG. 5 and.

It is configured to include a changeover 2 and a switch 6.

The storage device 4 includes a plurality of printed circuit boards 9a.

Fault diagnosis circuits 8a, 8b...8n mounted in correspondence with the functional blocks are connected to 9b...9n, and fault diagnosis signals are input from the diagnostic circuits 8a...8n.

The numeric display section l includes a 7-segment numeric display element 13 made of one light emitting diode, liquid crystal, etc., and a drive circuit 12 for driving the numeric display element 13. & Deciphers code information such as failure code signals and converts them into numerical display signals! The kneader 11 is configured to include a kneader 11. This numeric display section 1 is connected to a numeric information generating means 3 and a memory 4 via a switch 2.

The numerical information generating means 3 includes, for example, a reference clock pulse generator 31 and a ring counter for counting the pulses, and sends out a numerical code signal corresponding to the distance of the variable distance marker, and displays the variable distance numerically. Displayed in section l.

The memory device 4 includes a plurality of flip-flow circuits 4a.

4b . The flip-flop circuits 4a...4n are each provided with a set terminal S, and failure diagnosis circuits 8a...8 are connected correspondingly to the set terminals S.
A diagnostic signal from n is input.

Then, in response to the high/low level of the signal, "1" or MO" is applied to the corresponding flip-flop circuit 4 in the storage area.
a...4n is activated.

This storage device 4 stores the spatial arrangement of a series of information set in the storage area as described above with the number # of each functional block.
1 to #n are used as failure code signals.

Further, each of the above flip-flop circuits 4a...4n is
It has a reset terminal R, and the output of the clear signal generator 5 is input to this terminal H.

This clear signal generator 5 is a clock pulse generator 51
and a frequency divider 52 that divides the frequency of the clock pulse, and outputs a clear signal E at a constant period T. This signal causes the memory 4 to be reset at regular intervals.

The switch 2 has a plurality of logic switch elements each consisting of a set of two AND gate circuits 21, 22 and an OR gate circuit 23, corresponding to the numerical information of the numerical information generating means 3 and the bits of the storage area of the memory 4. The fault code signal is input to the AND gate circuit 21 of each switch element, and the numerical information is input to the AND gate circuit 22.

Further, this switch 2 is provided with a switching control terminal Cs that is commonly connected to each of the above-mentioned switch elements, and a switch 6 that inputs a switching command signal from the outside is connected to this terminal Cs. This switch 6 is connected to each AND gate circuit 21, 22 for one minute. That is, the AND gate circuit 21 is connected to the AND gate circuit 22 via the inverter 24, and the AND gate circuit 22 is directly connected to the PA.
In the first embodiment configured as described above, each part operates as follows.

First, when the switch 6 is off, in the changeover 2,
A high-state gate open signal is input to the AND gate circuit 22, and a low-state signal is input to the AND gate circuit 21 via the input terminal 24. In this state, switch 2
1 is in the normal display mode, that is, a state in which numerical information is displayed.

The decoder 11 of the numeric display section 1 includes an AND gate circuit 22
and the numerical information generating means 3 via the OR gate circuit 23.
The counter 32 is connected to the counter 32 of FIG.

The numerical information generating means 3 counts the reference clock pulses of the clock pulse generating circuit 31 to generate a numerical code signal corresponding to the distance of the variable distance marker to the decoder 1.
Send to 1.

In the numeric display section 1, the code signal is decoded by a decoder 11, and the result is inputted to a numeric display element 13 via a drive circuit 12 to display a variable distance.

Next, when the radar operator turns on the switch 6, a switching command signal is input to the switch 2, a gate open signal is input to the AND gate circuit 21, and the mode is changed to the failure diagnosis point display mode. becomes. That is, the decoder 11 of the numeric display section l is connected to the memory 4 via an AND gate circuit 21 and an OR gate circuit 23.

In the flip-flop circuits 4a...4n of the memory 4, #
Fault diagnosis circuit 8a corresponding to the functional block of 1-an.
・: Failure diagnosis signal from 8n is input. This diagnostic signal is formed to be "1" in case of normal operation and "°O" in case of failure.

Note that each flip-flop circuit 4a of this memory device 4...
・4n is connected to the frequency divider 52 of the clear signal generator 5, and is periodically cleared and brought to the initial state by the clear signal E sent out at a period T obtained by dividing the clock pulse. Ru.

Now, assume that the failure diagnosis signal is input to each of the flip-flop circuits 4 & . . . 4n, and a series of set states become as follows.

“l...11111” In this case, the series of set states of the storage area of the storage device 4 are as follows:
Indicates that all functional blocks are normal.

When the above series of set states is input as a failure code signal to the AND gate circuit 21 of the switching rs2, the circuit 2
Since the gate open signal in the high state is input to the other input of 1, this fault code signal is directly sent to the numeric display section 1 via the OR gate circuit z3. Since all bits of the signal are "1", the decoder 11 outputs
I deciphered it.

O is displayed on the number display element 11.

Next, for example, if a failure occurs in the functional block #3, the failure diagnosis circuits 8&...8n will indicate that the circuit 8c is 0'' and the other circuits 8a, 8b, 8d...8n are 1'. outputs a fault diagnosis signal. Therefore.

In each of the flip 70° tube circuits 4a...4n of the memory 4, a failure diagnosis signal is set in series as follows.

"1...11011" The above-mentioned series of set states is sent to the numeric display section l via the switch 2 as a failure code signal, as described above. Since the third bit of the signal is 0'' and the other bits are "l", the decoder 11 decodes it as 3, and the number display element 11 displays 3.

In this way, the set state of the fault diagnostic signal is
It is sent to the numerical display part l as a fault code signal, and the first bit is rlJ, the second bit is r2'J, the third bit is r3J, and the nth bit is rnJ. The number corresponding to the bit position is displayed.

When there are ten or more functional blocks, the first or higher fault diagnosis circuits are connected to the first flip-flop circuit and the tenth flip-flop circuit. This results in 2
It becomes possible to support a number of functional blocks exceeding an order of magnitude.

Structure and Operation of Second Embodiment A second embodiment of the present invention shown in FIG. 4 includes a failure determination circuit 7 in the failure location display device of the first embodiment. Therefore, only the configurations that are different from the first embodiment will be described.

The failure determination circuit 7 includes a logic operation section consisting of a Nant gate circuit 71 and a display element consisting of one light emitting diode 72. The failure determination circuit 7 receives the outputs of the flip-flop circuits 4a, . . . , 4n of the storage device 4, performs logical operations such as logical product negation, determines the presence or absence of a failure, and displays 1.

In such a configuration, if the failure code signal set in the memory 4 is "l...11111", the output of the Nant gate circuit 71 becomes "0" and the first light emitting diode 72 does not light up.

On the other hand, if the fault code signal includes °°0", such as "61...11101", the output of the Nant gate circuit 71 becomes "1", and the light emitting diode 72 lights up.

This allows the operator of the radar device to know that a failure has occurred. Therefore.

The operator can know the location of the failure by turning on the switch at the appropriate time, taking into account the display state of the numerical information.

<Configuration and operation of Z3 embodiment> The fi3 embodiment of the present invention shown in FIG. It is connected to terminal Cs. Therefore, only the configurations that are different from the second embodiment will be described.

The failure determination circuit 7 includes a Nant gate circuit 71 that inputs the outputs of the flip-flop circuits 4a...4n of the storage device 4 and performs logical operations such as logical AND NOT, and the output of the circuit 71 is as follows. , is input to the light emitting diode 72 and is also input to the control terminal Cs of the memory device 4.

Note that in the storage device 4 of this embodiment, the connection position of the input terminal 24 connected to the control terminal Cs is different from that of the above embodiments. That is, the AND gate circuit 21 is directly connected to the switching control terminal Cs.

An AND gate circuit 22 is connected to the control terminal Cs via an inverter 24.

However, if an AND gate circuit is used in place of the Nant gate circuit 71, the connection position of the input to output 24 will be the same as in each of the embodiments described above. and,
In this case, the relationship between turning on and turning off the light emitting diode 72 is opposite to the operation described below.

In such a configuration, if there is a failure in any of the functional blocks, the output of the Nant gate circuit 71 becomes "1", one light emitting diode 72 lights up, and a high level gate is output to the AND gate circuit 21 of the memory 4. The open signal is input, and the failure code signal stored in the memory 4 is input to the numerical display section 1.On the other hand, if there is no failure at all in each functional block, the output of the Nant gate circuit 71 is as follows.

It is turned on, and the gate opening signal inverted by the inverter 24 is input to the AND gate circuit 22, and the numerical information generating means 3 is connected to the numerical display section l.

Therefore, according to this embodiment, numerical information is normally displayed on the numerical display section, and when a failure occurs in the radar device, the number is automatically switched to display the number of the functional block where the failure occurs.

<Modifications of Embodiments> In each of the above embodiments, the switch 2 is configured with a logic switch element that combines an AND gate circuit and an OR gate circuit. may be configured.

For example, as shown in FIG.
Analog switch element and inverter 2 using 5.26
4 can be used. In this case,
Switching speed can be improved.

[Effects of the Invention] As explained above, the present invention provides a numeric display section of a radar device having a numeric display section for displaying numeric information such as a distance marker, by changing the display mode vJ by a switching command signal,
, By displaying the i location numerically, radar operators can easily check for the presence or absence of a failure and recognize the failure location on the panel surface whenever necessary, without having to check the lighting status of the light emitting element on the printed circuit board. I can do it. Therefore, according to the present invention, since it is possible to accurately notify service personnel of the location of the failure, necessary repair parts, etc. can be accurately*@, and the setup is not time-consuming and is efficient and quick. This has the effect of allowing repairs to be carried out on time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an overview of the fault location display device of the radar system 2 of the present invention, FIG. 2 is a time chart for explaining the operation of the fault location display device of the present invention having the above configuration, FIGS. 5 and 5 are block diagrams showing the configurations of the first to third embodiments of the failure location display device of the present invention, respectively, and FIG. 6 is a block diagram showing the configuration of the switch used in each of the above embodiments. FIG. 2 is a circuit diagram showing an example. DESCRIPTION OF SYMBOLS 1...Numeric display part 2...Switcher 3...Numeric information generation means 4...Memory device 4a, 4b...4n
...Flip-flop circuit 5...Clear signal generator 6...Switch 7...Failure judgment circuit 8a, 8b...8n...Failure diagnosis circuit 9a, 9b...
...9n...Printed circuit board 11...decoder
12... Drive circuit 13... Number display element 21.22... AND gate circuit 23... OR gate circuit 24... Inverter 3
2... Counter 51... Frequency divider 31.5
1... Clock pulse generator 71... Nant gate circuit 72... Light emitting diode

Claims (3)

[Claims] (1) The device has a fault diagnosis circuit for diagnosing faults for each functional block inside the device, and has a video display section that displays images and a numeric display section that displays numerical information such as distance markers. A fault location display device that is applied to a radar device having a fault diagnosis circuit and displays a fault location inside the radar device using a fault diagnosis signal from the fault diagnosis circuit, A memory device that forms a fault code signal that indicates a fault location of the radar device and temporarily stores the fault code signal; and a clear signal generator that forms a clear signal that resets the memory contents of the memory device at predetermined intervals. and a switching device that switches between the numeric information and the fault code signal and inputs it to the numeric display section in response to a switching command signal from the outside. Location display device. (2) The device has a fault diagnosis circuit for diagnosing faults for each functional block inside the device, and the display section includes a video display section that displays images and a numeric display section that displays numerical information such as distance markers. A fault location display device that is applied to a radar device having a fault diagnosis circuit and displays a fault location inside the radar device using a fault diagnosis signal from the fault diagnosis circuit, A memory device that forms a fault code signal that indicates a fault location of the radar device and temporarily stores the fault code signal; and a clear signal generator that forms a clear signal that resets the memory contents of the memory device at predetermined intervals. a switch that switches between the numerical information and the fault code signal and inputs it to the numerical display section in response to a switching command signal from the outside; and a switch that retrieves the fault code signal from the memory and determines whether or not there is a fault. What is claimed is: 1. A failure location display device for a radar device, comprising: a failure determination circuit that determines and displays a failure location display device for a radar device. (3) A failure location display device for a radar device according to claim 2, wherein the determination result of the failure determination circuit is inputted to the switching device as a switching command signal.