JPS6110373Y2 - - Google Patents
Info
- Publication number
- JPS6110373Y2 JPS6110373Y2 JP2163780U JP2163780U JPS6110373Y2 JP S6110373 Y2 JPS6110373 Y2 JP S6110373Y2 JP 2163780 U JP2163780 U JP 2163780U JP 2163780 U JP2163780 U JP 2163780U JP S6110373 Y2 JPS6110373 Y2 JP S6110373Y2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- switching
- circuits
- subtraction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000002131 composite material Substances 0.000 claims description 7
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 5
- 230000010363 phase shift Effects 0.000 claims description 5
- 102100036464 Activated RNA polymerase II transcriptional coactivator p15 Human genes 0.000 description 3
- 101000713904 Homo sapiens Activated RNA polymerase II transcriptional coactivator p15 Proteins 0.000 description 3
- 229910004444 SUB1 Inorganic materials 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 101150080287 SUB3 gene Proteins 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 230000005236 sound signal Effects 0.000 description 2
- 229910004438 SUB2 Inorganic materials 0.000 description 1
- 101100311330 Schizosaccharomyces pombe (strain 972 / ATCC 24843) uap56 gene Proteins 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000001010 compromised effect Effects 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 101150018444 sub2 gene Proteins 0.000 description 1
Landscapes
- Noise Elimination (AREA)
- Stereo-Broadcasting Methods (AREA)
Description
本考案はパイロツトトーン方式FMステレオ放
送のFMステレオ信号復調回路に関する。
従来のFMステレオ信号復調回路においては、
その出力音声信号中にパイロツト信号(19KHz)
が残留混入してしまうのを防ぐため、該回路の後
段にパイロツト信号除去用ハイカツトフイルタを
必要としている。しかるに、このフイルタの遮断
下限周波数は16〜18KHz程度であつてその遮断特
性の裾は15KHz付近まで及んでおり、この15KHz
という周波数がFM放送の音声周波数範囲の上限
にあたる結果、出力音声信号の高域周波数特性が
犠性となつていた。またこのフイルタで生ずる位
相偏移の及ぼす悪影響も多大であり、不都合であ
つた。
本考案の目的は、上述したような従来の不都合
を解消するFMステレオ信号復調回路を提供する
ことにある。
以下、本考案の一実施例につき、図面に基づい
て説明する。
図中、INは図示しない前段検波回路から出力
されるFMステレオコンポジツト信号D(t)を
入力する入力端、SGはコンポジツト信号D
(t)のサブキヤリヤ(38KHz)の位相を基準に
して夫々π/2ラジアンずつ位相が異なりかつサブ
キヤリヤと同一周波数を有する4つの非対称方形
波スイツチング信号a,b,c,dを出力するス
イツチング信号発生回路、S1,S2,S3,S
4は前記スイツチング信号a,b,c,dにより
夫々別にコンポジツト信号D(t)をスイツチン
グするスイツチング回路、C1〜C4はコンデン
サ、A1〜A4はバツフア増幅回路、PCはパイ
ロツト信号除去回路、SUB1〜SUB3は減算回
路、PS1はその入力信号の位相を進ませる進相
回路、PS2はその入力信号の位相を遅らせる遅
相回路、LC1,LC2はレベル調整回路、L−
OUTは左信号出力端、R−OUTは右信号出力端
を夫々示す。
以上の構成において、まずコンポジツト信号D
(t)を、
D(t) =(L+R)+(L−R)sinωct+psin
ωc/2t …(1)
但し、L+R:メイン信号
L−R:サブ信号
ωc:サブキヤリヤ角周波数
ωc/2:パイロツト信号角周波数
p:パイロツト信号レベル
とする。
次にスイツチング信号発生回路SGから出力さ
れる4つのスイツチング信号a,b,c,dを数
式で表わす。これらはサブキヤリヤの位相を基準
にして夫々π/2ずつずれた信号であるから、サブキ
ヤリヤとの位相差をa…0b…π/2c…πd…−π/2
とすれば、
a=s0+s1sinωct+s2sin2ωct+… …(2)
b=s0−s1cosωct−s2sin2ωct+… …(3)
c=s0−s1sinωct+s2sin2ωct+… …(4)
d=s0+s1cosωct−s2sin2ωct+… …(5)
のようにフーリエ展開される。
(2)〜(5)式で示したスイツチング信号a〜dによ
り、スイツチング回路S1〜S4においてコンポ
ジツト信号D(t)を夫々スイツチングすると、
バツフア増幅回路A1〜A4からは夫々信号f1〜
f4が出力される。
なお、ここではパイロツト信号角周波数ωc/2に
ついて考察しているため、信号a〜dの第3項ま
でをとつて計算する。
f2=b×D(t)
=s0(L+R)+s1/2psinωc/2t+s0psin
ωc/2t…
(7)
f4=d×D(t)
=s0(L+R)−s1/2psinωc/2t+s0psin
ωc/2t…
(9)
但し、φ=tan-1s1/2s0である。
これらの信号f1〜f4のうち、まず信号f2と信号f4
にパイロツト信号除去回路PC中の減算回路SUB
3によつて減算操作を加えると、信号f5が得られ
る。
f5=f2−f4=s1psinωc/2t …(10)
この信号f5はパイロツト信号そのものから成り立
つ信号である。従つて、信号f5の位相を進相回路
PS1によつてψだけ進ませ、レベルをレベル調
整回路LC1によつて
The present invention relates to an FM stereo signal demodulation circuit for pilot tone FM stereo broadcasting. In the conventional FM stereo signal demodulation circuit,
Pilot signal (19KHz) in its output audio signal
In order to prevent residual contamination, a high-cut filter for removing pilot signals is required at the subsequent stage of the circuit. However, the cutoff lower limit frequency of this filter is about 16 to 18KHz, and the tail of its cutoff characteristics extends to around 15KHz.
As a result, this frequency was at the upper limit of the audio frequency range of FM broadcasting, and as a result, the high frequency characteristics of the output audio signal were compromised. In addition, the adverse effects of the phase shift caused by this filter were significant and inconvenient. An object of the present invention is to provide an FM stereo signal demodulation circuit that eliminates the conventional disadvantages as described above. Hereinafter, one embodiment of the present invention will be described based on the drawings. In the figure, IN is an input terminal into which the FM stereo composite signal D(t) output from the front-stage detection circuit (not shown) is input, and SG is the input terminal for inputting the composite signal D.
Switching signal generation that outputs four asymmetric square wave switching signals a, b, c, and d, each having a phase difference of π/2 radians based on the phase of the subcarrier (38KHz) of (t) and having the same frequency as the subcarrier. circuit, S1, S2, S3, S
4 is a switching circuit that separately switches the composite signal D(t) according to the switching signals a, b, c, and d, C1 to C4 are capacitors, A1 to A4 are buffer amplifier circuits, PC is a pilot signal removal circuit, and SUB1 to C4 are capacitors. SUB3 is a subtraction circuit, PS1 is a phase advance circuit that advances the phase of its input signal, PS2 is a phase delay circuit that delays the phase of its input signal, LC1 and LC2 are level adjustment circuits, and L-
OUT indicates the left signal output end, and R-OUT indicates the right signal output end. In the above configuration, first, the composite signal D
(t), D(t) = (L+R)+(L-R) sinω ct + psin
ω c /2t (1) where L+R: main signal LR: sub signal ω c : subcarrier angular frequency ω c /2: pilot signal angular frequency p: pilot signal level. Next, the four switching signals a, b, c, and d output from the switching signal generation circuit SG will be expressed by mathematical expressions. These are signals that are shifted by π/2 with respect to the phase of the subcarrier, so if the phase difference with the subcarrier is a...0b...π/2c...πd...-π/2, then a=s 0 +s 1 sinω ct +s 2 sin2ω ct +… …(2) b=s 0 −s 1 cosω ct −s 2 sin2ω ct +… …(3) c=s 0 −s 1 sinω ct +s 2 sin2ω ct +… …( 4) Fourier expansion is performed as follows: d=s 0 +s 1 cosω ct −s 2 sin2ω ct +… (5). When the composite signal D(t) is switched in the switching circuits S1 to S4 using the switching signals a to d shown in equations (2) to (5), respectively,
The buffer amplifier circuits A1 to A4 output signals f 1 to A4, respectively.
f 4 is output. Note that since the pilot signal angular frequency ω c /2 is considered here, the third terms of the signals a to d are taken for calculation. f 2 =b×D(t) =s 0 (L+R)+s 1 /2psinω c /2t+s 0 psin
ω c /2t… (7) f 4 =d×D(t) =s 0 (L+R)−s 1 /2psinω c /2t+s 0 psin
ω c /2t… (9) However, φ=tan −1 s 1 /2s 0 . Among these signals f 1 to f 4 , first, signal f 2 and signal f 4
The subtraction circuit SUB in the pilot signal removal circuit PC
After adding the subtraction operation by 3, the signal f 5 is obtained. f 5 =f 2 −f 4 =s 1 psinω c /2t (10) This signal f 5 is a signal consisting of the pilot signal itself. Therefore, the phase of the signal f5 is changed to the phase advance circuit.
PS1 advances it by ψ, and the level is adjusted by level adjustment circuit LC1.
【式】倍し
たうえで、これを減算回路SUB1において信号f1
に逆相で加えてやれば信号f6を得る。
f6=s0(L+R)+s1/2(L−R)…(11)
また同様に、信号f5の位相を遅相回路PS2によつ
てψだけ遅らせ、レベルをレベル調整回路LC2
によつて[Formula] After multiplying this, the subtraction circuit SUB1 outputs the signal f 1
If you add it in reverse phase, you will get a signal f 6 . f 6 = s 0 (L + R) + s 1 /2 (L - R) (11) Similarly, the phase of the signal f 5 is delayed by ψ by the phase delay circuit PS2, and the level is adjusted by the level adjustment circuit LC2.
by
【式】倍したうえで、こ
れを減算回路SUB2において信号f3に逆相で加え
てやれば信号f7を得る。
f7=s0(L+R)−s1/2(L−R)…(12)
すなわち、信号f6及び信号f7を見れば明らかなよ
うに、これは純粋な左信号及び右信号となつてお
り、もはやパイロツト信号は完全に消去されてい
るのである。
以上、詳細に述べたように、本考案に係るFM
ステレオ信号復調回路によれば、フイルタを用い
なくともパイロツト信号を効果的に除去すること
ができ、従つてフイルタ使用に伴う周波数特性の
劣化(この場合特に15KHz付近の高域特性の劣
化)や、位相偏移等の有害な現象の併発を完全に
防止し得ると共に、その構成上、入力パイロツト
信号レベルが増大するようなことがあつたとして
も、出力信号中にパイロツト信号やサブキヤリヤ
が漏洩する虞れは全くない等、本考案回路は極め
て優れた特長を具有するものである。[Formula] Multiply this and add it to the signal f 3 in the opposite phase in the subtraction circuit SUB2 to obtain the signal f 7 . f 7 = s 0 (L + R) - s 1 /2 (L - R)...(12) In other words, as you can see from the signal f 6 and signal f 7 , this becomes pure left and right signals. The pilot signal has now been completely erased. As described above in detail, the FM according to the present invention
According to the stereo signal demodulation circuit, the pilot signal can be effectively removed without using a filter, and therefore the deterioration of frequency characteristics caused by using a filter (in this case, the deterioration of high frequency characteristics especially around 15KHz) can be eliminated. It is possible to completely prevent the simultaneous occurrence of harmful phenomena such as phase shift, and due to its configuration, even if the input pilot signal level increases, there is no possibility that the pilot signal or subcarrier will leak into the output signal. The circuit of the present invention has extremely excellent features, such as having no defects at all.
図面は、本考案に係るFMステレオ復調回路の
一実施例を示す回路ブロツク図である。
IN…入力端、SG…スイツチング信号発生回
路、S1〜S4…スイツチング回路、C1〜C4
…コンデンサ、A1〜A4…バツフア増幅回路、
PC…パイロツト信号除去回路、SUB1〜SUB3
…減算回路、PS1…進相回路、PS2…遅相回
路、LC1,LC2…レベル調整回路、L−OUT
…左信号出力端、R−OUT…右信号出力端。
The drawing is a circuit block diagram showing an embodiment of the FM stereo demodulation circuit according to the present invention. IN...Input terminal, SG...Switching signal generation circuit, S1-S4...Switching circuit, C1-C4
...Capacitor, A1-A4...Buffer amplifier circuit,
PC...Pilot signal removal circuit, SUB1 to SUB3
...subtraction circuit, PS1...phase advance circuit, PS2...delay phase circuit, LC1, LC2...level adjustment circuit, L-OUT
...Left signal output terminal, R-OUT...Right signal output terminal.
Claims (1)
との位相差が夫々0゜,90゜,180゜,270゜であ
りかつその周波数がサブキヤリヤの周波数と同一
である第1、第2、第3、第4の非対称方形波ス
イツチングを出力するスイツチング信号発生回路
と、 第1、第2、第3、第4のスイツチング信号の
夫々によつて各別にFMステレオコンポジツト信
号をスイツチングする第1、第2、第3、第4の
スイツチング回路と、 第2および第4のスイツチング回路の出力と減
算する第1の減算回路と、第1の減算回路の出力
を各別に移相する第1、第2の移相回路と、第
1、第2の移相回路の出力レベルを各別に調整す
る第1、第2のレベル調整回路と、第1、第3の
スイツチング回路の出力から第1、第2のレベル
調整回路の出力を夫々各別に減算する第2、第3
の減算回路とを有するパイロツト信号消去回路と
を備えたことを特徴とするFMステレオ信号復調
回路。[Claims for Utility Model Registration] First and second signals whose phase difference with the subcarrier of the FM stereo composite signal is 0°, 90°, 180°, and 270°, respectively, and whose frequency is the same as that of the subcarrier. , a switching signal generation circuit that outputs third and fourth asymmetric square wave switching signals, and a switching signal generation circuit that individually switches the FM stereo composite signal by each of the first, second, third and fourth switching signals. a first subtraction circuit that subtracts the outputs of the second and fourth switching circuits, and a first subtraction circuit that separately phase-shifts the outputs of the first subtraction circuits. , a second phase shift circuit, first and second level adjustment circuits that separately adjust the output levels of the first and second phase shift circuits, and a first level adjustment circuit that adjusts the output levels of the first and third switching circuits. , second and third subtracting the output of the second level adjustment circuit, respectively.
1. An FM stereo signal demodulation circuit comprising: a subtraction circuit; and a pilot signal cancellation circuit having a subtraction circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2163780U JPS6110373Y2 (en) | 1980-02-21 | 1980-02-21 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2163780U JPS6110373Y2 (en) | 1980-02-21 | 1980-02-21 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS56123657U JPS56123657U (en) | 1981-09-19 |
JPS6110373Y2 true JPS6110373Y2 (en) | 1986-04-03 |
Family
ID=29617792
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2163780U Expired JPS6110373Y2 (en) | 1980-02-21 | 1980-02-21 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6110373Y2 (en) |
-
1980
- 1980-02-21 JP JP2163780U patent/JPS6110373Y2/ja not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS56123657U (en) | 1981-09-19 |
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