JPS61101138A - Frame synchronization method - Google Patents
Frame synchronization methodInfo
- Publication number
- JPS61101138A JPS61101138A JP59222051A JP22205184A JPS61101138A JP S61101138 A JPS61101138 A JP S61101138A JP 59222051 A JP59222051 A JP 59222051A JP 22205184 A JP22205184 A JP 22205184A JP S61101138 A JPS61101138 A JP S61101138A
- Authority
- JP
- Japan
- Prior art keywords
- synchronization
- frame
- frame synchronization
- synchronization method
- code rule
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
- H04L7/0066—Detection of the synchronisation error by features other than the received signal transition detection of error based on transmission code rule
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/04—Speed or phase control by synchronisation signals
- H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明はディジタル伝送系のフレーム同期方式に係り、
特に同期復帰による情報欠除が問題となる伝送システム
に好適なフレーム同期方式に関する。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a frame synchronization method for a digital transmission system.
In particular, the present invention relates to a frame synchronization method suitable for transmission systems where information loss due to synchronization recovery is a problem.
従来のフレーム同期方式では同期パターンの検出のみを
行なっていたため、誤同期となる恐れがあり、また同期
がとれるまでの数フレーム分の情報が欠除してしまう欠
点があった。誤同期を防ぐためたとえば特公昭５０−７
８８９、特開昭５９−２４５６に記載されているように
パリティピットを誤同期検出に用いる方法が考案されて
いるが、１フレームに１〜２回しか検出できないため、
情報の欠除はすくえなかった。Since conventional frame synchronization methods only detect synchronization patterns, there is a risk of erroneous synchronization, and there is also the drawback that information for several frames until synchronization is achieved is lost. To prevent incorrect synchronization, for example,
A method of using parity pits to detect false synchronization has been devised as described in 889 and Japanese Patent Application Laid-open No. 59-2456, but since it can only be detected once or twice in one frame,
The lack of information was irresistible.
本発明の目的は同期復帰による情報の欠除を少なくする
ことが可能なフレーム同期方式を提供することにある。An object of the present invention is to provide a frame synchronization method that can reduce the loss of information due to synchronization recovery.
光デイジタル伝送系では２仏僧号を送るため。 The optical digital transmission system is used to transmit the names of two Buddhist monks.
直流成分抑圧を目的としたｍＢｎＢ、ｎＢｌｃなどの伝
送符号が一般に用いられている。受信端ではこれらの符
号則チェックにより伝送路の誤り検出を行なうが、本発
明はこの結果をもとにフレーム同期の動作を制御するこ
とで情報の欠除を防ぐものである。すなわち、符号則チ
ェックは１フレーム内で多数回行なわれるため、同期パ
ターン検出によるより短時間で同期はずれ、誤同期の検
出が可能であり、再ハンチングの動作に迅速に移ること
が可能となる。Transmission codes such as mBnB and nBlc aimed at suppressing DC components are generally used. At the receiving end, errors in the transmission path are detected by checking these coding rules, and the present invention prevents information from being deleted by controlling frame synchronization operations based on these results. That is, since the code rule check is performed many times within one frame, synchronization can be lost in a shorter time than by synchronization pattern detection, erroneous synchronization can be detected, and re-hunting can be started quickly.
以下、本発明の一実施例を第１図により説明する。１は
光受信機であり、受信光潜号を識別再生してフレーム分
離回路４に出力する。フレーム分離回路４は受信信号か
らフレームパターン、サービス信号などを取り除き、情
報ビットだけをバッファメモリ（図示せず）に送り出す
にの時に必要な各種タイミング信号はタイミング発生回
路５から供給される。そのためにはフレーム同期をとる
必要があり、従来からフレーム同期パターン検出によ−
るフレーム同期回路２が用いられている。An embodiment of the present invention will be described below with reference to FIG. Reference numeral 1 denotes an optical receiver, which identifies and reproduces the received optical latent code and outputs it to the frame separation circuit 4. The frame separation circuit 4 removes frame patterns, service signals, etc. from the received signal, and is supplied with various timing signals necessary for sending only the information bits to a buffer memory (not shown) from the timing generation circuit 5. To achieve this, it is necessary to establish frame synchronization, and conventionally, frame synchronization pattern detection has been used.
A frame synchronization circuit 2 is used.
しかし、フレーム同期パターンの検出のみでは同期復帰
に数フレームかかる欠点があるため本発明ではさらに伝
送符号則誤り検出回路３を用いて同期はずれを検出する
ものである。伝送符号としては公衆回線の１００ Ｍ
ｂ ／ ｓ系では８ＢＩＣが用いられていて、符号則誤
り検出回路も公知のものが存在する。However, since detection of a frame synchronization pattern alone has the disadvantage that it takes several frames to recover synchronization, the present invention further uses a transmission code rule error detection circuit 3 to detect synchronization loss. The transmission code is 100M for public lines.
In the b/s system, 8BIC is used, and there are also known code rule error detection circuits.
フレーム構成は第２図のようであり、４つのサブフレー
ムからなっている。第２図でＦ１〜Ｆ４がフレーム同期
パターンである。従って１周期にわたりパターンの一致
をみないと同期はずれかどうか検出できない。一方８Ｂ
ＩＣ符号されたものを１ワードとすると１つのサブフレ
ームに１６ワード含まれるが、そこで符号則誤りが数回
起これば同期はずれと見なしてかまわない。たとえば伝
送路誤り率が１０−Ｇ程度とすればフレーム同期が合っ
ているにもかかわらず符号則誤りが１サブフレーム内で
ｎ回起る確率は、
Ｅ＝（１−ε）１′−“・ε１ εまただしＥは伝送
路誤り率（＝ １０−’）。The frame structure is as shown in FIG. 2, and consists of four subframes. In FIG. 2, F1 to F4 are frame synchronization patterns. Therefore, it is impossible to detect whether the synchronization is out of synchronization unless the patterns match over one cycle. On the other hand 8B
One subframe contains 16 words, but if a coding rule error occurs several times, it can be considered as an out-of-synchronization. For example, if the transmission path error rate is about 10-G, the probability that a coding error will occur n times in one subframe despite frame synchronization is E=(1-ε)1'-"・ε1 ε where E is the transmission path error rate (= 10-').
従ってｎ ＞ ３とすればＥ ＜ １０−”であり現実
には起らない。そこで１サブフレーム内で符号則誤りが
３回以上起った場合フレーム同期はずれと判断し、フレ
ーム同期回路２に制御信号を送出すれば１サブフレーム
内で再ハンチングモードとすることが可能となり、フレ
ーム同期復帰の高速化が実現できる。従って情報の欠除
も最小限に抑えられる。Therefore, if n > 3, E <10-'', which does not occur in reality. Therefore, if a coding rule error occurs three or more times within one subframe, it is determined that the frame synchronization is out of order, and the frame synchronization circuit 2 By sending a control signal, it becomes possible to enter the re-hunting mode within one subframe, realizing faster recovery of frame synchronization.Therefore, deletion of information can also be minimized.
本発明によれば復帰時間の短縮が図れるため情報欠除が
少なくなり、回線の信頼性も向上できる。According to the present invention, it is possible to shorten the recovery time, thereby reducing information loss and improving the reliability of the line.
符号則誤り回路は回線監視用として通常設けられている
ものであり、本発明のために特に複雑な回路は必要とし
ない。The code rule error circuit is normally provided for line monitoring, and the present invention does not require any particularly complex circuitry.
第１図は本発明の一実施例のブロック図、第２図はフレ
ーム構成例を示す説明図である。
１・・・光受信機、２・・・フレーム同期回路、３・・
・符号則誤り検出回路、４・・・フレーム分離回路、５
・・・り寥２因FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is an explanatory diagram showing an example of a frame configuration. 1... Optical receiver, 2... Frame synchronization circuit, 3...
- Code rule error detection circuit, 4... Frame separation circuit, 5
・・・2nd reason
Claims (1)
ル伝送系のフレーム同期方式において、伝送符号則検出
回路および同期パターン検出回路を備え１フレーム内で
予め定めた個数以上の符号則誤りを検出した場合強制的
に再ハンチングさせ、１フレーム内で連続して所定以上
の符号則一致を検出した場合は同期がとけたと見なすこ
とを特徴としたフレーム同期方式。In a digital transmission frame synchronization method that encodes the transmitted signal and adds a synchronization pattern, it is equipped with a transmission code rule detection circuit and a synchronization pattern detection circuit, and is forced when more than a predetermined number of code rule errors are detected in one frame. A frame synchronization method is characterized in that re-hunting is performed, and if a predetermined or higher code rule match is detected consecutively within one frame, it is considered that synchronization has been achieved.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59222051A JPS61101138A (en) | 1984-10-24 | 1984-10-24 | Frame synchronization method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59222051A JPS61101138A (en) | 1984-10-24 | 1984-10-24 | Frame synchronization method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61101138A true JPS61101138A (en) | 1986-05-20 |
Family
ID=16776325
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59222051A Pending JPS61101138A (en) | 1984-10-24 | 1984-10-24 | Frame synchronization method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61101138A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2608871A1 (en) * | 1986-12-18 | 1988-06-24 | Cit Alcatel | Time-division method of multiplexing and demultiplexing synchronous digital streams |
| FR2631762A1 (en) * | 1988-05-18 | 1989-11-24 | Cit Alcatel | FRAME SYNCHRONIZATION DEVICE FOR A BLOCKED SYNCHRONOUS DIGITAL TRAIN USING A BLOCK CODE AND FRAME STRUCTURE |
| US5247546A (en) * | 1990-06-29 | 1993-09-21 | International Business Machines Corporation | Method and apparatus for automatic functional speed setting of a data circuit terminating equipment |
-
1984
- 1984-10-24 JP JP59222051A patent/JPS61101138A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2608871A1 (en) * | 1986-12-18 | 1988-06-24 | Cit Alcatel | Time-division method of multiplexing and demultiplexing synchronous digital streams |
| FR2631762A1 (en) * | 1988-05-18 | 1989-11-24 | Cit Alcatel | FRAME SYNCHRONIZATION DEVICE FOR A BLOCKED SYNCHRONOUS DIGITAL TRAIN USING A BLOCK CODE AND FRAME STRUCTURE |
| US5247546A (en) * | 1990-06-29 | 1993-09-21 | International Business Machines Corporation | Method and apparatus for automatic functional speed setting of a data circuit terminating equipment |
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