JPS61101048A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce the wiring capacitance and the inductance component of the titled device as well as to perform a high speed operation on a circuit by a method wherein a pair of emitter follower transistor constituting a logic gate circuit are symmetrically arranged, and an input transistor and a comparison transistor are arranged almost symmetrically on both sides of said transistors. CONSTITUTION:A pair of collector resistors RC1 and RC2 constituting an emitter coupled logic circuit, emitter follower transistors TrQ3 and Q4, and emitter resistors RL1 and RL2 are symmetrically arranged in such a manner that they are closely positioned with one another. A plurality of input TrQ11-Q12 and a comparison TrQ2 are arranged almost symmetrically on the reverse side of TrQ2 are arranged almost symmetrically on the reverse side of TrQ3 and Q4 pinching the resistors RC1 and RC2. As a result, the length of wirings between the TrQ11-Q13 or a TrQ2 and the resistors RC1-RC2 and TrQ3 and Q4 can be brought to the minimum, and the wiring capacitance and the inductance component are reduced, thereby enabling to improve the working speed of the circuit.

Description

[Detailed Description of the Invention] [Field of Apparatus] The present invention relates to an apparatus that is particularly effective when applied to the layout of elements constituting semiconductor integrated circuit devices and logic gate circuits, such as emitter-coupled logic circuits. (or current mode logic circuit)
The present invention relates to a device that is effective for use in layout of elements in a device.

[Background Device] An emitter-coupled logic circuit (hereinafter referred to as an ECL circuit) as shown in FIG. 1, for example, is known as a basic gate circuit constituting a logic LSI (large scale integrated circuit). When constructing a logic LSI such as a gate array using such an E C1 circuit as a basic gate circuit, the gate array generally has a high degree of integration and the element size is quite small, so there is no need to pay much attention to the layout of the elements. It was thought that the circuit would operate at a sufficiently high speed.

Therefore, the layerer 1 of the elements in the ECL circuit in the Goo 1-array, which uses the conventional ECL circuit as the basic gate circuit.
~ is, for example, IEEE 1980 P1112-P
1] 16 “MU I T I-LEV E L METAL
As shown in ``LEVERAGE'', this was done mainly from the viewpoint of making wiring easier, especially making it easier to connect to the power supply line.

However, even in highly integrated logic LSIs such as the Goo1-Array, the load resistance (
Collector resistance) R, cl and the wiring to the base of the 1-transistor (hereinafter referred to as emitter-follower transistor) Q3 that constitutes the emitter follower, and the 1-transistor Q2 for comparison to which the reference voltage VBD is applied.
If the wiring from the collector to the load resistor Rc 2 and the emitter follower 1 to the base of the transistor Q4 is redundant, the length of the wiring will be longer than if the wiring was made as short as possible due to the capacitance and inductance components of the wiring. It was found that the gate delay time increased by nearly 50%.

[Object of the Invention] An object of the present invention is to provide a layerer 1 system that allows a logic gate circuit for configuring a logic LSI such as a gate array to operate at the highest speed.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] Representative inventions disclosed in this application will be summarized as follows.

=3- In other words, a pair of collector resistors and an emitter follower transistor and their emitter resistors constituting a logic gate circuit such as an ECL circuit are arranged close to each other and symmetrically, and with the collector resistor marked -F in between. By arranging a plurality of input transistors and a comparison transistor that constitutes a current switch circuit with them on the opposite side of the emitter follower transistor, the collector of the input transistor or comparison transistor can be connected to its load resistance and the emitter follower transistor.・Make sure the length of the wiring to the transistor is as short as possible,
The purpose of this invention is to reduce the wiring capacitance and inductance component, thereby enabling the logic gate circuit to operate at the highest speed.

[Embodiment] FIG. 2 shows an embodiment of the layout of a basic circuit cell when the present invention is applied to a 1-array having an ECL circuit as a basic gate circuit.

In this embodiment, the base regions B, 1 to B13 and the emitter regions E1 . ~E13 and collector drawer area C・
11 to C13 are formed side by side, respectively. Among these, emitter regions E11 to E13 are connected to each other by a connection line L11 made of a first aluminum layer.

A power supply line L2'l made of a second aluminum layer is arranged along the vertical direction approximately in the center of the drawing, and a single input transistor Qll is placed on both sides of this power supply line L21.
A base region B2, an emitter region E2, and a collector lead-out region C2 of a comparison transistor Q2 are formed on the opposite side of Q13. This comparison 1- transistor Q
The base region B2 of No. 2 is connected to the VBB line L22, which is also formed from the second aluminum layer, adjacent to and parallel to the power supply line L21, via the connection line L12 made of the first aluminum layer. It is connected.

The aluminum connection line L12 and the VNE line 422 are connected through a through hole TH.

In addition, in the center of the drawing, collector resistors R and c made of polysilicon are shown perpendicular to the power supply lines l and 21.
1 and Rc2 are formed continuously.

This collector resistance Rc1. Base regions B3+ of emitter follower transistors Q3 and Q4 are located on the opposite side of the transistors Q11 to Q13 and Q2 across Rc2.
84 and emitter regions E3 and E4 are formed symmetrically across the power supply line L21, and the power supply lines r, 21
Below these emitter follower transistors Q3
A common collector draw-out area C34 for Q4 and Q4 is formed.

Each of the collector lead-out regions C11 to C13 of the input transistors Q11 to Q13 and its collector resistance Rc
1 and emitter follower transistor Q3
are connected to the base region B3 by aluminum connection lines 1 and 3 made of the first aluminum layer. Similarly, the collector lead-out region C2 of the comparison transistor Q2, one end of its collector resistor Rc2, and the base region B/I of the emitter follower 1 to transistor Q are connected to the aluminum connection line L13 of the first layer. ' are connected to each other by.

In addition, the above emitter follower 1 to transistor Q3, Q
The common collector draw-out area C34 of No. 4 is an auxiliary power line L made of a first layer of aluminum formed below and parallel to the power line L21, although it is not particularly limited.
14 to the second-layer power supply line L21, and is supplied with a power supply voltage Vcc. 1. The connection line Ll'1 is coupled to the power supply line L21 through the through hole TH2. by this,
Emitter follower 1-transistor Q3. Q4 is on,
The influence of fluctuations in the power supply voltage caused by turning off and causing current to flow or being cut off is made less likely to be transmitted to the power supply voltage on the current switch circuit side.

Further, in the vicinity of the emitter follower 1 helangistors Q3 and 04, emitter follower resistors RL1 and R1,2 made of polysilicon layers are formed toward the outside, and the resistors R1-1 and R,L2 are formed outwardly. One end is connected to the emitter follower transistor Q3 by a connection line [,15 and 17,5' made of the first aluminum layer formed in a U-shape so as to go around the outside of the base regions B3 and B4, respectively. and Q4 are connected to emitter regions E3 and E4, respectively.

The other ends of the resistors R1-1 and R, L2 are connection lines L16 and (2), respectively, which are made of the first aluminum layer.

16', power supply lines L21 are connected to both sides of the cell, respectively.
They are connected to V77 lines T, 23 and I, 24, respectively, which are made of a second aluminum layer disposed in a direction parallel to the line, and a power supply voltage TT is applied thereto. Connection line L16 and vT7 line L'23 are connected through through hole T H3, and connection line L16' and v1 alignment ■
:24 are connected to each other through a through hole TH4.

In the above layout configuration, the transistors Q11 are arranged approximately symmetrically across the power supply line L2.
Since the transistor Q2 side of Q13 and Q2 has a small number of elements, a blank space is generated when the cells are accommodated in a rectangular area. In this embodiment, although not particularly limited, this blank area adjacent to the comparison transistors 1 to Q2 is utilized to draw out the collector lead-out region C5, emitter region E5, and base region B5 of the constant current transistor Q5.
is formed. Then, "1 input 1 helangistor Q11-Q, emitter region E1. ~E.

The connection line I41.3 connects the emitter region E2 of the comparison 1 to transistor Q2. is extended and connected to the collector lead-out region C5 of the constant current transistor Q5.

The base region B5 of constant current 1 to transistor Q5 is vT
It is connected to the wiring L25, which is also formed from the second aluminum layer on the outside of the o-line L24 and in parallel thereto, via a connection line L17 made from the first aluminum layer, so as to receive a constant voltage Vcs. It is being done. The connection line L17 and the wiring L25 are coupled through a through hole TH5.

Further, in the blank space between the region where the constant current transistor Q5 and the emitter follower resistor RL2 are formed, an emitter resistor R5 for a constant current source made of a polysilicon layer like the resistor RL2 is formed. There is. One end (lower end in the drawing) of this emitter resistor R5 is connected to the emitter region E5 of the constant current transistor Q5 via connection lines 7 and 8 made of the first aluminum layer.

Further, the other end of the emitter resistor R5 is connected to the power supply lines 2, 21 and V via a connection line 1.19 which is also made of the first aluminum layer. A V line L26 formed of the first aluminum layer is connected between and in parallel with the ↑ line [, and the two lines, and a power supply voltage V:6 is applied thereto. The connection line r-, 9 and the Vap mill line 26 are connected through a through hole TI6.

According to the layout of the above embodiment, the input transistor Q
Among ll to Q11a, especially the collector lead-out region C12 of Q12, one end of the collector resistor Rc1, and the base region B3 of the emitter follower transistor Q3 are arranged close to each other on a substantially straight line, so that a connection line connecting them is The wiring length of Li3 becomes the shortest. In addition, since the collector lead-out region C2 of the comparison transistor Q2, one end of the collector resistor Rc2, and the base region B4 of the emitter follower 1 to the transistor Q4 are arranged close to each other in a substantially straight line, they are connected. The wiring length of the connection line L13' is also minimized.

As a result, input l and transistor Q1. ~The capacitance and inductance components of the wiring connected to Q13 and the collector of the comparison transistor Q2 are reduced, and the operating speed of the ECL circuit is increased by -1, allowing it to operate at the maximum speed determined by the element dimensions. .

Next, FIG. 3 shows a sectional view taken along the line ■-■ in FIG. 2.

On a semiconductor substrate 1 such as P-type m-crystalline silicon, N''-buried layers 2a and 2b are selectively formed in advance in correspondence to portions where elements (transistors) are to be formed.

Further, an isolation oxide film 3 is formed between each element and between the base region and the collector lead-out region.

And, in the above N''-Rikome Shukomi layer, 1- of 2b, N-
A type epitaxial layer 4 is formed, and by selectively shallowly doping P type impurities into this N- type epitaxial layer 4, transistors Q12 and 03. Base area B of Q4, 2. B3. P-type semiconductor region 5a which becomes B4,
5b and 5c are formed, respectively. In addition, the above N-
By selectively introducing N-type impurities deep into the type epitaxial layer (4) so as to reach the N+ buried layers 2a and 2b, an N-type semiconductor region 6a that becomes the collector lead-out region C12 of the input transistor Q12 and an emitter are formed. An N-type semiconductor region 6b is formed which becomes a common collector lead-out region C34 of follower transistors Q3 and Q4.

Further, on the P-type semiconductor regions 5a, 5b, 5c, one helangistor Q12 and one helangistor Q3. Thin N-type semiconductor regions 7a+7b, 7c, which will become the emitter region of Q4, are formed by selective ion implantation or the like.

On the isolation oxide film 3a between the transistors Q12 and Q3, there is a polysilicon layer 8 which becomes the collector resistance Rc1.
is formed by a CVD method (chemical vapor deposition method) or the like.

−12= And each of the semiconductor regions 5a to 5c, 6a.

6b and 7a to 7c and a part of the surface of the polysilicon layer 8, a contact hole 9 is formed, and a first aluminum layer is deposited thereon and patterned by selective etching to form an input signal line. The aluminum wiring layer 10a and the input transistor Q11~
An aluminum wiring layer 1. which becomes a connection line L-ii that connects the emitters of transistor Q13 and comparison transistor Q2 to each other.
Ob and the input transistor Ql 2 (Qll, Q1
3) A connection line L13 connecting the collector lead-out region C12 (C11, C13), one end of the collector resistor Rc1 (polysilicon layer 8), and the base region B3 (semiconductor region 5b) of the emitter follower transistor Q'3.
An aluminum wiring layer 10c and the like are formed.

Note that the aluminum wiring layer 1. Od, 1. Oe,
10 f.

tog are respectively connected to the connection line L16 in FIG.
+ r-14+ T-16'y This is the first aluminum wiring layer corresponding to r-13'.

On the aluminum wiring layer 10a-10g, PSG
An interlayer insulating film 11 such as a film (phosphorus silicate glass film) is formed, and on this interlayer insulating film 11, second aluminum wiring layers 12a and 12b, which mainly serve as power supply lines, are formed.
is formed. Aluminum wiring layer 12 shown in FIG.
a, 12b are power supply lines l-12, and VBB.
This is an aluminum wiring layer that becomes line L22. Although not shown, a final passivation film is formed on the first aluminum wiring layers 12a, 12b, . . . .

In the embodiment described above, the number of input transistors constituting the ECL circuit is three, but the number is not limited thereto, and the number may be two or four or more.

Furthermore, the resistors such as the collector resistors RC1+Rc2 may be diffused resistors made of a diffusion layer formed on the main surface of the semiconductor substrate instead of polysilicon resistors.

[Effect] E CL, a pair of collector resistors and emitter follower transistors constituting the circuit and their emitter resistors are arranged close to each other and symmetrically, and on the opposite side of the emitter follower transistor with the collector resistor in between. Since the multiple input transistors and the comparison transistors constituting the current switch circuit are arranged approximately symmetrically, the wiring from the collector of the input transistor or comparison transistor to the load resistor and emitter follower/1-transistor transistor is arranged almost symmetrically. Due to the effect that the length of E
This has the effect of allowing the L circuit to operate at the highest speed.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in Embodiment 1, a general conventional type L-transistor was illustrated and explained as an example, but the input 1-transistors Qz to Q13 constituting the ECL circuit and the comparison transistor Q
2 and =15- and emitter follower transistor Q3. It goes without saying that the structure of Q4 is not limited thereto, and may be a transistor of a graft base structure or a 5ST (super self-alignment transistor) structure.

In addition, in the embodiment 1, a constant current transistor Q5 is disposed beside the comparison transistor Q2, and an emitter resistor R
The emitter resistor R5 is disposed between L2 and the constant current transistor Q5, but the emitter resistor R5 is disposed between the transistor Q3 and the constant current transistor Q5.
The arrangement of 5 is not limited at all, and it can be arranged at any other position without diminishing the effects of the present invention.

[Field of Application] In the following explanation, the invention made by the present inventor is mainly applied to a gate array having an ECL circuit as a basic gate circuit, which is the field of application which is the background of the invention, but the present invention is not limited thereto. It can be used in general logic LSIs having ECL circuits and even NTL (non-threshold logic) circuits.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing an example of the configuration of an ECL circuit;
FIG. 3 is a plan view showing an example of the layout of an ECT circuit to which the present invention is applied, and FIG. 3 is a cross-sectional view taken along the line m-IH in FIG. Q11-Q13...Input transistor, Rcl. Rc2...Load resistance (collector resistance), Q3゜Q4
...Emitter follower 1 helangister, RL 1
r RL 2...Resistance for emitter follower, Q5...
・・・1 helan resistor for constant current, T-11~L19...
...Connection line, L21 to L'26...Power line, 1
...Semiconductor substrate, 2a, 2b...N''-buried layer, 3.3a...Isolation oxide film, 4...N-type epitaxial layer, 5a to 5b...・P-type semiconductor region (
base region), 5a, 6b... N-type semiconductor region (collector lead-out region), 7a to 7C... N-type semiconductor region (emitter region), 8... polysilicon layer (collector resistance), 9...Contact holes, 10a-l
og...First layer aluminum wiring layer (connection line), 11...
...Interlayer insulating film, 12a. 12b...Second aluminum wiring layer (power line). Condolences

Claims (1)

[Claims] 1. A semiconductor integrated circuit device comprising a logic gate circuit having a plurality of input transistors whose emitters are commonly connected to each other and an emitter follower connected to the collector terminals of these input transistors, a collector lead-out region of one of the input transistors, and one end of a load resistor connected to the collector of the input transistor;
A semiconductor integrated circuit device characterized in that base regions of transistors constituting an emitter follower are arranged close to each other and aligned substantially in a straight line. 2. When the logic gate circuit is an emitter-coupled logic circuit, a comparison transistor is provided along with the input transistor, its collector-side load resistance, and the first emitter follower transistor, approximately symmetrically thereto. 2. The semiconductor integrated circuit device according to claim 1, further comprising a collector-side load resistor and a second emitter follower transistor. 3. Above the boundaries of the symmetrically arranged elements,
A semiconductor integrated circuit according to claim 2, characterized in that wiring for supplying these power supply voltages is provided, and a common collector lead-out region of the two emitter follower transistors is formed under the wiring. circuit device.