JPS6097449A - Information processor with read-only memory - Google Patents

Abstract

PURPOSE:To make stored information hard to read and to improve a secrecy holding function by comparing ROM stored information of a data processor with information that a person who knows a program inputs externally on a chip without outputting the information, and making a decision. CONSTITUTION:When an address specification start signal 105 is generated, a start address value is set at an address specifying part 102, a state corresponding to decision result coincidence is set at a decision making part 104, and the address assignment of ROM101 is performed on the basis of address specifying information 107. The ROM101 transfers stored information on addresses to a comparison part 103 through an information transfer line 108. Comparative input information 109 inputted from outside the data processor is inputted to the comparison part 103 and a comparison result signal 110 is generated when the both do not coincide with each other and sent to the decision making means 104. The decision making part 104 changes into the state corresponding to the decision result dissidence when the comparison result signal 110 is generated, and when an address specification end signal 106 is generated by an address specifying part 102, a decision end signal 111 is outputted.

Description

[Detailed description of the invention] [Technical field to which the invention pertains] The present invention fl-J: tfjli exclusive memory (hereinafter referred to as R
(referred to as OM)'! The present invention relates to a data processing device including r-, and particularly to a device called a single-chip microcomputer in which a central processing unit, an input/output device, and a memory are integrated on a single semiconductor chip.

[Description of prior art]

In a single-chip microcomputer, a program dedicated to a user is written into a memory (ROM) on the chip during the manufacturing process of a semiconductor integrated circuit. The ROMK: Checking of the written storage information is performed by inputting ROM address information from outside the integrated circuit chip and outputting the accessed ROM information to the outside of the chip. Therefore, anyone can easily know the ROM information just by adding the address information, which poses a big problem in terms of maintaining the confidentiality of the program information.

[Purpose of the invention]

The purpose of the present invention is to provide an information processing device that can check the program contents without knowing the contents of the third device.〇 [Structure of the invention] A single-chip microcomputer executes a ROM program internally and communicates with the outside. Focusing on the fact that there is no need to output this information, the present invention provides a means for a person who knows the program to input all information from the outside and compare and judge this with the contents of the ROM on the chip. be a sign.

〔Effect of the invention〕

According to the present invention, the entire contents of the ROM can be checked on the second chip without being output to the outside of the chip, so that security against third parties is completely ensured. However, since only the comparison results are sufficient without checking the contents, the contents check can be done in a very simple manner.

[Explanation of Examples]

FIG. 1 is a block diagram showing the configuration of a data processing apparatus according to an embodiment of the present invention. In the figure, 100 is a data processing device, 101 is a ROM, 102 is an address designation section, 103 is a comparison section, 104 is a determination section, 105 to 111
05 is the address specification start signal, signal 06 is the address specification end signal,
Information 07 is address designation information, information 108 is ROM storage information, information 109 is comparison input information, signal 110 is a comparison result signal, and signal 1] is a determination end signal. The address designation unit 102 generates the address information 507 of the ROM10I and an address designation completion signal 106.The comparison unit 103 compares the storage information 108 of the ROM10I with the comparison input information 109 and outputs the result signal 110.The 0 determination unit 104 outputs the address Designation start signal 105 and address designation end signal 10
6 and a comparison result signal 110, a determination end signal 111 is output.

The operation of this circuit will be explained below. When the address designation start signal 105 is generated, the start address fit 'f: is set in the address designation unit 102, a state corresponding to the match of the determination result is set in the determination unit 104, and the ROM10I? Address. The ROM 101 transfers the stored information at the address to the comparison unit 103 via the information transfer line 108f. On the other hand, the comparison input information +11109 inputted from the outside of the data processing device lα) is inputted to the comparison unit 103 and compared with the storage information 108 from the ROM10I, and if they do not match, the comparison unit 103 generates a comparison result signal 111 and outputs a determination means. 04. Here, the address specifying unit 102 sequentially updates the address information, and in synchronization with the update, input comparison information 109'ft is changed and the comparison unit 103 continuously compares. When the comparison result signal 110 is generated, the determination unit 104 changes to a state corresponding to the determination result mismatch, and when the address designation end signal 106 from the address designation unit]02 is generated, the determination unit 104 determines the state of the 1'0 constant result. In other words, the data processing device of the embodiment shown in FIG. The input information and the ROM storage information were continuously compared based on the address specification, and a match was found up to address r of the address specification path. A match determination signal is output at the corner.

The comparing section 103 and the determining section 104 in the embodiment shown in FIG. 1 will be explained by showing their circuit configurations. FIG. 2 shows a comparison section] 03 Theory J1 ■ Circuit diagram 200 to 207 are comparison circuits, 208 is a comparison output circuit, and information A. ~7 represents storage information from the ROM, information BO~ represents comparison input information, and signal 209 represents comparison result output. Comparing circuits 200 to 207 each input information 0 to 7 and information 80 to γ and output exclusive logic F signals. The comparison output circuit 208 is the comparison circuit 200 to 207.
Takes the logical sum of the signals output from. This comparison part is ROM
Exclusive OR is performed on the stored information Ao~D and comparison input information B0~F by the comparison circuits 200~207, and when the results do not match, if the output of one of the comparison circuits is The comparison output circuit 208 performs a logical sum, and the comparison result signal 209 becomes '1'', and the comparison circuits 200 to 207
If all the comparison information matches, the comparison result signal 209 becomes '0'. Therefore, by comparing the ROM storage information and the comparison input information input from the outside, the meaning can be determined in case of cine matching. It has a function of outputting a signal 209 indicating the determination unit 104 to the determination unit. FIG.
Judgment termination circuits 304 to 308 indicate signal or transfer lines. Signal 305 is an address specification start signal, signal 306 is a comparison result signal, 1 bar number 304 is an address specification end signal,
The signal 3071-j is the judgment end signal, the signal 308 is the judgment end mismatch signal, and the judgment circuit 30] is a set-reset flip-flop that stores the judgment state based on the address designation start signal 3()5 and the comparison result signal 306'). (Hereafter R8-
The judgment end circuits 302 and 303 output a judgment end signal 307 and a judgment end mismatch signal 308, respectively, based on the addressing end information 304 and the output of the judgment circuit 301. Now address specification start signal 30
5 is generated, R8-F/F of the determination circuit 301 is set, and the address and comparison information are sequentially updated without generating the comparison result signal 306. When the address specification is completed, the address specification end signal 304 is generated. Said R8-F/
Output of F Q @ 1'', RO to the end address of the tsumashi address
If the information in M and the comparison information match, the AND output of the judgment end circuit 302 becomes 1'', and a judgment end signal 307 is output.On the other hand, if the comparison information and the information in the ROM do not match, the comparison section outputs A comparison result signal 306 is generated, R8-F/F of the judgment circuit 3ol is reset, and the output Q becomes '1'.
”, the output Q becomes @Oj!, so the judgment end circuit 303
The logical product of is l'', which outputs a multiple determination end mismatch signal 308. Note that the address designation unit 102 of the embodiment in FIG.
This is a counter for generating address information of M101, and updates the address value generated at regular intervals. Here, when the counter is counted up from the address designation end address, an overflow signal is generated, so the overflow signal is inputted to the determination end circuits 302 and 303 as the all address designation end signal 304. In the embodiment, if storage information judgment is started and the ROM information and input comparison information do not match, the RS of the judgment circuit 301 is changed during the judgment.
- With the F/F reset, the comparison is continued until the specified end address, and only when all comparisons are completed, the judgment result is output as a judgment end signal. Therefore, for those who know the ROM information of data processing equipment, the desired information can be correctly read by simply inputting all the information to be compared sequentially.
It can be easily determined whether or not it is stored in M. However, if a person who does not know the ROM information tries to know the stored information, it is necessary to try all the input comparison information and its sequence, and it takes a lot of time to read it, so this embodiment is a security protection method. For example, if one word of ROM content is 8 bits, one word can contain all 256 pieces of information.

If the ROM capacity is 8 words - Ml, and it takes 10 microseconds to extract the information, the time required to decode all the information in the ROM is 25 G'X IOX 10' seconds, which is converted into a year. It is about 580,000 years old. Here, the ROM capacity built into the data processing device *7: is more than 1000 words, and the description ↑ 1 is written by someone who does not know the 11v information. is 1
It is actually impossible for VC to try to know if information.

As described above, according to the present invention, it is possible to determine that information is correctly stored in the ROM without outputting all the ROM storage information of the number of data processing bags to the outside, and the effect is that it is difficult to read out the storage information, that is, it is not easy to steal the ItOM contents. was attacked,
It is possible to improve the confidentiality function.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the south block configuration of an embodiment of the present invention, FIG. 2 is a circuit diagram of the comparison section of the embodiment of FIG. 1, and FIG. 3 is a circuit diagram of the determination section of the embodiment of FIG. 1. ◎ 100... Data processing device, 1 (11...
...ROM. ]02・River・・Address specification section, 1o3・・・Comparison section, 104・・・Judgment section, 105・・・・
Addressing start signal, 106... Addressing end signal, 107... Address information, 108...
...ROM storage information, 109...Comparison 18th report, 110...Comparison result signal, 111...
...Judgment end signal, 200-207... River/comparison circuit, Ao-7...ROM storage information, 208... Group/comparison output circuit, B0-. ...Comparison input information,
209... Comparison result signal, 301...
Judgment circuit, 302.303 Old...Judgment end circuit, 30
4...Address specification end signal, 305...Address specification start signal, 306...Comparison result signal, 3
07... Group/judgment end signal, 308... Judgment end mismatch signal. Agent Patent Attorney Uchihara Oto 61?2 ノ ■8〈) 2nd Taku

Claims (1)

[Claims] In a data processing device having read q memories all on the same chip, a data input bus for inputting data from outside the chip and the read-only memory are connected to respective input terminals of the comparator, and An information processing device characterized in that the information stored in the read-only memory is checked by comparing data with the information stored in the read-only memory.