JPS6090399A - Voice recognition type scale scoring apparatus - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a tempo generation mechanism of a voice recognition type pitch notation device.

When singing a song, recognizing the pitch at which it occurs, and transcribing that pitch, it is common to sing the song in time with the tempo.

In other words, the pitch notation device must transcribe pitch by pitch in accordance with this tempo signal. in this case,
As a tempo generator, a constant and stable tempo signal is displayed, but as a user who sings, you have to start singing in accordance with this tempo signal. However, in a general tempo generation mechanism, the tempo is generated regardless of the user's will, so the song starts to sing after 141 seconds.

11 Town 1%lli 11, 1・1・zu・'
・, ・,', L LIlriting +1・ -χ・ +1
λ′ is also 1・l++! It+.

- After the start of the song, the transcription function is prohibited until the audio input is applied, and the tempo signal is synchronized at the beginning of singing by ensuring a predetermined tempo cycle from the time the audio is input. Let this be the first step.

Hereinafter, the present invention will be explained in detail according to the drawings.

FIG. 1 is a block diagram of the present invention.

11dOPU, 2t'! 3 is an address decoder, 3 is an audio pitch extracting section, 4 is a JRAM, 5 is a note display section, 6 is a musical tone generating section, 7 is a switch section, and 8 is a tempo generating section.

From aPUl, address decoder 2 hair torque signal A
D is connected and the data node (indicated by DATABU8)
is commonly connected to the data terminals from the audio pitch extracting section 3 to the switch section 7.

In addition, the RD multiplied signal from the O P Ul is connected to the RD terminals of the audio pitch extractor 3, RAM 4, and switch section 7, and the WR multiplied signal is connected to the RD terminals of the audio pitch extractor 3, RAM 4, and switch section 7, respectively. ' Connected to the WR terminal of L.

From the address decoder 2, the AD1 signal is sent to the AD\I No. 75 voice pitch extraction unit 3, and the AD1 signal is sent to the RAM 4,
The signal is connected to the note display section 5, the ADlo (iJ number) is connected to the music generation section 6, and the AD11-12 signal 75 is connected to the switch section 7. Also, a microphone for audio input (indicated by M'XC) is connected to the T1n, which is the output of the tempo generator 8, is sent to the tempo generator 8, which is the output of the pitch extractor 6)
The MP signals are respectively connected to the INT (interrupt) input terminals of cpυ1.

Next, the operation of each block will be briefly explained.

The address decoder 2 determines which block the 0PU1 is currently working on, and selects one of the four blocks.

The audio pitch extractor 3 amplifies the audio signal input from the microphone, selected by the AD\ signal output from the address decoder 2, detects the peak of the fundamental wave of this audio waveform, and divides the peak from peak to peak. Measure the time between
This is a block that stores the measured values. and,
If necessary (in this case, when 0PU1 selects AD\), data is loaded onto the data bus (indicated by DATA Bσ8). Further, the /L times signal shown in FIG. 1 is generated only when there is audio input, and its period is approximately equal to the pitch period of the audio input waveform.

RAM41-j, address decoder 2 output 6AD
V is selected by the 1 signal. RAM +T), the address input terminal is generally a number, but in the case of 1st figure, it is AD11.
Indicated to be accessed by words only.

Naturally, a plurality of address signals from apσ1 are connected to the RAM 4, but these are omitted in FIG. Therefore, the AD1 signal is a chip select signal for the RAM 4, as indicated by -C. Further, since the connection between OPσ1 and RAM4 is already known, the detailed connection relationship will not be described.

RAM 4 iJ is a block that stores pitch information obtained from the audio pitch extraction unit 3 (determined by i-OPUL and scale data after conversion. In other words, OP
U I &'j, the scale data obtained from the voice pitch extracting section 3 is written into the RAM 4 in order. Furthermore, when modifying or reproducing the stored scale data, the data stored in the RAM 4 is sequentially read out and processed.

The note display unit 5 is a block that sequentially displays a part of the data stored in the RAM 4, and is a liquid crystal or LmD
It consists of a display body and a drive circuit.

FIG. 2 is an external view of the display when configured with LEDs.

Implement LIItD corresponding to each scale on the 5-line staff, and
It is arranged so that the scale up to the note is displayed all at once. Also, a sharp L tu (indicated by #) for semitone display,
D is also implemented.

The musical tone generator 6 is a block that recognizes and converts the scale data stored in the RAM 4 and converts the scale data into musical tones, and also has the function of arbitrarily selecting a plurality of types of musical tones. The musical tone generation section 6 converts the scale data (data already stored in the RAM 4) instructed by the OPU 1 into a musical tone signal, amplifies this signal by a filter section and an amplification section, and drives a speaker.

The switch section 7 includes a mode switch section for setting each mode of recording, correction, and playback, and a mode switch section for setting each mode of recording, modification, and playback, and a mode switch section for setting each mode of recording, correction, and playback, and a start and control section for each mode.
It consists of end switches, a Kahnle movement switch in correction mode, an octave shift switch during correction or playback, and a key correction switch for correcting the key of the scale. These switch groups are also selected by AD11-12 signals, ! -Get on top of Tabas. 0PU11j
, reads this switch data from the data bus, and performs switch processing as necessary.

The tempo generator 8 includes a variable oscillation circuit whose oscillation frequency can be easily varied using a variable resistor, a seven-tempo generation section, a tempo generation circuit synchronized with the tempo signal, and a tempo display circuit that allows you to visually confirm the tempo. , consists of an audio-synchronized tempo control section with a 17ζ configuration so that the tempo signal is synchronized with the audio input;
Connect to T input (interrupt input).

Next, the operation of 0PUI will be explained according to the operating procedure. 0
PU1 is pruned by the TgMP signal,
The data of the audio pitch extractor 3 is read multiple times at a timing of about half of the period of this TEMR signal. That is,
When audio input is added in accordance with the TffiMIJi number generated from the tempo generating section 8, the pitch data of the audio signal of a relatively stable pitch is read. 0PU1 quickly reads this relatively stable pitch data multiple times and converts the multiple pitch data into multiple scale data. Then, the majority logic of these multiple data is
, the most frequently occurring scale data is stored in the RAM 4 as a single scale data. By doing this, it is possible to achieve a relatively high detection rate even if the pitch of the vocalization is slightly unstable. At this time, the audio pitch extractor 5 outputs new pitch data for each pitch of the input audio signal.

That is, the audio pitch extraction section extracts audio pitch data in real time.

0PU1 sequentially detects and stores friend scale data in RAM4-\ according to the TFiMP signal. The above is the operation in the composition mode or recording mode.

Furthermore, at the same time as storing it in the RAM 4, the note display section 5
It is also possible to transfer scale data to display notes in real time.

In the modification mode, the scale data stored in the RAM 4 is read out and modified. In this case, scale data for eight notes is displayed on the note display section 5, and corrections are made while checking this.

In this correction mode, if the scale is displayed from the note display section 6Vc and at the same time the scale data is also transferred to the musical sound generation section to express two systems of musical tones and display, corrections will become easier. Dew.

In playback mode, the scale data stored in RAM4 is
In synchronization with the T Fi TA P signal from the tempo generating section 8, the musical note display section 5 and the tone generating section 6 are simultaneously reproduced. Therefore, in the composition mode, the scale of a song input slowly can be sped up when played back. That is, ap.

1 is 1v in synchronization with the variable T E IJ P signal.
This is because it is made by J.

This completes the explanation of the system configuration of the present invention.Furthermore, a more detailed explanation will be given with reference to Figure 2 and subsequent figures.

First, in order to explain in order, a detailed explanation of the voice pitch extracting section 3 will be given.

FIG. 3 is a detailed diagram of the speech pitch extraction section 3, sof'
i amplifier circuit, 31tri voltage follower, 3
211 inversion amplifier IM circuit (amplification factor = 1x), 65 and 54f
-J peak hold circuit, 35 is a set-reset clip-flop (hereinafter abbreviated as SRF//'F), 56f
37 is a delay circuit, 38 is an oscillation circuit that generates a clock for IMH2, 39 is a r1 counter, 40 is a latch circuit, 41 is an electronic switch that is opened and closed by 8 manual forces (as shown), 42 is an AND circuit, 43 is a microphone (hereinafter abbreviated as M-C).

MIO43 is connected to the amplifier circuit 300Å to the power end, :1. ! / width circuit 30 output to voltage follower 310 input terminal, voltage follower 31 output cover, peak hold circuit 3
5 input end and inversion increase 1! Each is connected to the prefectural circuit 320 input terminal. Is the output of the inverting amplifier circuit 32 a peak hold circuit? The output of the peak hold circuit 33 goes to the input end of S Rr/F S 5 set (indicated by S), and the output of the peak hold circuit J path 34 goes to the input end of 8RF/F55.
to the reset (denoted R) input terminal of 8RF/F55.

To the input end of the output differential circuit 360, the output φ of the differential circuit 36
(denoted by L) are respectively connected to the φλ input terminals of the input latch circuit 40 of the delay circuit s7. The output of the delay circuit 37 (
φR) is latched to the reset input terminal of the counter 59, the output of the oscillation circuit 58 (indicated by I MHz) is latched to the clock input terminal 1\ of the counter 39, and the 41 output of the counter 39 is latched to the input terminal of the latch circuit 4o. The output of the circuit 4o is connected to an electronic switch 41, and the output of the electronic switch 41 is connected to a data bus (DATABUD). The AND circuit pg42-\ receives A:oqfn and RD(i), and its output is connected to the S terminal of the electronic switch 41.

Here, the electronic switch 41 is composed of a general (3-state buffer;
Hell\fx C) M Output t, 1c, Impedance and howl.

Next, the operation of the ondo j pitch 11 output section will be explained with reference to FIG. 713 and FIG. The I″iμ diagram is a timing diagram of each part in FIG. 3.

First, the audio signal input from the MIO 43 is transmitted to the amplifier circuit 5.
0 and the voltage follower 31, the waveform shown by h in FIG. 4 is obtained. Further, the output of the inverting amplifier circuit 52 with an amplification factor of 1 is the inverse of waveform A as shown in FIG. 4B. Waveforms A and B are amplified audio waveforms, and are inverted symmetrical waves. This waveform A is connected to the input terminal of the peak hold circuit 550, and the waveform B is connected to the input terminal of the peak hold circuit b4.
detects and holds all peak values of each waveform. However, this peak hold circuit 65 and 3414. The capacitor C shown in the figure has a peak (fX is held like an analog, but due to the extended RK, it is slightly discharged -C
There is. In other words, after detecting the peak of the input waveform, C and H
According to the time constant of , at a certain position of the 1' point (as shown in the figure), a broken curve, which is not shown on the waveforms B and B in FIG. 4, is formed. Then, the outputs of the peak hold circuits 35 and 54 are respectively
(shown by C and D in Figure 1) is at level 1 when producing the peak of shaping A or when detecting the peak of waveform B. In other words, the peak hold circuit 33 detects the positive peak of the audio waveform, Peak hold circuit 54 Iri Detects the negative peak of the audio waveform 1. Generally, the audio waveform is A in FIG.
Although the waveform is irregular as shown in FIG. 3, the peak hold circuit shown in FIG. 3 can efficiently detect the hourly pitch. Furthermore, the same wave number of audio is generally 70.
Since it is about 91 JOHrr from H2, it is preferable to set the time of C and R by 10 ms or more.

仄【゛This is the output of the peak hold circuit 36 (indicated by C)
is set to all S RF/F 35, and the output (J) of the peak hold circuit 54) is S RF
/F 55 operates to reset.

The timing is shown by Q/-]) and self in FIG.

The E waveform is of SRF/F35. This is the output. That is,
8 RF/F 35 is set at the peak C of the audio waveform and reset at the negative peak. Soshi-C1s n F
/F s The Q output of s is equal to the period of the voice pitch, as shown in the 41st line.

Next, the output of the differentiating circuit 36 and the output of the d-wind circuit are denoted by φL and φR, respectively, and their timing is shown in FIG.
Indicated by L and φR. The bend, φL, or φR occurs only at the positive peak of the audio waveform, and its generation period is approximately equal to the audio pitch.

Here, the φL counter is operated by the clock input of the latch circuit 40. This counter 59Vi is preferably in a binary block format of +s to 16 bits. and,
Counter 59 <-x 'Ei voice pinch % ll Reset from the generated φR signal 5, otherwise I MB
I missed the second clock. Also, launch circuit 4
0 latches the elbow value of the φL1 word counter 4o. Since the φL times signal and the φR times signal are generated slightly before, the I signal immediately before the counter 40 is hit.
'+i: i: held by the latch circuit 4u.

That is, the value counted at timing Ti (shown) in FIG. 4 is latched and held in the region of timing r 2 (1, !, 1 shown). Like C, latch circuit 4
The content held in 0 is that new data is detected in real time according to the audio pitch.And since the clock of the counter 39 ticks at I MB2, for example, the count value of the counter 59 is If it is 2000J, the period of the voice pitch is 2ms, and the fundamental frequency of the voice is 11500H.
Tilt by 2. Next, the contents held in the latch circuit 40 are transferred to the data bus at the secondary time when the AJ')\ signal and the RD double signal are valid, according to an instruction from apυ. In other words, audio pitch data required by the OPU is supplied onto the data bus in real time.

Continued on next page Note that the count value of the counter 59 indicates which pitch name the pitch of the voice input corresponds to.
A list of note names is shown in the table below.

In this table, the one item "acceptable voice pitch period" means the voice input pitch period that should be allowed compared to the musical absolute pitch, and it applies even if the pitch produced by a person is slightly off. This means that it is recognized by replacing it with the name of a note near the pitch. Further, the allowable count value represents the measured value of the counter 39.

As explained above, the audio pinch extraction section can efficiently extract audio pitch data with high accuracy and a simple circuit configuration.

Next, the RAM 4 will be described. The element called RAM is already well known, and its connection relationship with the CPU is also widely known. Therefore, detailed pregnancy explanation will be omitted here.

Next, the note display section 5 will be explained in detail.

The explanation will be made according to FIGS. 5, 21, 6, and 7.

5 is a detailed view of the note display section, FIG. 2 is an external view of the note display section, FIG. 6 is a detailed view of the inside of the block in FIG. 5, and FIG. 7 is a detailed view of the note display section in FIG. Part of the timing First, referring to FIG. 5, 50 is a group of AND circuits, 51a to 51h are 3-step launch circuits consisting of a launch circuit and a 5-state buffer, and 52 is a decoder. 55 is an X-driver (, 54 is a Y driver, 55 is a timing generator, and 56 is an LEiD display body.

Generally, as a display element, L]! +D or liquid crystal is conceivable, but in this embodiment, an LED display is shown as an example.

A detailed explanation of the case of LKD'tle will be given below.

AND circuit group 50 is AD2~? Signal (as shown) t-
This is a gate element that opens and closes with the WR multiplication signal (shown in the figure). The outputs φ2 to φ9 (shown) of the AND circuit group 50 are connected to the φ outputs of the three-step latch circuits 51a to 51h, respectively. In addition, the 5-stage trunk circuit 51a~
Data bus (DATA Bt) is connected to the IN input terminal of 51h.
B) are connected to each other, and their OUT terminals are commonly connected to the input terminal of the decoder 52. here,
Since the data bus is 8 bits, the input terminal of decoder 520 is also 8 pins.

φA to φH, which are the outputs of the timing generator 55'
(shown) are connected to the input terminal of the X driver 54 and to the eight input terminals of each of the five-step latch circuits 51a to 51h.

The output of the decoder 52 to the input terminal of the tix driver 56,
The outputs of the driver 55 and the X driver 54 are each connected to an LFiD display 56. Here, the LgD display body 56 has an external view as shown in FIG.
A group of LEDs is mounted on the 5-line staff. And that LED
The group consists of 8 blocks, each block is
The outputs of the driver 54 are connected to control the outputs of the driver 54.

That is, the LFi group shown in FIG.
It is arranged to be driven by a cylindrical matrix. Then, the output timing of the timing generator 55 (
φA to φH) are shift pulses as shown in the timing diagram of FIG. That is, the X driver 54
Eight blocks of the LED group in FIG. 2 are sequentially driven in response to the pulses shown in the figure.

Next, we will explain how data is transferred from the OPU to the note display section.

First, the CPU instructs which note to display in which of the eight blocks in the note display section, so A D 2-
One of the 19 signals (shown) is selected and a WR signal is generated at the same time. For example, if you want to display a specific note on the leftmost note LPtD pronk,
2 signals and put predetermined scale data on the data bus. Among the outputs of the AND circuit group 50, the φ2 signal becomes active, and the 3-step trunk circuit 51a takes in the scale data on the data bus. Here, the five-step launch circuit 51a has a configuration as shown in FIG. 6, and reads data into the φ terminal and outputs it through the sPJ terminal. Therefore, the scale data is transferred to the decoder 52 using the φA multiplied signal shown in FIG. 7 by the three-step latch circuit 51aH. The decoder 52 converts the scale data into a predetermined 1. Convert to BD lighting signal and use X driver 5
Drive 5. In this case, one block of TJ E D
Since the display consists of 16 pieces, the output of the decoder 52 is 16 pieces.

That is, the LFiD display body 56 may be driven only by the output signals of the timing generator 55 and may be asynchronous with the data transfer from the CPU. With the above configuration, the CPU can transfer arbitrary scale data to an arbitrary display section at an arbitrary timing. Therefore, the negative phase of CPU processing can be reduced, and the configuration of the program can be simplified.

Next, the musical tone generating section 6 will be explained in detail.

FIG. 8 is a detailed diagram of the musical tone generator. 8o is a musical tone selection switch group, vibrato and the stain effect switches that control the aiFi musical waveform, 821 AND circuit,
83 is a musical tone generation circuit, 84 is a filter, 85 is an amplifier circuit, and 86 is a speaker.

The data bus is connected to the DIN input terminal of the musical tone generation circuit,
The AND circuit 82 receives the AD10 signal and the WR signal, and its output is connected to the WR input terminal of the musical tone generating circuit 85.

The musical tone selection switch group 80 and the effect switch 81 are each connected to a musical tone generation circuit 85.

The output of the musical tone generation circuit 85 (indicated by OUT) tj is connected to the input terminal of the filter 84, the output of the filter 84 is connected to the input terminal of the amplifier circuit 85, and the output of the amplifier circuit 85 is connected to the speaker 86.

When the CPU generates musical tones, it selects the AD10 signal,
Next, put the specified scale data on the data bus, and at the same time
Generate R signal. The musical tone generation circuit 83 reads the scale data applied to the DXN terminal using the WR signal, and
Recognize the scale data and synthesize musical sounds. As the musical tone generating circuit, a musical tone generating LSI currently available on the market is sufficient, and its peripheral circuits are also known as Kameko circuits for electronic musical instruments. In this embodiment, musical tone generators I and 8I are positioned as custom LB engineering and are applied. Naturally, there must be a CPU data reception (Pf function).

As explained above, the CPU can easily reproduce beautiful musical tones by transferring to the address of the predetermined scale code 1AD10.

Next, the switch section 7 will be explained in detail.

FIG. 9 is a detailed diagram of the switch section. Reference numerals 90a to 90c are five-speed bus sofas similar to those shown in FIG. 10, which are controlled by eight input terminals. 91 is a mode switch for setting each mode of composition, modification, and playback, 92 is a start switch, and 95 is]! iND switch, 94 to 97 are cursor movement switches in the modification mode, 98 is a rotary digital switch for correction or octave shift during playback, and 99 is a rotary digital switch for 1-bit correction or key correction during playback. , 10
0 and 101 are AND circuits.

A mode switch 91, a start switch 92, and an end switch 93 are respectively connected to the input terminals of a 5-stage amplifier 90a, and the cursor moves 1 inch 94 to 9.
7 are each connected to an input terminal of a 3-state buffer 90b. Further, the respective outputs of rotary digital switches 98 and 99 are connected to the input terminal of 3-state buffer 90c. 3 state banhua 90a, 90b and 90
The respective outputs of C are commonly connected to a data bus.

The RD multiplied signal is connected to one input terminal of the AND circuits 100 and 101, the AD11 signal is connected to the other input terminal of the AND circuit 100, and the AD12 signal is connected to the other input terminal of the AND circuit 101. are connected to each other. The output of the AND circuit 100 is a 5-state buffer 90a and 90b.
The output of the AND circuit 101 is 5 to each of the 8 input terminals.
Each is connected to the S input terminal of the state buffer 90c.

Next, the operation will be explained.

As an apu, when you want to know the status of the switch, first
Dl 1 signal and RD signal? By activating it, the status of each switch from mode switch 91 to cursor movement switch 97 is output on the data bus. a p
U td Read and store the data. Also, A
By activating all the D and RD signals, it is possible to know the switch states of the rotary digital switches 98 and 99.

Next, follow the operating instructions and explain the function of each switch.
First, the mode switch 91 is set to composition mode, and the start switch 92t-, ty is pressed.

In this state, does the QPU input audio according to the TBMP signal? To detect. Specifically, the pinch data tj412. input, convert it to scale data and store it in RAM4.
memorize them in order. Next, when the voice input is completed, the end switch 95 is turned on to end the composition mode.

Next, the mode switch 91f is set to the correction state, and the start switch 92 is turned on. The CPU detects this state and reproduces the musical scale data from the beginning to the eighth in the RAM 4 to the note display section 5 and the musical tone generation section 6. In this case, the switch data of the rotary digital switch 98 for octave shift and the rotary digital switch 99 for key adjustment are used as reference. For example, if both rotary digital switches 98 and 99 are in the shift zero position, the scale data in RAM 4 will be reproduced as is. In addition, the rotary digital switch 98 for octave is
If it is located at the octave amplifier position, the scale data in RAMA is shifted by one octave and then played back. At this time, only the scale data to be transferred to the note display section 5 and musical tone generation section 6 is processed, leaving the scale data in the RAM as is.

Further, the rotary digital switch 99 for key correction has the function of, for example, converting the G major key to F minor major key for reproduction. Specifically, " * A6 *
If you play a melody like B4 + D4 # one step up, Cp, As #・am 1”
4 and so on.

In the correction mode, cursor movement switches 94 to 9
7, it is possible to arbitrarily modify the rt mark at any position. In this case, the scale data itself in the RAM 4 is modified by moving the cursor.

Further, in the correction mode, when the start switch 92 is turned on, the first 81st floor is reproduced. That is, the operation is to reproduce and correct each 8-tone scale. Therefore, when the correction for eight notes is completed, the start switch 92 can be turned on and the correction for the next eight notes can be started.

Next, the reproduction mode will be explained. In reproduction, the operation is very similar to that described in the correction mode. First, the mode switch 91 is set to the reproduction mode, and the start switch 92 is turned on.

The CPU sequentially reproduces the scale data in the RAM 4 to the whole note display section 5 and the musical tone generation section 6 in synchronization with the TKMP signal. At this time, the rotary digital switch 98 for octave shift
Needless to say, the playback is performed according to the switch state of the key adjustment rotary digital switch 99.

By implementing the switch unit as described above, the CPU can easily read the switch data, and the CPU can easily read the switch data.
It is possible at any time. However, since the switches may be operated quickly, for example
It is necessary to consider things like installing a switch at 00m5.

In addition, it has powerful correction functions and various playback functions,
Once you have memorized all the scale data, you can modify it as many times as you like.
Moreover, it can be played in any octave and in any key.

Next, the tempo generator 8 will be explained in detail.

FIG. 11 is a detailed diagram of the tempo generator.

110 is a variable oscillation circuit that can be varied by resistor Rx; 11
1 is a counter, 112 and 113 are differentiating circuits, 114 is a centric flip-flop (hereinafter abbreviated as SRF/F), 115 and 117 are AND circuits, 116 is an OR circuit, 119 is a delay circuit, and 1201d is a visual display means. ,1
21 is an auditory indicator 19, and 122 is a speaker on inch.

The output of the variable oscillation circuit 110 is connected to the clock input terminal of the counter 111, the output of the counter 111 is connected to the input terminal of the differentiating circuit 112, and the output of the differentiating circuit 112 (indicated by Tx) is connected to one input terminal of the OR circuit 116. be done.

The song mode signal and the start signal (shown) are supplied from the switch section 7 (No. M and are connected to the input terminals of the AND circuit 1150, respectively. (denoted by R),
Cent input of φL multiplied signal SRF/F114 (indicated by S)
connected to each. Here, the φL multiplied signal is a signal supplied from the audio pinch extraction section 5 described above, and is generated only when audio input is added, in synchronization with the pitch of the audio. Therefore, in the case of silence, the φL times signal is not generated.

The Q output of the S RF/F 114 is connected to the input terminal of the differentiating circuit 115 and one input terminal of the AND circuit 117, and the output of the differentiating circuit 115 (indicated by BG'N) is connected to the other one of the OR circuit 116. It is connected to the input terminal, the recent input terminal of the counter 111, and the recent terminal of the differentiating circuit 112, respectively. The output of the OR circuit 116 is connected to the other input terminal of the AND circuit 117, one input terminal of the AND circuit 118, and the input terminal of the visual display means 1200, respectively.

Also, uIKH is input to the other input terminal of the AND circuit 118.
z signal is connected. The output of the AND circuit 117 (T
Y) is connected to the input terminal of the delay circuit 119, and is connected as the output FiTg-MP signal of the delay circuit 119 to the INT input terminal of QPU1 in FIG.

The output of the AND circuit 118 is the speaker on switch 122
The visual display means 120 is connected to the input terminal of the auditory display means 121 through the LKD, and the visual display means 120 is composed of a circuit for driving LKD and LKD, and produces σ(j) as a tempo display. The auditory display means 121 is composed of a speaker and a speaker drive circuit, and generates a tempo sound using an I KHz signal.

Next, the operation will be explained with reference to the timing diagram shown in FIG. FIG. 12 is a timing diagram of each part in the 11th section 1. The tempo generator of this embodiment implements a tempo synchronization system in which the tempo is synchronized with the audio input at the beginning of the song.
Trying to.

First, I set it to composition mode, turned on the start switch sound, and started singing the song, but when I switched to composition mode and turned on the start switch? If you turn it on, the tab in Figure 12 will appear.
The Q signal becomes level ＼ at the timing of . t in Figure 12
In the timing region a, the Q signal is at level 1, and the Tx signal becomes the TY signal, and the TEMP signal is generated. However, as a CPU, even in the 1000 song mode, as long as the start switch is not input, the Q signal is at level 1.・No transcription is performed using the TEMP signal. That is, no transcription is performed in the ta timing region. Then, when the start switch is turned on, the Q signal becomes level page, so
In the timing region of tb, no TK-MP double signal is generated,
There is no transcription. Even if you start in composition mode, the music is not transcribed, which saves RAM4 memory space.

Next, if singing starts at the timing of tbc, the φL times signal starts to be input here, and SRF/F114 is sent. At the same time, the differentiating circuit 1
13 operates and a BGM signal is generated. Since this BGN (what number tma counter 111 and the differentiating circuit 112i17 cents), the Tx times signal is generated at a predetermined period after this BGN 4M signal is generated.And in the region of tc, the 13ON signal and the Tx times signal are generated. T ′AM P (i
Generation of number i is performed.

Furthermore, the Tz multiplied signal [is generated at the timing shown in FIG. 12 only when the speaker switch 122 is on. 1- In other words, since these tempo confirmation means occur in any situation, it becomes easy to determine the tempo of the song.

The counter 11174 receives the clock from the variable oscillation circuit 110 and divides the frequency to generate a tempo cycle determined by the resistor Rx. Therefore, the Tx signal is a normal Te/bo signal.

In addition, the TliiMP signal is created by delaying the TZ signal, but this is because the beginning of the voice is a relatively unstable voice waveform, and if the 1f voice pitch is extracted at this initial timing, the pinch extraction efficiency decreases).

Since we want to extract a pinch near the center of timing 1β in FIG. 12, the interrupt (INT, ie, TKMP reconnaissance) to the CPU is slightly delayed.

If you use the tempo generator as explained above, you don't have to worry about the beginning of the song, you can also improve RAM storage efficiency, and when you start in playback mode, you can cut out the silent section and start the song. If you play it faithfully from the beginning
It is J-Noh.

The present invention has been explained in its entirety above, and by implementing the present invention, the following effects can be expected.

1) Relatively stable pitches of speech can be extracted.

2) - Since a recorded song can be played back with octave shift and key correction, a wide range of melodies can be played back.

5) The recorded melody (scale data) 1 can be modified by a simple switch operation.

Since the audio pinch extraction section simultaneously detects the positive and negative peaks of the audio waveform, the pitch detection efficiency is high and an extremely simple circuit configuration is required.

5) There is no need to match the tempo at the beginning of the song,
Easy to sing and efficient use of RAM.

6) From the user's point of view, it is easy to learn absolute pitches.

7) Since the melody composed by the user can be played back with multiple tones, it is possible to supply products with high commercial value.

8) Since the audio pinch extraction unit is a relatively versatile extraction unit, it is possible to easily transcribe not only audio but also musical instrument performances.

9) Since data is transferred through the CPU path line, 110 devices such as a printer or CRT can be easily added using this path line.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the present invention, and FIG. 2 is a block diagram of the LIIC.
D is an external view of the note display section, FIG. 6 is a detailed diagram of the audio pitch extraction section, FIG. 4 is a timing diagram of FIG. 3, and FIG. 5 is a detailed diagram of the note display section. FIG. 6 is a detailed diagram of some blocks in FIG. 5, FIG. 7 is a timing diagram of FIG. 5, FIG. The figure is a detailed diagram of the switch section, and the first
0 is a detailed diagram of some blocks in FIG. 9, FIG. 11 is a detailed diagram of a tempo generation section, and FIG. 12 is a timing diagram of FIG. 11. 1...QPU 2...Address decoder 6...Audio pinch extraction section 4...RAM 5...Musical note display section 6...Music sound generation section 7...Switch section 8...Tempo generation Part 30...Amplification circuit 61...Voltage follower 3
2...Inverting amplifier circuit 55.54...Peak bold circuit 35...Centricent Flynn 7'Frog 36...
・Differential circuit 57...Delay circuit 58...Oscillation circuit
69... Counter 4u... Launch circuit 41...
Electronic switch 42...AND circuit 43..., Micros 1-oh 150...AND circuit group 51a-51h...5-step latch circuit 52...
Decoder 53...X driver 54...Y driver 55...Timing generator 80...Musical tone selection switch 81...EFF switch 82...AND circuit 83...Musical tone generation circuit 8
4...Filter 85...Amplification circuit 86...Speakers 90a to 90c...5 state buffer 91...Mode switch 92...Start switch 93...
End switches 94 to 97...Cursor movement switch 9th...Rotary digital switch for octave shift 99...Rotary digital switch for key adjustment 100.
101...AND circuit 110...Variable oscillation circuit 111...Counter 1
12.113...Differential circuit 114...Centreset flingfronf-11
5,117,118...AND circuit 116...OR circuit 119...Delay circuit 120...Visual display means 121...Audible display means 122...Speaker on switch and above Applicant Seiko Representative of Denshi Kogyo Co., Ltd. Patent Attorney Mogami

Claims (2)

[Claims] (1) At least a pitch extraction means for extracting the basic pitch of the waveform of a voice or musical score, a conversion device for converting the pitch information obtained from the pitch extraction means into a musical scale, and a method of outputting the conversion device is memorized. It consists of a memory circuit, a reproduction means for visually or audibly displaying the contents stored in the memory circuit, and a tempo generation means, and the tempo generation means generates a tempo signal in synchronization with the start time of audio input. A voice synchronized tempo generation mechanism is used, and the tempo 18
The pitch extracting means is configured to operate according to the occurrence of the signal.The tempo mechanism follows at the beginning of one song. (kli): I-7
A voice recognition type pitch notation device that makes +/”-/- 'r!? (h). (2) The voice recognition pitch notation device according to claim 1, characterized in that in the embedded mode, the ``I'' and ``I48'' functions are prohibited until a voice input is applied.