JPS6089979A - Semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a semiconductor device, and particularly to a compound semiconductor device which has excellent uniformity and reproducibility of gate threshold voltage of a field effect transistor element, and has high productivity.

(b) Background of the technology In order to improve the operating speed of semiconductor devices and reduce power consumption, many transistors use compound semiconductors such as gallium arsenide (GaAS), which has a much higher carrier mobility than silicon (Si). Proposed. Field-effect transistors (hereinafter abbreviated as FETs) are currently the mainstream transistors that use compound semiconductors, as their manufacturing process is simpler than bipolar transistors.
is being done a lot.

In semiconductor devices of conventional structure such as 8-dish or GaAS, carriers move within the semiconductor space where impurity ions are present. During this movement, the gear is subject to scattering by lattice vibrations and impurity ions, but if the temperature is lowered to reduce the probability of scattering due to lattice vibrations, the probability of scattering by impurity ions increases.
Carrier mobility is thereby limited. In order to eliminate this impurity scattering effect, the region where impurities are added and the region where carriers move are spatially separated by a heterojunction interface, and the heterojunction electric field increases the mobility of carriers, especially at low temperatures. Even higher speeds have been realized by effect transistors (hereinafter abbreviated as heterojunction FETs).

(C) Prior art and problems An example of the conventional structure of a heterojunction FET is shown in FIG.
s layer 2 and n-type aluminum gallium arsenide (AtGaA), which has a smaller electron affinity and contains donor impurities.
s) A layer 3 and an n-type GaAS layer 4 are provided, and an n-type GaAS layer 4 is provided.
The aAS layer 4 and, if necessary, a part of the n-type AtGaAS layer 3 are selectively removed to provide a gate electrode 7 in contact with the n-type AtGaAS layer 3, and a source electrode on the n-type GaAS layer 4. 8 and a drain electrode 9 are provided.
Electrons transferred from the type AtGaAS layer 3 (referred to as the child supply layer) to the non-dorfed ΦGaAS layer 3 (referred to as the channel layer) are thus generated near the heterojunction interface between both layers.
The dimensional electron gas 6 functions as a channel, and by controlling its electron concentration by the voltage applied to the gate electrode 7, the source electrode 8. -! The impedance between the NiDrain electrode 9 and the NiDrain electrode 9 is controlled.

The basic characteristics such as the saturation value Idss of the north-drain current and the gate dark voltage yth of the Peter junction type redundant T having the structure as explained above are as follows.
It can be controlled by the thickness and impurity concentration of the semiconductor layer interposed between it and the channel layer 2. Conventionally, as a means for implementing this control, a recess structure in which the thickness of the n-type A4GaAs layer 3 is selectively etched is often used.
There is.

As a means of forming the recessed structure mentioned earlier.

Conventionally, wet etching has been the most commonly used method.

In other words, when a resist mask is set using the lithography method, the amount of etching is controlled by concentrating maximum attention on the composition, temperature, and surface condition of the etching solution, and the source is taken out of the etching bath. The etching end point is determined by measuring the current between the drain electrodes many times.

However, forming a wet etching process using such a wet etching method is not only complicated, but also involves large variations in the amount of etching, resulting in problems in reproducibility. Furthermore, the wet etching method usually has poor selectivity in the etching direction, and side etching progresses significantly, reducing pattern accuracy.

As an etching method suitable for improving pattern precision and rationalizing the process, conversion to dry etching is being made in all semiconductor manufacturing processes. In the dry etching method, the atmosphere inside the etching chamber has already been monitored by means such as gas analysis, emission spectrometry, or mass spectrometry.
This method is not suitable for controlling the thickness of a single semiconductor layer, such as selecting the etching end position of a GaAs layer. Therefore, even in the dry etching method, it is necessary to measure the current between the source and the drain -4=, but if the sample to be processed is repeatedly taken out of the etching chamber for this purpose, the loss of working time is enormous.

Furthermore, in integrated circuit devices that use the heterojunction FET described above as an element, in many cases, elements in the enforcement mode and depletion mode are used together, and even in the same mode, the gate threshold voltage yth is different. Different elements may be required. In this way, when heterojunction FETs with different gate threshold voltages yth are mixed on the same semiconductor substrate, the complexity of the conventional manufacturing method described above becomes even more pronounced, making it extremely difficult to implement it industrially. be.

fd) Purpose of the Invention The present invention copes with the above-described situation and makes it possible to realize a semiconductor device including field effect transistor elements in which gate threshold voltages and the like are set to be different from each other with high precision and good reproducibility. The purpose is to provide a structure that

(e) Structure of the Invention The object of the present invention is to alternately stack two types of compound semiconductor layers containing at least one element that is not common to each other on a semiconductor layer forming a gate channel of a field effect transistor. This is achieved by a semiconductor device in which a gate electrode is provided on a surface from which a semiconductor stacked structure has been selectively removed.

Further, in the semiconductor device, two types of compound semiconductor layers containing at least one element that is not common to each other are alternately laminated on the semiconductor layer forming the gate channel of the field effect tunnel, and the semiconductor laminated structure is etched by a dry etching method. selectively etching and detecting the non-common elements in the gas generated by the etching.
It can be manufactured by a manufacturing method in which self-etching is terminated and a gate electrode is disposed on the etched surface. In particular, if each of the two types of compound semiconductor layers is thinned within a required tolerance, the termination of the etching can be extremely easily controlled by the number of times the non-common elements appear in the gas.

(f+ Embodiments of the Invention The present invention will be specifically described below using embodiments with reference to the drawings.

FIGS. 2A to 2C are step-by-step cross-sectional views showing states in the main manufacturing steps of the embodiment of the present invention relating to the heterojunction type I''ET.

Refer to FIG. 2(a) On a semi-insulating GaAS substrate 11, for example, a non-doped QaAs layer 12 is grown to a total thickness of about 300 (nm) by, for example, a molecular beam epitaxial growth method, and silicon (SL), for example, is added as a donor impurity to 2×10”. (,”' l
An n-type At0.3Ga0.7AS layer 13 is grown to a thickness of, for example, about 30 (nm).N-type QaA layer 13 containing, for example, Sl to a thickness of about 2×10 (tan) is grown.
The s-layer 14 and the n-type AzO, 3GaO, 7As layer 15 are alternately stacked, and the thickness of each layer is set to 1 (nm), for example.
grow to a certain extent. Note that in this example, n-type GaA
10 layers of S layer 14, n layer tO3GaO1, s layer 15
There are nine layers.

The n-type At0.3GaO,7As layer 13 is an electron supply layer, and its impurity concentration and thickness are such that when a gate electrode is provided on this surface, the intended upper limit of the gate threshold voltage can be obtained. It is most effective to select

In addition, the n-type GaAS layer 14 and the n-type At0.3Ga0.7
The impurity concentration with the As layer 15, the thickness of each layer, and the lamination thickness are selected in relation to the intended value range of the gate threshold voltage and the width of allowable variation.The thickness of each layer ranges from a monoatomic layer to a monoatomic layer. For example, up to several tens (nm).

The impurity concentration ranges from non-doped to, for example, 2xlO” (crn
−”) can be selected.

Referring to FIGS. 2(b) and 3, a recess is formed in the gate region. In this embodiment, etching is performed by sputtering with an argon (Ar) ion beam, but the acceleration voltage of the ion beam is set at about 100 (V) l to prevent damage to the semiconductor layer. The gas generated by this etching is analyzed, for example, by SIMS (secondary ion mass spectrometry) to monitor temporal changes in the amount of aluminum (At) contained therein. The amount of kl changes as shown in FIG. 3, and thereby the etching depth can be determined precisely. For example, in the example shown in Fig. 3, the etching depth is 17 (
nm). Since the etching depth, and thus the thickness of the remaining semiconductor layer, can be accurately grasped in this way, etching can be easily stopped at the optimum position.

Note that as an etching method, it is also possible to apply a two-selective chemical dry etching method, and as a monitoring method, it is also possible to apply Auger electron spectroscopy.

FIG. 2(e) Reference source electrode 18. Drain electrode 19 and gate electrode 17
can each be formed by conventional techniques. The source electrode 18 and the drain electrode 19 may also be formed after the recess is formed as in this embodiment.

In this example using a wafer with a diameter of about 5 mm, the gate threshold voltage Vth=0. A standard deviation σylh=5 (mV) with respect to the standard value of IV is obtained. This value is greatly improved compared to the standard deviation σV t h =20 to 30 (II) VI in the conventional example under the same conditions.

The above explanation is based on AtGaAs/GaAs heterozygous F.
Although the target is ET, it can be similarly applied to semiconductor devices with conventional structures that do not spatially separate impurities, and can also be applied to semiconductor devices using different compound semiconductor materials. The present invention can be applied by detecting arsenic (As) in nGaAs/InP) based semiconductor devices.

(g) As described in detail, according to the present invention, a compound semiconductor device including a field effect transistor element can be provided with excellent reproducibility and productivity with little variation in characteristics such as gate threshold voltage. This makes it possible to achieve the effect of promoting ultra-high-speed, large-scale information processing.

[Brief Description of the Drawings] Fig. 1 is a sectional view showing a conventional example of a heterojunction FET, Fig. 2(a) to fcl are sectional views in order of steps of an embodiment of the present invention, and Fig. 3 is a dry etching It is a figure which shows the example of the monitor inside. In the figure, 11 is a semi-insulating GaAS substrate, 12 is a non-doped GaAs layer, 13 is an n-type AtGaAs layer, 1
4 is an n-type QaAs layer, 15 is an n-type A tQ a A 8
Layer 16 is a two-dimensional electron gas, 17 is a gate electrode, 18 is a source electrode, and 19 is a drain electrode. Figure 1 Ryo? Figure 2 σ) −ri

Claims (2)

[Claims] (1) Two types of compound semiconductor layers containing at least one element that is not common to each other are alternately stacked on a semiconductor layer forming a gate channel of a field effect transistor, and the semiconductor stack structure is selectively removed. A semiconductor device characterized in that a gate electrode is provided on a surface. (2) a semiconductor layer forming the gate channel; It is composed of a first semiconductor layer and a second semiconductor layer that has a smaller electron affinity than the first semiconductor layer, forms a heterojunction with the first semiconductor layer, and contains donor impurities, and Electrons transitioning from the second semiconductor layer cause the first
2 is formed near the heterojunction interface of the semiconductor layer of
2. The semiconductor device according to claim 1, wherein the dimensional electron gas functions as a gate channel.