JPS6083370A - Polycrystalline silicon thin film transistor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a field effect transistor using a semiconductor thin film containing silicon crystal grains in an active region, particularly an 0N-OFF transistor.
This invention relates to high-performance thin film transistors with high ratios.

[Background of the invention]

Conventional polycrystalline silicon thin film transistors have the advantage of having higher field effect mobility and therefore faster operation than transistors using amorphous silicon thin films, but the gate electrode is located on the thin film semiconductor between the source and drain electrodes. In the case of a structure in which only one TPT is formed in the TPT, the leakage current at the interface between the thin film semiconductor and the insulating substrate is large in the case of OFF operation, and the OFF resistance is small compared to a TPT using amorphous silicon. Furthermore, due to the gaps between the gate and the source and between the gate and the drain, the ON resistance is large, and therefore the ON/OFF ratio is low.

[Purpose of the invention]

The purpose of the present invention is to reduce the leakage current at 012
Increase the Fp resistance and reduce the ON resistance to 0N
An object of the present invention is to provide a thin film transistor with a large -OFF' ratio and good operating characteristics.

□ [Summary of the invention] By providing two gate electrodes on the top and bottom of a thin film semiconductor containing silicon crystal grains with a diameter of more than 10 m, which has a higher carrier mobility than amorphous silicon, leakage current when turned off can be reduced. Since it flows only through the center of the semiconductor film, the large leakage current generated near the interface can be completely suppressed, and the lower gate electrode extends to the gap between the upper gate and source, □, and the gap between the upper gate and drain. Therefore, during ON operation, the resistance of the above region also decreases, and the ON resistance of the entire unit can be reduced.
The N-OFF ratio can be increased.

[Embodiments of the invention] Hereinafter, an embodiment fc of the present invention will be explained with reference to FIG.

For example, a C film with a thickness of 0.1 μm is vacuum deposited on an insulating substrate 1 such as quartz or Corning 7059 glass, and CRT is processed by a photo-etching process to form a lower gate electrode 2. Next, the well-known CVD process is performed. Law (Chemica)
5iOz insulating film 3k 0.3~0.5 tt
m is formed, and then CVD method or MBD method (Molec
ular f3eam Deposit ion)
A silicon film 4 containing polycrystals is formed to a thickness of 0.6 to 1 μm. At this time, doping with impurities is not performed. A 5I02 film is again formed to a thickness of 0.6 to 1.0 .mu.m, and holes are made to form a source region and a drain region. To form the source and drain regions, B
To form a + layer, use p1 ions or As+ ions k, p”
To form a layer, B+ or B F 2+ ions are applied at a dose and force of, for example, 1016 cm-2 at room temperature. speed voltage 1
It is implanted at 00 KV and then heat treated at about 800 to 1100 tr. In addition, when a glass substrate of gold having a low softening point is used, all methods such as heat treatment at a width of about 500 to 600 C are used. After this heat treatment, the 8102 film used as a mask for ion implantation is removed. After that, 0.6% of 81025 was used as an insulating film for the upper gate.
~1 μm is formed and holes for electrode contact are made. kl all over
After depositing gold on the electrode, At
After complete processing, a source electrode 6, a drain electrode 7, and an upper gate electrode 8 are formed. At this time, the upper gate electrode 8 is
As shown in FIG. 2, it is formed so as to be in contact with the lower gate electrode. Note that FIG. 2 is a sectional view taken along line A=A in FIG. 1. Upper gate length is 20μm 1 lower gate length is 40μm
And...

FIG. 3 shows an example of the characteristics of a prototype thin film transistor compared with a conventional one. In a conventional single-gate transistor, the ON-□・C)F IP ratio is about IQ4, but in this embodiment, it is about 10', which is an improvement of about two orders of magnitude. effective.

In this embodiment, as the lower gate TIf,g, C
Although gold is used, it goes without saying that the same effect can be obtained by using high-melting point metals such as Ni, W, and MO, or transitional metal silicides such as nickel silicide and molybdenum silicide.

〔Effect of the invention〕

According to the present invention, during the OFF operation, the depletion 1- spreads in the upper and lower parts of the semiconductor thin film sandwiched between the two gate electrodes, completely blocking the flow of carriers. Therefore, the carriers are swept away from the vicinity of the interface with the insulating film, where the leakage current is large, and a large OF
F resistance is obtained. In addition, during ON@ operation, the large lower gate electrode forms a continuous channel between the source and drain including the gap at the top, so the ON resistance is reduced. Above all, ON-0 with large resistance
This has the effect of increasing the FF ratio.

[Brief explanation of the drawing]

FIG. 1 is a longitudinal sectional view of a polycrystalline silicon thin film transistor of the present invention, and FIG. 2 is a sectional view taken along line A-Ai in FIG. FIG. 3 is a diagram showing an example of the characteristics of a prototype # membrane translister. 1... Insulating substrate, 2... Lower gate electrode, 3...
・Insulating film, 4... Silicon film containing polycrystal, 5...
Insulating film, 6... Source/electrode, 7... Drain electrode, 8... Upper gate electrode, pole, 9... Thin film transistor of this embodiment, 10... Conventional thin film transistor. Figure 1 A Figure Z Figure 3 Gate (v) Continuation of page 1 J Higashi Koioken Death Sho Uchigakubo 1-28 @ Address Display of Hitachi, Ltd. Intermediate Procedural Amendment Case 1981 Patent Application No. 190738 Name of the Invention Group for Correcting Polycrystalline Silicon Thin Film Transistors, 11 Jun 1 Patent Applicant f'tGli L5101 Stock Qrl It'l'
, 'Zig's work Osamu Toshiro Human population +f 〒Iω1-115-1 Marunouchi, Chiyoda-ku, Tokyo
No. Stock Co., Ltd. 1 [:1 Stand Rasoi 11', +su1 inside,:1
Story Bow.../l! 1llt Human Rights) J Supplementary Notes ``Scope of Claims''σ'' in the description of the invention ``Detailed Description of the Invention'' The claims are serially numbered +lt', il on a separate sheet. 2, page 3, line 6 11σ of the present specification) r Ill I
ll Correct J to "μTn". 3. r V Op OLl r on page 4, line 2 of the same above.
Correct J to rVapourJ. . 4. Ibid., page 4, line 11, 1-1, -) 1 ion” is replaced with “
P+ ion”. Attached Claims: A field effect transistor using a semiconductor thin film containing polycrystalline silicon grains as an active region, characterized in that gate electrodes are disposed above and below the semiconductor thin film. Thin film 1 ~ transistor. 2. The length in the source/drain direction of the gate electrode placed on the back side of the semiconductor thin film surface where the source electrode and drain electrode are placed is longer than the length in the same direction of the gate electrode placed on the front side. A thin film 1-run lister according to claim 1, characterized in that it has an asymmetric structure. 3. The thin film transistor according to claim 1 or 2, wherein the gate electrode disposed under the semiconductor thin film is made of a high melting point metal or a transition metal silicide.

Claims (1)

[Claims] 1. In a 'field-effect transistor' in which a semiconductor thin film containing silicon crystal grains with a grain size exceeding 10 cm is used as an active region, gate 'ttL poles are arranged at the upper and lower parts of the semiconductor thin film. A thin film transistor characterized by: 2. The gate electrode is placed on the back side of the semiconductor thin film surface on which the source and drain electrodes are arranged.
2. The thin film transistor according to claim 1, wherein the thin film transistor has an asymmetric structure in which the length in the source-drain direction is longer than the length in the same direction of the gate electrode disposed on the front side. 35. The thin film transistor according to claim 1 or 2, wherein the gate electrode disposed under the semi-rod thin film is made of a high melting point metal or a transition metal silicide.