JPS6081982A - solid state imaging device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] Technical Field The present invention relates to a signal processing circuit for a solid-state imaging device, and in particular to a signal processing circuit for a solid-state imaging device.
The present invention relates to a signal processing circuit for an S-type solid-state imaging device.

Background Art A CCD type solid-state image sensor (hereinafter abbreviated as CCD area sensor) having a horizontal charge-coupled device (HCCD) and a MOS type solid-state image sensor having a horizontal signal line (HSL) (hereinafter abbreviated as MOS area sensor) ) is publicly known.

Since these area sensors generate characteristic noise along with their output signals, many prior art techniques have been proposed to remove the noise. JP-A No. 53-40215 discloses that a horizontal signal line and a reference power source are connected by a reset transistor, and a vertical signal line and a horizontal signal line are connected by a horizontal scanning transistor and a clear transistor connected in parallel.

Television image engineering handbook, page 432 is MOS
In a line sensor, a method is disclosed in which a signal line and a reference power source are connected through a reset transistor, and the signal voltage is sampled. Sekin & Tompsett, Charge Transfer Device, Kindai Kagakusha, 49 pages, and How-e
s & Morgan, Charge-Coupled
Devices & systems, John
Wiley & Sons, page 74, discloses processing the signal voltage of a CCD area sensor by a quadratic double sampling technique.

DISCLOSURE OF THE INVENTION According to the above-mentioned prior art, a MOS area sensor or C
The SN ratio of the CD area sensor is improved.

However, the S/N ratio of solid-state imaging devices needs to be further improved, and many problems need to be solved for practical use. The problem with conventional MOS area sensors equipped with a reset transistor that connects the horizontal signal line and the reference power supply is that the signal charge is divided into the vertical signal line and the horizontal signal line, so the signal voltage on the horizontal signal line becomes small. be. Because the horizontal signal line is not sufficiently charged due to the large capacity of the vertical signal line and the short turn-on time of the horizontal scanning transistor, only about 30% of the signal charge of the photocell is transferred to the HS.
Sent to L. The clear operation of the clear transistor performed during the horizontal blanking period is performed on the vertical signal line (V
A fixed noise charge is left in SL). The above-mentioned fixed noise charges are generated due to variations in the horizontal scanning transistor and the clear transistor or variations in the horizontal scanning pulse voltage and the clear pulse voltage. The problem with conventional CCD type area sensors that use phased double sampling circuits is that the clamp circuit and sample hold circuit of the phased double sampling circuit involve switching operations, so it is difficult to configure them with bipolar signal processing circuits. It is a certain thing. Furthermore, the clock noise of the clamp circuit and sample-and-hold circuit described above lowers the signal-to-noise ratio of the signal. The present invention has been made to solve the above problems. Several independent inventions are disclosed to solve the above problems. These independent inventions are described together because they are deeply interrelated and produce synergistic effects when practiced together. The present invention therefore improves the signal-to-noise ratio of a solid-state imaging device. JP58-1
5374, JP 58-59681, JP 57-1871
No. 73 is a prior invention of the present invention filed by the present applicant. JP 57-41081, JP 57-65073
, JP 57-83974, JP 58-145153, JP 57-107771, JP 57-129146 JP 5
No. 8-6134 and Japanese Patent Application Publication No. 58-20405 are prior inventions related to the present invention. The features and advantages of the present invention are explained below.

Independent Invention 1 (Claim 1) In the MOS area sensor having the structure of Claim 1, the reset transistor operates during the first period to apply a reference potential to the horizontal signal line, and the clamp circuit operates during the next second period. Then, a reference potential is applied to the second end of the coupling capacitor, and a signal charge is read out from the storage capacitor to the HSL in the next third period. In this way, the reset noise caused by the reset transistor is greatly reduced, and the average signal voltage output is greatly increased compared to the embodiment in which a resistor is connected to the horizontal signal line. In a conventional example in which a horizontal switch circuit is configured by a horizontal scanning transistor and a clear transistor, and is equipped with the above-mentioned reset switch, VSL and H
Due to the capacitance division of the SL and the shortening of the operating time of the horizontal scanning switch, the signal voltage of the HSL has been significantly reduced. According to the present invention, it is possible to obtain a horizontal signal voltage that is two to three times higher than that of the conventional example, and furthermore, the horizontal scanning switch can be made smaller, so that horizontal scanning noise is reduced. Furthermore, by setting the second period after the first period, or by setting the second period to overlap with the first period, the reset noise output during or after the first period can be reduced as described above. It can be removed with a clamp circuit. As a result of the above, the signal-to-noise ratio of the signal was greatly improved.

Dependent invention 1, (Claim 2) In Independent Invention 1, the structure of Claim 2 is added.

Then, the output signal voltage is selectively transmitted by the sample and hold circuit or the analog transmission gate circuit during a fourth period other than the first period or the second period. In this way, horizontal scanning noise voltage can also be removed. However, before the fourth period begins, the signal charge needs to be read out from the storage capacitor to the HSL. In conventional line sensors, it is known to eliminate horizontal scan noise through the use of reset switches and sample and hold circuits. However, when this technology is applied to an area sensor, there are disadvantages in that the signal voltage of the HSL becomes small and that a large residual signal charge exists in the VSL due to the reason explained in Independent Invention 1. Furthermore, due to the reset noise, the SN
The ratio has dropped significantly. Furthermore, in the conventional phase-box double sampling technique, it was not publicly known that by applying this technique to the MOS area sensor of Independent Invention 1, horizontal scanning noise can be removed together with reset noise. According to the present invention, since horizontal scanning noise and reset noise can be removed, the signal-to-noise ratio of a signal can be greatly improved, especially in a MOS area sensor equipped with a horizontal scanning transistor. The horizontal switch circuit of Independent Invention 1, the reset switch,
Horizontal scanning noise can be removed by using a sample hold circuit or an analog transmission gate circuit and setting the first, third, and fourth periods so that they do not overlap.

Furthermore, reset noise can also be removed by using a low-pass filter. Note, however, that noise charge remains in the HSL after the reset period (first period) due to clock voltage fluctuations or thermal fluctuations when the reset switch turns off. If this noise voltage is clamped via a capacitor (coupling capacitor), S
The N ratio is further improved. This is due to the fact that the fluctuation noise described above does not change much over a short period of time. That is,
Low frequency components of fluctuation noise are cut out. The high frequency components are then suppressed by a low pass filter. In the horizontal switch circuit disclosed in Independent Invention 1, VS
The fact that 80% to 95% or more of the signal charge of L can be transferred to HSL has been explained by the prior invention by the present applicant. As a result, the problem of clearing residual signal charge (residual signal charge in VSL) by using a reset switch becomes easier. In the past, a clear switch connected in parallel with a horizontal scanning switch generated a large amount of noise. This is due to variations in the clear pulse voltage and horizontal pulse voltage, and variations in the threshold voltage or capacitance of the clear transistor and horizontal scanning switch. Furthermore, since the reset switch of the present invention only needs to discharge HSL, it can be made smaller and its reset noise can be reduced. The above explanation is an explanation of both independent invention 1 and dependent invention 1. Note that the sampling of signal voltages by the analog transmission gate circuit is simpler than the sample-and-hold circuit disclosed in the conventional phase-box double sampling technique, and has the advantage that it can be constructed using a bipolar integrated circuit. In conventional sample and hold circuits, the noise voltage coexisting with the input signal voltage at the moment the sampling switch turns off is held only during the hold period. As a result, the instantaneous high-frequency noise voltage mentioned above is lowered in frequency, and there is a drawback that it cannot be removed even by using a low-pass filter.

By using an analog transmission gate circuit, the above-mentioned high frequency noise voltage is transmitted as is, and therefore can be easily removed by a low pass filter.

Dependent Invention 2, (Claim 3) In the structure of claim 3, the horizontal scanning noise can be made much smaller than in the embodiment using horizontal scanning transistors, so it is possible to start the fourth period at a time when the third period does not end. can. The problem with dependent invention 1 is that it is necessary to set the first, second, third, and fourth periods within one pixel processing period. In the conventional corrugated double sampling technique, each period is set independently from each other. As a result, the operating time of each switch became extremely short, and the increased number of pixels made design extremely difficult. For example, one pixel signal is 130n
When processing in seconds, each period is 20nsec.
, and a transition period of about 13 nsec is arranged between each period. The present invention ameliorates the above problems.

Dependent Invention 3 (Claim 4) In the structure of claim 4, since the clamp circuit suppresses transmission of switching noise of the reset switch, the fourth period can overlap with the third period. As a result, each period can be made longer than the conventional double sampling technique. Increasing the signal transmission period (fourth period) improves the average SN ratio.

Dependent Invention 4 (Claim 5) In the structure of Claim 5, horizontal scanning noise becomes extremely small. Therefore, by setting the first period within the second period, a signal voltage with very small reset noise and horizontal scanning noise can be generated at the second end of the coupling capacitor. As a result, the sample and hold circuit or analog transmission gate can be set to any time period. Also,
The sample hold circuit and analog transmission gate circuit can be omitted. As a result, each period becomes longer, the average signal-to-noise ratio is improved, and circuit design is simplified. For example, when processing one pixel signal in 130 nsec, the first period starts at the same time as the second period, the first period is 40 nsec, the second period is 60 nsec, and the fourth period is 70 nsec.
The third period is arbitrarily set within the fourth period.

Dependent invention 5, (claim 6) In the structure of claim 6, in each horizontal scanning period,
Each HSL receives signal charge from a different VSL. In this way, each HSL can operate in an overlapping manner, so that the time required for processing one pixel signal increases significantly. In preferred embodiments, two or four HSLs are provided. In this way, each of the first to fourth periods becomes significantly longer, which facilitates circuit design and reduces clock power.

Independent Invention 2 (Claim 7) The structure and advantages of claim 7 are set forth in claim 2. Claim 7 is an extension of claim 2.

Dependent Inventions 1, 2, (Claim 8), (Claim 9) In the structure of Claim 8, a simple bipolar analog transmission gate circuit is disclosed. In a preferred embodiment, the output signal voltage is generated from the collector of the bipolar transistor and the pulse circuit is a second bipolar transistor. In this way, in an embodiment in which a plurality of analog transmission gates are arranged, it is possible to suppress the level difference due to variations in the base/emitter voltage and the increase in clock power.

Independent invention 3 (Claim 10) The structure and advantages of claim 10 are explained in claim 3.

Claim 10 is an extension of claim 3. HCCD
DC MOS gate (potential barrier) between
In a CCD type linear or area sensor equipped with
Since the transfer clock noise of the HCCD is constant and very small, even if the fourth period is executed before the end of the third period, the deterioration of the S/N ratio is very small. Of course, it is also possible to remove transfer clock noise with a low-pass filter.

In this way, each period can be extended.

Independent invention 4 (Claim 11) The structure and advantages of claim 11 are the same as claim 4.

Claim 11 is an extension of claim 4. In this way, the first to fourth periods can be extended.

Dependent invention 1, (Claim 12) The structure and advantages of claim 12 are the same as claim 5.

In this way, the first to fourth periods can be extended. In preferred embodiments, sample and hold circuits or analog transmission gate circuits are omitted. The period other than the second period is the fourth period, and the third period is set within the fourth period.

Independent Invention 5 (Claim 13) The problem with each of the above inventions or the conventional phase-box double sampling circuit is the design of a high-speed clamp circuit. Particularly in embodiments that do not have sample-and-hold circuits or analog transmission gate circuits, the clamp circuit must operate at high speed. (It is necessary to fix the potential of the second end of the coupling capacitor at high speed.) In adopting the structure of claim 13, the above problem is solved. That is, the clamp period (second
period), if the potential fluctuation at the first end of the coupling capacitor increases the emitter-base voltage of the emitter-follower transistor of the charging circuit, the emitter-follower transistor will flow a large charging current and charge the coupling capacitor. The potential change at the second end of is suppressed. Then, the above-mentioned potential fluctuation at the first end of the coupling capacitor is rapidly discharged due to the constant current discharge characteristic of the discharge circuit. During this discharge, the charging current of the emitter follower circuit is suppressed to zero or to a large extent.

The more the emitter resistance of the discharge circuit is reduced, the larger the above-mentioned discharge current becomes. In a preferred embodiment, a DC voltage is applied to the base of the second bipolar transistor, the control circuit is a third bipolar transistor, and the emitter follower transistor (of the charging circuit) and the base of the third bipolar transistor are Pulse voltages of opposite phase are applied. In this way, the clamp circuit can be constructed from a bipolar transistor integrated circuit. Furthermore, the second bipolar transistor can be operated in saturation. In a preferred embodiment, if the polarity of the signal voltage is designed so that the reset-off pulse noise voltage generated when the reset switch turns off reduces the above charging current, the falling transient waveform voltage of the reset-off pulse noise voltage will be reduced by the charging current. Since the emitter-base voltage of the emitter follower transistor of the circuit is pushed in the direction of increasing, the falling transient waveform voltage of the reset-off pulse noise voltage mentioned above can be clamped at high speed. As a result, the clamp period can end immediately after the reset period ends.

In each of the above-mentioned inventions, it is equivalent to adding known or unknown electric parts to the extent that the basic operation is not impaired. Other features and effects of each of the above inventions will be explained below. FIG. 1 is an equivalent circuit representing the correlated double sampling technique described in the Description of the Prior Art section. C.C.
The signal charge outputted from D1 is changed into a voltage by the output diode 2, and the output diode 2 is reset to the DC potential Voc1 by the reset switch 3.

Node 2A is connected to clamp switch 6 via amplifier 4A and coupling capacitor 5. Node 5B is input to a sample hold circuit constituted by sample switch 7 and capacitor 8 via amplifier 4B. Amplifier 4
C has high input resistance. FIG. 2 is a clock waveform diagram of FIG. FIG. 3 is an equivalent circuit representing one embodiment of the present invention. VSL12 and HSL11 are connected by a horizontal switch circuit 9. Briefly, during the horizontal blanking period, the signal charge of VSL is incompletely transferred to the second end of the first capacitor 9C via the first transfer gate having a DC gate potential, and further transferred to the second end of the first capacitor 9D. is incompletely transferred to the second end of the storage capacitor 9E via the storage capacitor 9E. The third capacitor 9A is a capacitor for stopping transfer, and the complete transfer gate 9F is a transfer gate for clearing noise charges. The third transfer gate 9G having a DC gate potential is a potential barrier, and when the horizontal scanning circuit 10 applies the horizontal scanning pulse voltage VX to the first end of the storage capacitor 9E, the signal charge at the second end reaches the above potential. Transferred across the barrier to HSL. HSL 11 is connected to reset switch 3 and amplifier 4A. Regarding the incomplete transfer operation and variations of horizontal switch circuits, reference is made to the above-mentioned prior application by the applicant. Amplifier 4A is connected to clamp circuit 6 via coupling capacitor 5. Then, the signal voltage at the second end of the coupling capacitor is outputted via the amplifier 4B. A clock waveform diagram of the signal processing circuit of FIG. 3 is illustrated in FIG. however,
Voltage value and polarity can be freely designed. Since the first period in which the reset switch operates is included in the second period in which the clamp circuit operates, the potential at the second end 5B of the capacitor 5 is hardly affected by reset noise. After the clamp switch is turned off, a third period in which the horizontal scanning pulse voltage is applied to the capacitor 9E is set, so that the signal voltage is output in the fourth period in which the HSL voltage is output. Since the horizontal scanning noise of the horizontal switch circuit described above is small, the dynamic range of the amplifier 4A may be small. However, in order to improve the S/N ratio, the amplifier 4A preferably includes a voltage amplification amplifier built into the solid-state image sensor. In one embodiment, the voltage amplification amplifier described above is a CMO
It is an S source grounded amplifier. The above P-type well for the CMOS amplifier can be manufactured using the same process as the P-type well for blooming suppression. However, it is preferable to create the resistor connected to the amplifier in the signal processing chip. FIG. 5 is an equivalent circuit diagram showing another embodiment of the present invention. 5 is basically the same as that shown in FIG. 4 with an analog transmission gate circuit 13 added thereto. However, other embodiments of the horizontal switch circuit are disclosed. Specifically, the third capacitor 9F and the fourth transfer gate 9H
is added. These are MOS electrodes, and signal charges are completely transferred. FIG. 6 is a clock waveform diagram of one embodiment of FIG. 5. The first period in which the reset switch operates (R1
) and the second period (C2) in which the clamp circuit operates overlap. After the clamp period ends, a third period (S
3) is set, and the fourth period (T4) in which the analog transmission gate circuit operates overlaps with the third period. The above-mentioned overlapping times are arbitrary. 7 and 8 represent an equivalent circuit of one embodiment of the clamp circuit. In FIG. 7, a clock voltage V is applied to the base of the emitter follower transistor 14, which is a charging circuit.
2 is applied. The emitter is connected to the second end 5B of the coupling capacitor 5. The discharge circuit includes a second bipolar transistor 15 and a third bipolar transistor 16 whose emitters are connected to a common emitter.

A DC voltage is applied to the base of the third bipolar transistor 16, and a clock voltage V2 is applied to the base of the second transistor 15 via a rectifier. Rectifying element 1
One end of 7 is connected to the first power supply Vs via a resistor 18. If the clock voltage changes and the base of the second transistor 15 becomes 0.5 V or more lower (negative) than the base of the third transistor, the second transistor is cut off.
The discharge stops. If the second terminal 5B is connected to an amplifier with a high input resistance, the potential at the second terminal 5B will be held for a sufficiently long period, so that the clock voltage V2 can be changed by changing 1V or more to reduce the emitter voltage. Follower transistor 14 is also cut off. And again the clock voltage V2
When V changes to positive, transistors 14 and 15 turn on.

The second terminal 5 is connected via a rectifying element instead of the transistor 14.
It is possible to apply a clock voltage to B. Further, it is possible to apply a DC potential to the emitter of the second transistor 15 via a rectifier instead of the third transistor 16. FIG. 8 is a modified embodiment of FIG. 7, and discloses that a DC voltage is applied to the base of the second transistor 15 and an opposite phase clock waveform V2 is applied to the base of the third transistor 16. Of course, the clock voltage V2 may be applied to the emitter of the second transistor 15 via a rectifier instead of the third transistor. FIG. 9 is an applied embodiment of FIG. 5, and discloses that two HSLs are arranged and three analog transmission gate circuits are arranged at the second ends 5B2 and 5B1 of the coupling capacitor 5, respectively. HSL11
A is connected to the VSL of the odd numbered column, and HSL11B is connected to the VSL of the even numbered column. The signal processing circuit connected to the HSL 11B operates in a phase 180 degrees different from that of the signal processing circuit connected to the HSL 11A. The analog transmission gate circuits 13 (A to F) each separate the color signals. The separated color signals are then sent to an adder 44 (A
, B, C). According to this embodiment, color separation is performed by arranging a plurality of analog transmission gate circuits shown in FIG. FIG. 10 is a sectional view of one embodiment of an analog transmission gate circuit. Three bipolar differential amplifiers 24, 25, 26 are arranged, and each differential amplifier 24, 2
5 and 26 have the same structure. Each amplifier includes a first transistor 20A and a collector resistor 23 connected to its collector.
A, an emitter resistance 22A sustained at its emitter,
It has a second transistor 21A whose common emitter is connected. An input signal voltage is applied to the base of the first transistor 20A, and clock voltages V4X, V4Y, V4Z are applied to the base of the second transistor. It is possible to take out the output from the emitter, and it is also possible to apply the clock voltage through a rectifier instead of the second transistor. When the first transistor is cut off, its collector is held at the second power supply potential VD. The analog transmission gate circuit of FIG. 9 may be understood with reference to FIG. FIG. 11 shows one of the adder circuits 44 (A, B, C) in FIG.
This is an equivalent circuit for explaining the embodiment, and in particular only 44A is shown.

[Brief explanation of drawings]

FIG. 1 is an equivalent circuit diagram showing a conventional phase-box double sampling circuit. FIG. 2 is a clock waveform diagram of FIG. Figure 3
1 is an equivalent circuit diagram representing one embodiment of the present invention. FIG. FIG. 4 is a clock waveform diagram of FIG. 3. FIG. 5 is an equivalent circuit diagram showing another embodiment of the present invention. FIG. 6 is a clock waveform diagram of one embodiment of FIG. 5. 7 and 8 are equivalent circuit diagrams representing the clamp circuit of the present invention. FIG. 9 is a block diagram representing an applied embodiment of FIG. 5. FIG. 10 is an equivalent circuit diagram showing the analog transmission gate circuit of the present invention. FIG. 11 is an equivalent circuit diagram showing the adder circuit. Patent applicant Shoichi Tanaka

Claims (13)

[Claims] (1) In a MOS solid-state imaging device equipped with a vertical signal line (abbreviated as VSL) and a horizontal signal line (abbreviated as HSL), a horizontal switch circuit that connects VSL and HSL, and a horizontal switch circuit that connects VSL and HSL,
The horizontal switch circuit includes an incomplete transfer gate, a storage capacitor, and a horizontal scanning element, and the potential fixing circuit has a first terminal connected to a signal voltage. A MOS solid-state imaging device comprising a coupling capacitor to which an applied voltage is applied, and a clamp circuit whose first end is connected to a second end of the coupling capacitor. (2) The MOS solid-state imaging device according to item 1, wherein the second end of the coupling capacitor is connected to a sample hold circuit or an analog transmission gate circuit either directly or via an amplifier. (3) The second end of the storage capacitor described above is connected to the HSL via a potential barrier, and the third period in which the horizontal scanning pulse voltage is applied to the first end of the storage capacitor that also serves as a horizontal scanning element is as described above. 3. The MOS solid-state imaging device according to item 2, wherein the period overlaps with the fourth period in which the sample-and-hold circuit or the analog transmission gate circuit operates. (4) The MOS type solid-state imaging device according to item 1, wherein the first period in which the reset switch operates overlaps with the second period in which the clamp circuit operates. (5), the second end of the above storage capacitor is connected to the HSL via a potential barrier, and a horizontal scanning pulse voltage is applied to the first end of the storage capacitor which also serves as a horizontal scanning element, and the above first period 5. The MOS solid-state imaging device according to item 4, wherein is set within the second period. (6), multiple horizontal signal lines (HSL) are arranged, and each
2. The MOS solid-state imaging device according to claim 1, wherein the SLs receive signal charges from different VSLs. (7), horizontal charge coupled device (abbreviated as HCCD).
or in a linear or area solid-state imaging device with HSL. The output diode or HSL of the HCCD is connected to one end of the reset switch, and the output diode or HSL of the HCCD is connected to the first end of the coupling capacitor through an amplifier.
the second end of the coupling capacitor is connected to the first end of the clamp circuit, and the second end of the coupling capacitor is connected to the analog transmission gate circuit directly or through an amplifier. Solid-state imaging device. (8) The above analog transmission gate circuit includes a bipolar transistor, an emitter resistor that connects its emitter to the first power supply, a collector resistor that connects its collector to the second power supply, and a pulse circuit that controls the emitter potential. The input signal voltage is applied to the base of the above transistor, the output signal voltage is generated from the collector or emitter of the above transistor, and the above collector resistor can be omitted when the output signal voltage is generated from the emitter. 8. The solid-state imaging device according to claim 7. (9) The above pulse circuit is a rectifier or a second bipolar transistor, and the first end or the second bipolar transistor of the rectifier
9. The solid state according to claim 8, wherein the emitter of the bipolar transistor is connected to the emitter of the signal amplification transistor, and a pulse voltage is applied to the second end of the rectifying element or the base of the second bipolar transistor. Imaging device. (10) In a linear or area solid-state imaging device with an HCCD or HSL, the output diode or HSL of the HCCD is connected to one end of the reset switch, and the output diode or HSL of the HCCD is connected to the first end of the coupling capacitor through an amplifier.
a second end of the coupling capacitor is connected to a first end of the clamp circuit, and a second end of the coupling capacitor is connected to a sample and hold circuit or an analog transmission gate circuit, either directly or through an amplifier; and H.C.C.
A solid-state imaging device characterized in that a third period in which signal charges are read out to the output diode of D or HSL overlaps with a fourth period in which the sample-and-hold circuit or the analog transmission gate circuit operates. (11) In a linear or area solid-state imaging device with an HCCD or HSL, the output diode or HSL of the HCCD is connected to one end of the reset switch, and the output diode or HSL of the HCCD is connected to the first end of the coupling capacitor through an amplifier.
The second end of the coupling capacitor is connected to the first end of the clamp circuit, and a signal voltage is output from the second end of the coupling capacitor. A solid-state imaging device characterized in that the period overlaps with a second period in which a circuit operates. (12) The solid-state imaging device according to item 11, wherein the second period includes the first period. (13) In a linear or area solid-state imaging device with an HCCD or HSL, the output diode or HSL of the HCCD is connected to one end of the reset switch, and the output diode or HSL of the HCCD is connected to the first end of the coupling capacitor through an amplifier.
the second end of the coupling capacitor is connected to the first end of the clamp circuit, the clamp circuit comprising a charging circuit and a discharging circuit, the charging circuit comprising a rectifying element or a bipolar transistor; The first end of the bipolar transistor or the emitter of the bipolar transistor is connected to the second end of the coupling capacitor, and a pulse voltage φ1 is applied to the second end of the rectifying element or the base of the bipolar transistor. A bipolar transistor, an emitter resistor that connects its emitter to a first power supply,
A control circuit for controlling the emitter potential is provided, and a pulse voltage φ2 or a DC voltage is applied to the base of the second bipolar transistor. The first end of the second rectifying element or the emitter of the third bipolar transistor is connected to the emitter of the bipolar transistor, and a pulse voltage φ3 or a DC voltage is applied to the second end of the second rectifying element or the base of the third bipolar transistor. A solid-state imaging device characterized in that a voltage is applied.