JPS607908B2 - Master-slave voltage regulator with pulse width modulation - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to DC power supplies, and more particularly to DC power supplies that use pulse width modulation (PWM) regulation to generate a regulated output voltage (AC or DC) from a primary input DC voltage. This invention relates to a DC-DC voltage converter.

The principles of PWM regulation are known in the art.

PWM regulators operate on the basic principle that the input DC voltage to be regulated is turned on and off or pulsed by a switching device (for example a transistor). The resulting rectangular pulse is applied through a transformer to a rectifier circuit (including a smoothing filter) to generate the desired regulated DC output voltage. By converting the input voltage into a pulse train, the magnitude of the rectified output voltage can be adjusted by varying the pulse width while keeping the pulse frequency constant. Automatic control of such systems is
This is accomplished by monitoring the magnitude of the DC output voltage and providing suitable circuitry to vary the pulse width as necessary to maintain the magnitude of the DC output voltage at a desired level. Please note that examples of prior art devices include those shown in the following US patents:

No. 3670234 June 13, 1972 James
sM. Joyce; No. 3789288 1974 King 1
B. dated March 29th. Day. Assow et al.; No. 3806791 197 King of France dated April 23, oJ. Johnson; No. 3870943 Dated March 11, 1973. R. W
eische ship 1st class; No. 3988661 Daniel J., October 26, 1976. McCoy.

One of the technical problems with conventional circuits using PW vessel regulators is the problem of maintaining current balance between the alternating switch devices (eg, transistors) that convert the DC input voltage into a pulse train.

These switch devices form the inverter section of the power supply, and furthermore, for optimal operation from the circuit, the power processed by each switch device is processed by other switch devices in the circuit. Must be equal to power. Another technical problem with conventional circuits is that
Occurs when multiple power supplies are connected in parallel to provide more power to a common load.

Prior art circuits are complex and cumbersome for power division between several power sources. The present invention is based on the known principles of PWM regulation, but uses a new master-slave type device to control the width of the pulses generated by the inverter section of the circuit.

This master-slave type device has several slaves.
It allows the unit to be used with a single master unit and also allows two or more power supplies to be paralleled, while ensuring current division between the power supplies. The configuration of the master unit and slave unit is the same, with differences depending on how they are wired into the circuit (ie, master or slave). According to one embodiment of the invention, the power supply (ie the DC to DC voltage converter) consists of one master unit and one slave unit.

It is equipped with a clock circuit having one output line for the master unit and one output line for the slave unit. The clock generates on each of its output lines a rectangular pulse train with only one pulse on one line at a given time, so that all pulses are of the same duration. The master unit is a transistor switch used to interrupt the input DC voltage in response to a pulse train-based signal that the master unit receives from a clock but which is not modified by a control signal representing the regulated output voltage of the power supply. Contains. The slave unit responds to a signal based on a pulse train that the slave unit receives from the clock, but which is not modified by a control signal representing the regulated output voltage of the power supply and the difference in charge flowing through the master unit and the slave unit.
Contains a transistor used to interrupt the input DC voltage. The current pulses flowing through the transistors of the master and slave units pass through the primary winding of the transformer. The voltage induced in the secondary winding of this transformer is rectified and filtered to produce the required regulated output voltage. In another specific example, the present invention is a pulse width modulation conversion circuit for converting a primary DC voltage into a secondary voltage, the amplitude of the secondary voltage is adjusted by the conversion circuit, and the conversion circuit is (n+1
) clock means for providing a symmetrical train of pulses on each of the conductors at a given time, such that only one pulse occurs on one of the conductors at a given time, and n is a large positive integer equal to 1; means; master pulse width modulation means responsive to one pulse train of (n11) conductors and a feedback signal representative of the magnitude of the secondary voltage; a master pulse width modulation means for controlling the current through a portion of the line; n slave pulse width modulation means, each slave pulse width modulation means having a one-to-one relationship (n11) conductors; in response to one pulse train and an output control signal, the output control signal comprising a feedback signal representative of the magnitude of the secondary voltage and the magnitude of the charge flowing through the master pulse width modulation means and the charge flowing through each slave pulse width modulation means. n slave pulse width modulation means, each slave pulse width modulation means controlling the current through a portion of the primary winding of the transformer by means of a primary DC voltage.

In another specific example, the present invention is a pulse width modulation conversion circuit for converting a primary DC voltage into a secondary voltage, the amplitude of the secondary voltage is adjusted by the conversion circuit, and the conversion circuit is (n + 1).
clock means for supplying symmetrical rectangular pulses to each of the conductors, the clock means generating only one pulse on one of the conductors at a given time, n being a positive integer equal to or greater than one; master pulse width modulation means responsive to a pulse train of one of the (n+1) conductors and a feedback voltage representative of the magnitude of the secondary voltage, the primary DC voltage causing current through the primary winding of the transformer; A master pulse width modulation means to control: n slave pulse width modulation means, each slave pulse width modulation means having a one-to-one relationship (
n+1) conductors and an output control signal, the output signal being a feedback signal representative of the difference in magnitude between the charge flowing through the master pulse width modulation means and the charge flowing through the respective slave pulse width modulation means. n slave pulse width modulation means, each slave pulse width modulation means controlling the current through a respective different part of the primary winding of the transformer with said primary DC voltage; and a secondary winding of the transformer. rectifying means connected to the secondary winding of the transformer for rectifying the resulting voltage appearing on the line and thereby generating a secondary voltage; monitoring the secondary voltage and representing the magnitude of the secondary voltage; and control circuit means for providing a feedback signal.

The invention will now be described in detail with reference to the accompanying drawings.

FIG. 1 is a simplified block diagram of the present invention.

The figure consists of a master pulse width modulator (PWM) 10 and n slave pulse width modulators designated 10a to 10n. The clock 12 supplies a rectangular pulse train to each of the (n+1) lines (i.e., conductors), and the pulses on line 14 are the master PWMIO', and the added pulses on lines 14a to 14n are the slave PWMIO's of 10a to 10n. are added to each. clock 12
operates such that at a given time there is one pulse on any of lines 14 to 14n. Master PWMI with optional pulse width modulated power regulator
The purpose of slave PWMI 0a to 10n is to cut off the input DC voltage.

An input DC voltage is applied to terminals 15 and 16, and a positive voltage is applied to terminal 19. The master PWMIO and each slave PWMIO 0a to 10n each have switching
It includes transistors 8 to 18n. Terminal 16 is connected to each transistor 18 to 18 by winding 20 to 20n.
n collectors, respectively. The outer emitter of each transistor is connected to the negative terminal 15 through resistors 22 to 22n, respectively. Resistance 22 to 22n
are extremely low values, each having a resistance of approximately 1 ohm, and are used as sensing resistors. winding 20 to 20
Note that n forms the primary winding of transformer 23. Windings 20 to 20n were Y-connected (n+1
) phase primary winding.

The secondary winding of the transformer 23 is composed of (n11) windings designated by reference numbers 24 to 24n. The windings 24 to 24n are considered to be Y-connected (n11) phase secondary windings.

The rectifier circuit 25 is connected to the windings 24 to 24n,
A rectified DC output voltage is generated at terminals 47 and 48. If desired, the number of secondary windings 24 to 24n may be fewer than shown, and more output voltages may be obtained from rectifier 15 than shown. Feedback control circuit 26 monitors the DC output voltage of rectifier 25 and generates a feedback signal 27 on line 28.

Signal 27 goes to master PWMIO and 29a to 2
Slave PWMI0a to 10n by 9n adder circuit
are supplied to each. The current flowing through transistor 8 of master PWMIO flows through resistor 22, and the magnitude of the voltage drop across resistor 22 represents the magnitude of the current flowing through resistor 22 and, therefore, through transistor 18. This voltage drop is transferred from the adding circuit 30a to 3 by the line 31.
Added to 0n. The remaining inputs of each of summing circuits 30a to 30n are supplied with a voltage between resistors 22a to 22n, respectively, as seen on lines 32a to 32n, respectively. The signals appearing at the respective inputs of the adder circuits 30a to 30n are added algebraically according to the equation.The signals appearing at the respective inputs of the adder circuits 30a to 30n do not appear simultaneously;
Note that they appear in order. In other words, when a pulse signal is flowing through the line 31, the line 32a to 3
The potential of 1n is zero, and when a pulse signal is applied to line 32a, the potentials of line 31 and lines 32b to 32n are zero, and so on. The output of each adder circuit 30a to 30n is
They are added to integrators 33a to 33n, respectively.
Since the input of each integrator 33a to 33n consists of a series of rectangular pulses of approximately the same magnitude and duration and of alternating polarity, the output of each integrator 33a to 33n alternates around the average value. The outputs of the various dividers 33a to 33n are added by 29M from an adder circuit 29a, respectively. 2
The adder circuits 9a to 29n algebraically add the signals appearing at their inputs according to the symbols shown.

For control purposes, the output of each summing circuit 29a to 29n is applied to a slave PWMI 0a to 10n, respectively.The output signal of each summing circuit 29a to 29n is designated by reference number 34a to 34n, respectively.
a through 34n are used to modify the length of time each transistor 8a through 18n is turned on in response to a pulse from clock 12, respectively. In a preferred embodiment of the present invention, as described above, the secondary windings 24, 24
a, . .

FIG. 2 shows the diagram of FIG. 1 when n=1 (that is, there is only one slave PWM). FIG. The clock circuit 12 is of a secondary design and is connected to the line 1.
4 (negative going)
g) The first rectangular pulse train is generated on the line 14a, and the second rectangular pulse train (negative going) is generated on the line 14a. The pulses on each line 14 and 14a have a 50% duty cycle, and the pulses on line 14 are 1800 out of phase with the pulses on line 14a. Pulse frequency is 20KHz
It is. The pulse on line 14 is applied to capacitor 35 of master PWMIO.

The terminal of the capacitor 35 is connected to an inverter 36 connected to the base of the transistor 18. Railroad 1
4 applies a rectangular pulse train to the capacitor 35, so the capacitor 3 connected to the input of the inverter 36
The output of No. 5 is a damped exponential waveform. Inverter 36 converts this attenuated exponential waveform into a square wave and, of course, inverts its gutter nature. Feedback control signal 27 from the output of feedback control circuit 26 is applied to the input of inverter 36 through resistor 37 . The effect of the feedback control signal 27 is that the inverter 36
to set the "base" level and therefore the duty cycle of the square wave generated by the inverter 36,
This helps control the amount of time that transistor 18 conducts current. Signal 27 will be explained in more detail later. The input voltage to be regulated is applied to terminals 15 and 16, terminal 16 having positive polarity. Terminal 16 is connected to the connection between two windings 20 and 20a. When transistor 18 is conducting (on), current flows from terminal 16 through winding 20 to the collector of transistor 18 and through resistor 22 to transistor 18.
Flows from the emitter to terminal 15. Slave PWMI0
a operates similarly. Line 14a applies a rectangular pulse train to capacitor 39 of slave PWMI0a. The other end of the capacitor 39 is connected to the input of an inverter 40 connected to the base of the transistor 18a. Line 14a applies a rectangular pulse train to capacitor 39 whose output, applied to the input of inverter 40, has a decaying exponential waveform. The inverter 40 converts this attenuated exponential waveform into a rectangular wave and inverts its polarity. Output control signal 34a is applied to the input of inverter 40 by resistor 42. The function of the control signal 34a is that the inverter 4
Setting a "base" level of zero, thus controlling the duty cycle of the square wave generated by inverter 40, helps control the time that transistor 18a conducts current. Control signal 3
The occurrence of 4a will be explained in more detail later. slave PW
Transistor 1 8a of MI 0a is master PWMI
It performs the same function as the transistor 18 of O.

When transistor 18a of the slaved PWMIO is turned on, current flows from terminal 16 through winding 20a and through resistor 22.
a and finally flows to terminal 15. The effect of the current flowing in alternation but not in the windings 20 and 20a is that the transformer 23
inducing a voltage in the windings 24 and 24a.

This voltage is rectified by diodes 43 and 44 as shown. The inductance 45 and capacitor 46 are
Terminal 47 performs smoothing to smooth the rectified DC voltage output supplied to output terminals 47 and 48 of positive polarity. Feedback control circuit 26 senses the voltage between terminals 47 and 48 and provides a feedback control signal 27 which is applied by resistor 37 to the input of inverter 36 .

As previously mentioned, signal 27 is the "base" of inverter 36.
Give the level. Providing the base level of the inverter 36 means that the magnitude of the signal required for the capacitor 35 to change the output of the inverter 36 is variable, that is, the voltage across the inverter 36 can be effectively adjusted. means. As a result, inverter 3
The duty cycle of the square wave generated by 6 will be adjusted, thereby adjusting the "on" time of transistor 18. This provides feedback control functionality by adjusting the duty cycle of the master PWMIO. The desired magnitude of the output voltage between terminals 47 and 48 is adjusted by varying the value of a rheostat 49 connected in series with a resistor 50 between terminals 47 and 48 as shown in FIG.

The rheostat 49 and the resistor 50 form a voltage divider, the output of which is applied to the non-inverting input (10) of the operational amplifier 51. A voltage of approximately 130 volts is applied to terminal 52. Zener diode 5 is used to supply a regulated reference input voltage to the inverting input (1) of operational amplifier 51.
3 are used with resistors 54 and 55. Resistor 56 is a feedback resistor for amplifier 51 connected as shown. The symmetrical control circuit 57 in FIG. 2 includes the addition circuit 30a,
It incorporates the functions performed in FIG. 1 by integrator 33a and adder circuit 29a.

It can be seen that circuit 57 senses the current passed through master PWMIO' by sensing the voltage drop across resistor 22. This voltage drop is applied by line 31 and resistor 59 to the inverting input (1) of operational amplifier 58. Additionally, circuit 57 senses the current conducted by slave PWMI0a by sensing the voltage drop across resistor 22a.
This voltage drop is applied through line 32a and resistor 60 to the non-inverting input (10) of operational amplifier 58. As is well known, the integration function of the circuit 57 includes a resistor 61 and a capacitor 6 connected in parallel between the output of the operational amplifier 58 and its inverting input (1).
Provided by 2. Operation of adding the integrated output and the feedback control signal 27 (i.e., addition circuit 29a in FIG. 1)
is the non-inverting input (10) of the operational amplifier 59 and the output of the operational amplifier 51 (
2 by reference to signal 27). The output signal 34a is connected to the inverter 4 by the resistor 42.
0 force applied. The purpose of signal 34a is inverter 4
The goal is to provide a "base" level of 0.

Setting the "base" level of inverter 40 adjusts the point at which inverter 40 changes its output state (between a logic 0 and logic 1) and also controls how long transistor 18a conducts current, i.e., The voltage can be adjusted effectively. For example, if transistor 8 of PWMIO is conductive for a longer time than transistor 18a of PWMIOa, the pulse signal on line 31 applied to the inverting input (1) of amplifier 58 will be applied to the non-inverting input (10) of amplifier 58. Lasting longer than the applied pulse signal (on line 32a), the output signal 34a of amplifier 58 (provided the magnitudes of the two aforementioned pulse signals are equal) increases in the negative direction as a result.

This results in a negative increase in the bias of inverter 40, which in turn causes longer positive pulses to be generated at the output of inverter 40, thereby increasing transistor 8a for a longer period of time.
conducts current. Similarly, if the conduction time of transistor 8 of PWMI O is shorter than that of transistor 18a of main PWMI 0a, the pulse signal on line 31 applied to the inverting input (1) of amplifier 58 will be 10), the output signal 34a of the amplifier 58 increases in the positive direction (further provided that the magnitudes of the two aforementioned pulse signals are equal). This causes the bias of inverter 40 to increase negatively, and inverter 40 then generates a short positive pulse at its output, causing transistor 18a to conduct current for a shorter period of time than in the general case (i.e. , the product of the current 1 and the conduction time t of the transistor 18 (provided that the magnitudes of the current pulses passed by the transistors 8 and 18a, and therefore the pulse signals on the lines 31 and 32a, do not necessarily have to be of the same magnitude). is the same as the product of the same parameters for transistor 18a (i.e. 1×t for transistor 18 is 1×t for transistor 18a)
It is desirable to ensure that

Expressed in other words, the charge (1×t) passing through transistor 18 is the charge (1×t) passing through transistor 18a.
) is desirable. FIG. 3 shows two conversion circuits 65a and 65 constructed in accordance with a preferred embodiment of the invention, illustrated in simplified block form and interconnected for parallel operation.
b.

Conversion circuits 65a and 65b are identical to each other and very similar to the circuits illustrated in FIGS. 1 and 2. Because of this similarity, the components of circuits 65a and 65b have been assigned reference numbers ten orders of magnitude higher than similar components of FIG. For example, clock 1 in Figure 1
2 is represented by the clock 112 in the conversion circuit 65a of FIG. 3, and the slave PWM I0a of FIG. 1 is represented by the slave PWM II0a of FIG. Conversion circuits 65a and 65
b performs a similar function to the circuit of FIG. Circuit 6 in Figure 3
The differences between 5a (and 65b) and the circuit of FIG. 1 are as follows. The circuit in Figure 1 has one master PWMIO and one
Illustrated for the general case of n slave PWMs, denoted 0a to 10n, circuit 65a of FIG.
1 master PWMIO and 1 slave PWM
Illustrated for the special case of II0a. Circuit 65a of FIG. 3 is a master PWMIIO that causes the PWMIO to operate as a slave PWMII0a when circuit 65a is used in parallel operation with one or more power supplies (e.g., with circuit 65b as shown in FIG. 8).
Contains additional circuitry for use with. Master PW
Additional circuitry used with the MIIO includes line 132, summing circuit 130, integrator 133, summing circuit 129 and two single pole single throw (SPST) switches 66 and 67 (interconnected to operate in unison). ), all of which are illustrated and interconnected in FIG. Switches 66 and 67 change the master PWM from a ``master'' unit to function as a ``slave'' unit.

When switches 66 and 67 are in the closed position as in circuit 65a of FIG.
It performs the same function as MII0a (or slave PWMI0a in FIG. 1). Switches 66 and 67 constitute circuit 6 of FIG.
When in the closed position as in 5b, the master PWMII
O performs the same function as the master PWMIO in FIG. Note that circuits 65a and 65b differ only in the positions of switches 66 and 67. (Circuit 65a and 65
If an additional conversion circuit (identical to b) is connected in parallel to conversion circuits 65a and 65b, the PWMIIO of circuit 65b
switch 6 of the additional conversion circuit so that it is only a master PWM that in combination operates as a "master" unit.
The positions are 6 and 69 wide. Output terminals 147 and 148 of circuits 65a and 65b are connected in parallel to supply power to terminals 68 and 69, and input terminals 115 and 116 of each circuit 65a and 65b are also connected in parallel; Note that this is not shown in FIG. 3 to avoid clutter. Furthermore, when circuits 65a and 65b are connected in parallel, line 128 of circuit 65a is connected to line 128 of circuit 65b, and line 131 of circuit 65a is connected to line 131 of circuit 65b.

[Brief explanation of the drawing]

FIG. 1 is a simplified block diagram of the present invention. FIG. 2 is a simplified block diagram of one particular embodiment of the invention. FIG. 3 is a simplified block diagram illustrating two power converters (in accordance with a preferred embodiment of the invention) connected for parallel operation.
10: Master m pulse width modulation means, 10a,...,
10n; Slave pulse width modulation means, 12; Clock means, 14, 14a, ..., 14n; Conductor, 23
; Transformer, 27: Feedback signal, 25; Rectifier circuit, 33a,
..., 33n; integrator; 29a, ..., 29n; addition circuit; 30a, ..., 30n; addition circuit. di Sasa small JF crab〃2pa dF Sasa◇〆

Claims (1)

[Claims] 1. A pulse width modulation conversion circuit for converting a primary DC voltage into a secondary voltage, in which the magnitude of the secondary voltage is adjusted, (n+1) clock means 12 for supplying a symmetrical pulse train to each of the conductors 14, 14a, .
(n+1) conductors 14, 14a, .
. a master pulse width modulation means 10 for controlling the current through the portion 20 of the winding; n slave pulse width modulation means, each slave pulse width modulation means having one
(n+1) conductors 14, 14a,... in a pair-one relationship
Feedback signal 27 responsive to both the pulse train of one conductor 14a,..., 14n of ...14n and the output control signal 34a,..., 34n, the control signal representing the magnitude of the secondary voltage.
and the magnitude of the charge passing through the master pulse width modulation means 10 and the respective slave pulse width modulation means 10a, . . .
n slave pulses, each controlling the current through a part 20a,...,20n of the primary winding of the transformer 23 with said primary DC voltage, based on the difference in the magnitude of the charge passing through the primary DC voltage A pulse width modulation conversion circuit comprising width modulation means 10a, . . . , 10n. 2 The output control signals 34a, ..., 34n are: (1)
(2) a first algebraic sum of a negative signal representing the magnitude of the current passing through the master pulse width modulation means 10 and (2) a signal representing the magnitude of the current passing through the controlled slave pulse width modulation means 10a, . . . , 10n; are obtained by the adding circuits 30a, . . . , 30n; the first algebraic sum is obtained by the integrating means 33a, .
3n; the second algebraic sum of (1) the resulting first algebraic sum and (2) the signal 27 representing the magnitude of the secondary voltage is integrated in the adder circuit 29a.
, . . . , 29n, and the second algebraic sum becomes the output control signals 34a, . 3 The transformer 23 is Y-connected to (n+1) phase primary windings 20, 20a, ..., 20n, which are Y-connected.
) phase secondary windings 24, . . . , 24n. 4 Claim 1, 2 or 3 where n=1
The pulse width modulation conversion circuit described in . 5. In a pulse width modulation conversion circuit that converts a primary DC voltage into a secondary voltage and adjusts the magnitude of the secondary voltage, a first
A first symmetrical rectangular pulse train is applied to the conductor 14, and a second symmetrical rectangular pulse train is applied to the second conductor 14a.
clock means 12 for supplying a second symmetrical rectangular pulse train having a phase difference of 180° from the first pulse train; and a feedback signal 27 representing the magnitude of the first pulse train and the secondary voltage of the first conductor 14. master pulse width modulation means 10 responsive to the second conductor 14a for controlling the current through the first portion 20 of the primary winding of the transformer 23 by the primary DC voltage; one slave pulse width varying means 10a responsive to both the second pulse train and the output control signal 34a, the output control signal being responsive to the feedback signal 27 representing the magnitude of the secondary voltage and The primary DC voltage is determined by the difference in magnitude between the charge passing through the master pulse width modulation means 10 detected by the voltage drop and the charge passing through the slave pulse width modulation means 10a detected by the voltage drop across the resistor 22a. slave pulse width modulation means for controlling the current passing through the second portion 20a of the primary winding of the transformer 23. 6 rectifier means 25 connected to the secondary windings 24, 24a of the transformer 23 for rectifying the voltage appearing on the secondary windings, thereby generating a secondary DC voltage at the two terminals 47, 48; and; feedback control circuit means 26 for monitoring the secondary DC voltage and providing a feedback signal 27 representative of the magnitude of the secondary DC voltage. circuit. 7. The output control signal 34a is subjected to a first algebraic summation of (1) a negative signal representing the current flowing through the master pulse width modulation means 10 and (2) a signal representing the current flowing through the slave pulse width modulation means 10a. (1) Integration of the resulting first algebraic sum and (2) second algebraic summation of the signal 27 representing the magnitude of the secondary DC voltage are performed, and the signal generated as a result is used for output control. 7. The pulse width modulation conversion circuit according to claim 6, wherein the signal 34a is generated in a procedure. 8. The pulse width modulation conversion circuit according to claim 5, 6 or 7, wherein the configuration of the master pulse width modulation means 10 and the configuration of the slave pulse width modulation means 10a are the same.