JPS6076097A - Nonvolatile semiconductor memory - Google Patents

Abstract

PURPOSE:To ensure the strict control for the time of replacement of a read-only memory (E<2>PROM) which can be electrically erased and written, by accumulating and storing the write indicating signals to be applied to the E<2>PROM in response to the address of the E<2>PROM. CONSTITUTION:A center device 20 controls terminal devices set at four remote areas and transmits data. The terminal devices have prescribed actions based on the transmitted data. The address signals ADR and write enable signals WE' transmitted to E<2>PROMs 11-14 from the device 20 are also sent to an E<2>PROM set opposite to the device 20. The erasing/writing frequencies carried out by the center 20 for addresses corresponding to E<2>PROMs 11-14 are written and stored to the address which is designated by the E<2>PROM10 with the signal ADR. The number bit 17 for each word of the E<2>PROM10 can cover the upper limit values 10<4>-10<5> of rewritable frequencies of E<2>PROMs 11-14. Such rewriting frequencies stored in the E<2>PROM10 are read out to outside when necessary as the read data RDT and used as the maintenance data for necessary counterplans.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a non-volatile semiconductor memory, particularly an electrically erasable and programmable read-only memory (hereinafter referred to as gtpaoM).
No. 1! The present invention relates to a nonvolatile semiconductor memory suitable for managing the number of changes.

As is well known, electrically programmable read-only memory (hereinafter referred to as BFROM) is often a 70-gate type nonvolatile memory with a two-layer polysilicon structure, in which electrons are stored in the floating gate. By charging the MO8FffT, the threshold voltage of the MO8FffT is controlled in a binary manner. Since such a MOS type non-volatile memory has 1 bit/cell, the E of the large capacity 4 is
PROMs are widely used for storing microprograms in general-purpose computers and programs or data in microcomputers.

However, data replacement in 8280M is not easy. In other words, when writing new data into the 8280M, it is first necessary to erase the old data, but since this involves discharging all memory cells with ultraviolet rays, it takes a long time at the factory or center. I will do it. In addition, the new EFROM in which the early data was written is transferred to the old EP.
R (JM and EPl also require a lot of effort and time to replace in the OM usage environment. Especially when one product is scattered over a wide area, it becomes a huge amount of work and becomes a bottleneck in terms of service. It's possible.

E''PROM has appeared on the market as an attractive non-volatile memory that eliminates these drawbacks of the 8280M.

E2P OM has a structure similar to that of EPROM except for a part of the film thickness, but the gate oxide film above the drain is made thinner so that electron tunneling occurs in this part. This makes writing and erasing data easier. That is, erasing and writing are performed by changing the direction of the high electric field between the control gate and the drain. Therefore, there is no need to use ultraviolet light to erase old data, and data can now be replaced relatively easily in the field.

However, there is an upper limit to the number of times that 2FROM can be rewritten (approximately 104 to 10" times). This is because as the above-mentioned erasing and writing are repeated to replace data, electrons tunnel. This is caused by being captured by traps in the oxide film.

Captured electrons cannot escape under the electric field for erasing and writing, and the number of captured electrons increases rapidly, until finally enough electrons are accumulated to correspond to the erased state (electron capture level is charged state). This causes the data to become unwritable.

Conventionally, in order to prevent this type of EtF ROM from falling into the above-mentioned malfunction situation, the number of erasing and writing operations at the same address was predicted, and the actual number of erasing and writing operations reached the upper limit for one write. Before I could think of that, I had replaced E"FROM.

Such traditional, crude management does not guarantee that erasures and
Use U, B”F when you cannot accurately determine the number of writes.
There is a drawback that the ROM is replaced too quickly, resulting in waste, or, conversely, replaced too late, making it impossible to retain data.

An object of the present invention is to provide a nonvolatile semiconductor memory suitable for precisely performing this type of management.

The memory of the present invention is characterized in that the write instruction signals to the E''FROM are accumulated and stored in correspondence with the addresses of the B!FROM.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.
It is composed of a memory cell group 1, an address buffer 2, an output buffer 3, an adder circuit 3, and an erase/write control circuit 4. Memory cell group 1 consists of 2 words x 17 pits/
The word structure is E"FROM as described above.

The address buffer 2 buffers an address signal AD input from the outside and supplies it to the memory cell group 1.
The data at the specified address (according to the address signal ADRK) is read out to the output buffer 3 and the adder circuit 4. When the externally applied write enable signal WFi is at the logic level '1'', it means that a read operation is instructed, and the read data from the memory cell group 1 is buffered in the L output buffer 3 and read out to the outside. The data is output as data RDT. At this time, the adder circuit 4 and the erase/write control circuit 5 do not function.

Next, when the write enable signal WE is at logic "0", it means that an erase/write operation is instructed. In this case as well, the address signal AD
The address specified by H is read and the output buffer 7
and is input to the adder circuit 4. The read data output from the output buffer 3 to the outside is ignored at the receiving destination.

The read data input to the adder circuit 4 is incremented by 1 by the write enable signal WE, and then input to the erase/write control circuit 5 . The erase/write control circuit 5 first erases the data at the address of the read data input to the adder circuit 4 (designated by the address signal AD), and then writes the data input from the adder circuit. That is, the contents of the address specified by the address signal AD are incremented in response to the write enable signal WE.

FIG. 2 shows the embodiment shown in FIG. 1 (EtF ILOM
An example of the application of 10) is shown below. The center device 20 controls terminal devices (not shown) located at four remote locations, and simultaneously transmits programs and data (hereinafter simply referred to as data), and the terminal devices operate based on this data. Perform a predetermined action. Such an example can often be found, for example, in data communication systems between head offices and branches.

To keep important data safe, each terminal device
E'PROMtl, 12, 13 and 14 are provided. DIFROM1'l, 12.13 and 14 are of identical construction, have the same word address <2 as IfltPROMIO, and have the same memory cells. However, B
The number of characters per word in IFROMI 1.12.13 and 14 is determined by the data sent from the center device 20, and is not necessarily determined by Fl:lPROM1.
It is not the same as the number of bits in 0 (17). Still, E
The write data WDT in PIIOMII, 12.13 and 14 is data received from the center device 20, and is not data that can cause an increment operation like in the ROM10.

The address signal AD and write enable signal WE sent from the center device 20 to E"FROM II, 12, 13, and 14 are also sent to E"FROMlo provided corresponding to the center device 20. E"FROMx
At O, the same operation as previously described with respect to FIG. 1 is performed. That is, the address specified by the address signal ADR in 18"FROMlo is
The number of times that the corresponding addresses of itPROMll, 12, 13, and 14 are erased and written by the center device 20 is written and stored. The small number of bits per word of E"FROMIO, 17, is Fli!FROM11, 12.
Upper limit of number of times 13 and 14 can be rewritten 104 to 106
This is the number necessary to cover the

The number of rewrites stored in E”PROMtO is
The data is read out to the outside as read data DT in a timely manner,
Used as maintenance data for necessary countermeasures.

In place of the adder circuit 4 in the embodiment shown in FIG. 1, the read data from the memory cell group l is preset by the write enable signal WE, and the same write enable signal WIi3 is used by a delayed signal. It is also possible to easily realize an embodiment in which a counter is provided to count up preset read data.

In addition, in the embodiment described above, the memory cell group is E
It is composed of E"FROM, but if you install an auxiliary battery that operates during a power outage, you can replace E"FROM with regular R
An embodiment in which AM is substituted (RAM and auxiliary battery are considered as non-volatile memory) can also be realized very easily.

According to the present invention, by employing the above configuration, E”
It is possible to precisely manage the FROM replacement timing.

[Brief explanation of drawings]

FIG. 1 shows an embodiment of the present invention, and FIG. 2 shows an example of its application. 1...Memory cell group, 2...Address buffer, 3...Output buffer, 4...
・Kabu 1 circuit, 5... Erase/write control circuit, 10
, 11, 12, 13, 14... Read-only memo that can be electrically erased and written! Ji"280M, 20...
...Center equipment.

Claims (1)

[Claims] A nonvolatile semiconductor memory characterized in that a write instruction signal to an erasable/writable memory is accumulated and stored in correspondence with an address of the memory.