JPS607473A - Image expansion display system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to an image enlargement display method for enlarging and displaying a portion of both sides. The method p:r according to the present invention is used when displaying a screen having the same dimensions as a part of the screen of a large display device on a small display device.

Prior Art and Problems Conventional image enlargement display methods include a method in which a sub-area of 1F4 is displayed on a large screen and this sub-area is moved throughout the screen to grasp the entire image; A method is used in which a program cuts out 11n areas from a large screen and arranges them in 11fi order in a refresh memory. However, in the former case, although the area of interest is enlarged, it is difficult to grasp the entire area on one screen at once, and in the latter case, compression cannot be started until a certain amount of data has been reached by the program. Therefore, there is a problem in that it takes a long time to finish compression and display the area of interest, but it is difficult to easily change the area of interest.

OBJECT OF THE INVENTION The object of the present invention is to divide a large screen into an arbitrary number of small areas, and to provide a condition for compressing and displaying the part to be displayed in detail within these small areas, the peripheral part thereof, and the outside part thereof. To provide an image enlargement display method that is relatively fast and allows the entire image to be viewed at once by automatically displaying an area of interest in the same size as a large screen and compressing the surrounding area. There is a particular thing.

Structure of the Invention According to the present invention, in an art dealer enlargement display method in which a screen of the same size as a part of the screen of a large display device is displayed on a small display device, the large screen is divided into arbitrary small areas. 8+! controls the readout of image data for each small area on the data memory based on a data memory that stores image data and an area of interest that indicates a small area that is to be displayed on the same size as the large screen. 1 address control circuit, a pressure 4:i ili control circuit that determines the vertical and horizontal compression ratio of each small region based on the region of interest and outputs it as a pressure Xi:i condition, and a pressure A: 1: fljJ control circuit. An image 17 from the data memory based on the circuit compression conditions; a compression circuit that compresses the data and outputs the compressed data as 12; and a compression circuit that stores the compressed data according to the write address and displays it on the display as 11;
-f of the compressed data to be stored on the refresh memory based on the refresh memory and the area of interest and the area number of one extraction from the first address control circuit.
a second address control circuit for controlling the 1-inclusive address, and displays an arbitrary small area of the small areas obtained by dividing the large screen with dimensions equivalent to the large screen, and specifies other small areas. This is achieved by providing a single image enlargement display method that compresses and displays images based on the vertical and horizontal compression ratios.

Embodiment FIG. 1 is a block diagram of an apparatus for implementing the single image enlargement display method according to the present invention. In FIG. 1, 1 is a data memory for storing image data to be displayed,
ii! The data is divided into nXm small areas. This is divided into 5 x 5 small areas as shown in 5th Ti1l (a), for example, and each small area is given permissions from 1 to nIII. 2 is a positive t'+Fi lil path which compresses the image data S from the data memory 1 based on a predetermined compression ratio of B'i of a small area, and 3 is a path which compresses the compressed data from the compression circuit 2 by i$. It is a fresh memory that stores data according to the input address and generates 11 characters on the display 7. 4 is a first address control circuit that controls data reading for each small area on the data memory based on the input of the small area to be displayed (hereinafter referred to as the area of interest) on the large screen. , 5 is the vertical direction of each small region based on the region of interest, ) compression f! which determines the compression ratio of 1 and outputs the compression conditions. iil'1i111J1 and 6 is the 4'fr beat of refresh memory 3 based on the area of interest and; It is constituted by an address iii control circuit of UBA 2 that controls the write address. In such an IS'i configuration, at the beginning, the cursor,
The area of interest L'll can be selected using the keyboard or other input means.
For example, as shown in Figure 5 (h), t, r'-5 (
The small area 13 of a) is inputted to the first address control circuit 4 as the attention/area No. 18 S1, and the first address production circuit 4
Now, let's take a look at the 0-area signal S, which is manually applied to 7LZt, and the size of the small area being served, 1β, l, , 4J4. According to the number, the vertical address S2 and the horizontal address S,
Outputs / to the data memory, and at the same time outputs /J
悄・IIJ或jjjf, 1.1. , l L/1't ILi 1iGt area - does not indicate the latter (iM
No. S3 to the compression control circuit 5, region J, 7? , end signal 32
// is output to pressure A'hi 11jl F+' 2.

, compression 1iil insertion 1v circuit 5 with θ, Tsuji [1, IrI Castle Sengo Syu and the first address fii! I'm sorry 1. '6
Which small 1 (information on whether 41 formation is being sent out from 4)?
Based on , we already have K 4P I]E t1+t ) rl
R, OM > -1 Hi 1% Determine the longitudinal compression ratio and v' hair compression ratio of the 6 small ti (j area) by referring to the daple stored in the 1% compression ROM.

is sent to the compression circuit 2 under the pressure 1l4 condition of 1/. Compression circuit 2 outputs &J code memory 70
Image 14: Data s, , I, - and data pulses S, 1, first addressing system %'' 11 circuit 4 sends out small area star l-pulses, and compression control circuit 5 sends out pulses. Vertical compression ratio data S4 and horizontal compression ratio data 84' are input, and based on these signals, a known compression method such as a sampling method, an average value detection method, etc. is applied, and compressed data S6 and compressed data pulses 86' are output. On the other hand, the second address control circuit 6 receives the compressed data pulse 86' sent out from the compression circuit 2, and the attention area signal S0 and readout area number S3 sent out from the first address control circuit 4.
is input, extracts the vertical and horizontal start addresses of each small area based on the table already stored in the ROM, creates an address using a counter using this as the initial value, and stores this in the refresh memory 3. Output. The data created in the refresh memory 3 is output and displayed on the display 7.

FIG. 2 is a block diagram illustrating the first address control circuit shown in FIG. 1 in more detail. lr, r In Figure 2, when the attention/overhead signal S1 is input, each counter 21
．． 22 and 23 are initialized. There are three types of counters: counter 21 that counts 4'f'Il addresses;
, a counter 22 that counts vertical at 1/s. The number of small areas to be handled is determined by the counter 23 that counts the numbers. The address of each small 1-1h (is 4:l#i at the top left of the small area, 1', vertical 7P)
Each memory (R, (,1 & T)z
4.

25, and is added to the data from the counter in the power 1 intermediate units 210 and 211 to obtain the address data S, /
Memory 24.2! generates the hexagram and vertical ato1/s data s2 and sends it to the data memory l! The output of the counter 23 that counts the order of the small areas as the address of [
East will be destroyed. The count up is for the Hiiragi address every time data is read out one pixel at a time, and for the vertical address every time one line of data is completed, the small area count is 1 small area data.
, is performed every time it is discovered. This circuit is data memory 1
♀Division 1-diA tJ...1i (Stops after outputting data for only the area.

Figure 3 provides a more detailed explanation of the compression circuit shown in Figure 1.
11 is a block diagram of Rabbit, in 3E1, is the picture R output from data memory 1? ``Data S, O and data full J' are applied to the lateral force network V;
ii! Small area end signal s2 sent from control circuit 4//
and compression fli: 4 yellow pressure coarse hole signal 84' sent from the control circuit 5 is input. The output of the lateral compression circuit 31 is supplied to the row buffer address generation circuit 32 and the small 4.4 of the first address control circuit 4. The t1 area end information 3 is stored in the line buffer 33 based on //. Output vertical pressure of row buffer 33 #! It is input to the i4 circuit 34, and the vertical compression circuit 34
The data is compressed based on the vertical compression ratio data S4 of the compression control circuit 5, and outputted to the refresh memory 3 as data S6.

8:)4 Figure 1 shows the second address i port II shown in Figure 1.
FIG. 2 is a block diagram illustrating the 1a11 circuit in more detail. In FIG. 4, the first address control circuit 4, the attention area signals s, i- and the read 'PJl area number S3
Based on the table stored in advance in the memo (ROM) 41, the vertical and vertical start addresses 'is, a, and this'L of each small area are sent to the refresh address generation circuit 42, and the corresponding The refresh address generation circuit 42 uses a counter to create an address with this L as the initial value 7, refresh, no 1 - rear address S
7 and L7 are output. The compressed data pulse S4' is given by the timing r of the generation point τ'142)[1, f)+1
1.111L is the first address; l. Output 1.1 from the control circuit 4. / 7'j nail 1 thief i;'f Use signal S2//.

Figure 5 (a) at 21°C shows the large screen divided into 5 x 5 small Qtl areas as mentioned above, and is taken in November.
1 (b) to (g) each show an example of the compressed area on the inner side of -A and the small area that you want to focus on, e, p'1. 1 to 1:1L et al. published by Taku issue 1 or 2
Any odor at 5.4 can constitute a region of interest at 4 Cm and a compressed eTi region ('N Zl,.

Figure 6), (b) is the JT of Figure 5 (b) to (g)
- It is a figure showing the case of a coarse hole and a compression ratio of 1.1. :
', 'Go to Figure 45 (l・)・(rr), The difference between I- is that compression of areas other than the area of interest is performed uniformly, fortune-telling Ka・9, Kot1
- FIT, pressure 4Hfli', lnII'il path 5
One group of compressions;ノT'j' j:! You can execute t IJ 1. In this display, [IA combined figure 5 (hi) (E
) Tsuba Futami 0 pressure rum + 5 non-f' in jll area? '-p'
,l? , Σ becomes 41-7-38 at first glance, and display 1 (appropriate L2 Z) on page 1, etc. Depending on the application, the compression ratio in the pressure
``The display effect will also be improved.

Effects of the Invention According to the image enlargement display method according to the present invention, it is possible to compress and display the area of interest on the screen and its surrounding area, so it is possible to display a visually pleasing image without causing unnatural distortion on the screen. and can be displayed at high speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a device implementing an image enlargement display method as an embodiment of the present invention, FIG. 2 is a block diagram illustrating in more detail the first address control circuit shown in FIG. 1, and FIG. FIG. 4 is a block diagram explaining the second address control circuit shown in FIG. 1 in more detail. FIG. Figures 5(b) to 5(g) are diagrams showing regions, and Figures 5(b) to 5(g) are diagrams showing examples of digit formation of a small region to be a region of interest and a compressed region around it, and Figure 6(a)
), (b) is m showing an example of formation of a region of interest and a compressed region with a compression ratio different from that shown in FIGS. 5(b) to (g). ■...Data memory, 2...Compression circuit, 3...Refresh memory, 4...! T'; J address system fi
i1 circuit, 5...JIJ'a f! ,'! ll11
Circuit, (3-2a 27 P Res 1iil (i'l
li'l 975.7...Disgray device, 21
．． ．． 22.23...Counter, 24*25,4]...
・Memory, 2 (3g 2712 F (... specific recovery de 1;, 210, 211... addition circuit, 31... luster pressure, road circuit, 32 river bound] Guffa address departure/1; times)
δ, 3; row buffer, 34...vertical compression circuit, 12
...Riff 1/, Sure 1/S generation circuit. Patent Applicant: Fujitsu Limited 117 Representative Patent Attorney Akira Aoki Patent Attorney Kazuyuki Nishidate Patent Attorney 1) Sachi Kiri Patent Attorney ± 111 Akiyuki Kuchi Figure 5 (C1) (C) (b) (d) Figure 6 (a) (b)

Claims (1)

[Claims] 1. In an image enlargement display method that displays a screen of the same size as a part of the screen of a large display device on a small display device, a data memory that divides the large screen into arbitrary small areas and stores them as image data; a first address control circuit that controls the readout of image data for each small area on the data memory based on an attention area indicating a small area to be displayed with the same size as the screen; a compression control circuit that determines the horizontal and vertical compression ratio of a small area and outputs it as a compression condition; a compression circuit that compresses the image data from the data memory and outputs it as compressed data based on the compression condition from the compression control circuit; a fresh memory for storing and reproducing compressed data on a display according to a write address; and a write address for storing compressed data on the refresh memory based on the attention area and the read area number from the first address control circuit. fti' control circuit, and displays any small area of the small areas obtained by dividing the large screen into a size equivalent to that of the large screen, and displays other small areas in a predetermined length and width. An image enlargement display method characterized by compressed display based on a compression ratio.