JPS607169A - Cmos integrated circuit - Google Patents

Abstract

PURPOSE:To prevent latch up, by providing a specified parasitic thyristor, whose breakover voltage is lower than that of other thyristors and whose holding voltage is higher than a power source voltage. CONSTITUTION:In a plurality of parasitic thyristors accompanied by a CMOS integrated circuit, the breakover voltage of the specified parasitic thyristor, e.g., the thyristor accompanied by input and output circuits, is made lower than that of the other thyristors and its holding voltage is made higher than a power source voltage. In this way, the thyristor is operated against external noises in an overwhelming mode, the external noises are removed, and latch up does not occur. In order to reduce the breakover voltage smaller than the voltage in an inner circuit, a junction, at which guard rings 25 and 26 are contacted, is formed so that the breakdown voltage between a well and substrate in an input output substrate becomes low. In order to make the holding voltage large, the guard rings 25 and 26 are provided, and the emitter concentration of a parasitic bipolar transistor is reduced.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to a 0M transistor in which a p-channel transistor and an n-channel transistor are formed as a pair on the same silicon substrate.
The present invention relates to an integrated circuit that prevents latch-up of parasitic silicon risks in the integrated circuit due to O8 elements.

(Prior Art) OMOEi elements have excellent features such as low power consumption and a wide operating voltage range, and are widely used in large-scale integrated circuits. However, in the case of the 0MO8 element, when external noise is applied to the input or output terminal, abnormal current continues to flow, which is likely to cause a so-called latch-up phenomenon. This latch-up phenomenon is caused by a parasitic thyristor that occurs due to the structure of the CMOB element, and prevention of latch-up is an important design issue. The details of the latch-up phenomenon will be explained below with reference to the drawings.

FIG. 1 shows a schematic cross-sectional view of essential parts of an 0MO8 element.

In the figure, 1 is a p-type silicon substrate, 2 is an n-type well, 3 is a p+ type source region and a p+ type drain region of a p-channel transistor, and 4 is an n-type silicon substrate of an n-channel transistor.
+-type source region and n+-type drain region, 5 is n+ region for fixing well potential, 6 is p+ region for substrate grounding, V is power supply potential level, vBB is ground level, n is input terminal, Out is output terminal shows.

As can be seen from the figure, in the 0MO8 device, a Kp channel transistor and an n channel transistor are formed on the same silicon substrate, so the substrate, well, source region, drain region, guard ring region (not shown in the example in FIG. 1) ) npn and pnp type parasitic bipolar transistors are formed between impurity layers having different concentrations and conductivity types, and these parasitic bipolar transistors are connected to each other to generate a pnpn structure parasitic bipolar transistor.

FIG. 2 is an equivalent circuit diagram explaining this state. In the figure, Trl is a pnp parasitic bipolar transistor, and Tr! is an npn-type parasitic bipolar transistor, R8 is a substrate resistance between the substrate grounding p medium region 6 and the parasitic bipolar transistor Tr, Rw is the well potential fixing n+ region 5 and the parasitic bipolar transistor Tr,
is the well resistance between .

As seen in the figure, when a noise current flows for some reason, this is used as a trigger, and the emitter-base of the parasitic bipolar transistors Tr, , 'rr becomes forward biased, p, Trl. , Tr, when positive feedback is applied between them, the parasitic thyristor turns on.

FIG. 3 shows the current-voltage characteristics of the parasitic thyristor to explain this state. When a voltage higher than the breakdown voltage 71 is applied to the reverse-biased junction between the well and the substrate due to noise, and a current higher than - flows, the parasitic silicon risk is turned on, and the high resistance state 11 is transferred to the low resistance state 1xzK. The minimum voltage V that can maintain the turned-on state of the thyristor is called the holding voltage. If the holding voltage is lower than the power supply voltage, the turned-on state is maintained by the power supply, resulting in a latch-up state. On the other hand, if the holding voltage is higher than the power supply voltage, the turned-on state cannot be maintained by the power supply, so when the noise disappears, the normal state is restored.

When the elements are arranged in high density, the holding voltage becomes smaller than the normally used power supply voltage of 5V. For this reason, the conventional latch-up prevention method is to place a guard ring around the p-channel transistor and n-channel transistor in a highly doped region (guard ring) of the same conductivity type as the substrate or well in the input/output circuit part where high-voltage pulse noise occurs. RB shown in FIG.

~ is made small, making it difficult for forward bias to be applied between the emitter and base of the parasitic thyristor, and reducing the %p channel and n
Methods have been used to increase the holding voltage by increasing the interval between channel transistors to 100 μm or more, increasing the base length of the lateral parasitic bipolar transistor, and decreasing the current amplification factor α. However, in this method, there is no guard ring area due to high density, and the transistor spacing is small. Therefore, the breakover voltage (third □ in the figure V) are the same, there is a risk that the parasitic thyristor in the internal circuit will operate first, and there is a drawback that it is not a perfect latch-up prevention method. In addition, the input/output circuits occupy a large area, which has the disadvantage of hindering higher density.

On the other hand, a method is also used in which a junction diode is provided in the input/output circuit section and external noise is removed by destroying the junction diode. However, since the time required for the parasitic thyristor (5) to turn on is extremely short, there is a high possibility that the parasitic thyristor will turn on before the external noise is removed by destruction of the junction diode, making it difficult to prevent latch-up. The drawback was that it was not effective.

(Object of the Invention) The present invention has been proposed to solve the above-mentioned drawbacks, and its object is to provide an integrated circuit that completely prevents latch-up.

(Structure of the Invention) In order to achieve the above object, the present invention provides a method in which the breakover voltage of a particular parasitic thyristor is lower than the breakover voltage of other parasitic thyristors among a plurality of parasitic thyristors attached to a CMOS integrated circuit. The gist of the invention is a CMOS integrated circuit characterized in that the holding voltage of the specific parasitic silicon risk is higher than the power supply voltage.

In summary, the present invention provides an integrated circuit in which the breakover voltage of a specific parasitic thyristor is smaller than the breakover voltage of other parasitic thyristors, (6) and the holding voltage of the specific parasitic thyristor is lower than the power supply voltage. It is characterized by its large size.

Next, embodiments of the present invention will be described with reference to the accompanying drawings. It should be noted that the embodiments are merely illustrative, and it goes without saying that various changes and improvements may be made without departing from the spirit of the present invention.

The present invention operates preferentially against external noise and removes the external noise because the breakover voltage of the specific parasitic thyristor is small, and the holding voltage of the specific parasitic thyristor is lower than the power supply voltage. As a dog, the principle is to prevent latch-up. As is clear from the above description, the specific parasitic thyristor is preferably a parasitic thyristor attached to an input/output circuit portion. As mentioned above, the breakover voltage is determined by the junction breakdown voltage between the well and the substrate. Therefore, in order to make the breakover voltage of the parasitic thyristor of the input/output circuit smaller than that of the internal circuit, it is necessary to lower the breakdown voltage of the well-substrate junction of the input/output circuit.

A method for this purpose is to change the shape and degree of the bond. In order to easily lower the junction breakdown voltage, it is effective to form a junction in which high concentration regions are in contact with each other.

On the other hand, to increase the holding voltage, reduce the current amplification factor α of the parasitic bipolar transistor, increase the substrate resistance,
A method of reducing well resistance is known. Substrate resistance can be reduced by using a low resistance substrate or by applying a guard ring. Also, the well resistance R,
In order to reduce this, it is effective to increase the well concentration and increase the well depth. However, since the substrate concentration and well configuration depend on the device characteristics, it is difficult to change them significantly. On the other hand, K, which reduces the current amplification factor α of the parasitic bipolar transistor, can be achieved by increasing the effective base length or decreasing the emitter concentration of the parasitic bipolar transistor. Among these methods, the method of increasing the effective base length is that the horizontal parasitic bipolar transistor requires a large area;
Transistors have drawbacks such as the deep well depth and the long time it takes to form the well. From the above point of view, a method to increase the holding voltage is to provide a guard ring,
It is desirable to reduce the emitter concentration of parasitic bipolar transistors.

(Example) This will be explained below using examples.

FIG. 4 shows a schematic cross-sectional view of the main parts of the 0MO8 element of the example. FIG. 4(a) shows the input/output circuit portion, and FIG. 4(b) shows the internal circuit portion.

An n-type well 22 having a sheet resistance of 2.7 Ω and a depth of 1 μm was formed on a p-type silicon substrate 21 having a specific resistance of 3.7 Ω·m. The source/drain 23 of the p-channel transistor in the well is exposed to boron ions at 1X with an energy of 25 KeV.
It was formed by two ion implantations in a 10' dip.

On the other hand, the source/drain 24 of the n-channel transistor in the substrate is exposed to arsenic ions at an energy of 130 KeV.
It was formed by implanting ×1015/7M11 ions. The surface concentration of the source-drain 23 of the p-channel transistor is 6 x 10"/am", which is the commonly used 6 x 1
The concentration was set to be lower than 0"/F7+3. The source/drain 24 of the n-channel transistor (9) transistor had a surface concentration of 1.times.10" each with a value normally used. In the input/output circuit portion, guard rings 25 and 26 were provided around both the p-channel transistor and the n-channel transistor.

However, the two guard rings 25 and 26 were configured to partially contact each other. On the other hand, the internal circuit does not have a guard ring.
The distance between the channel transistor and the n-channel transistor was 22 μm. 27 and 28 are an n+ region for fixing the well potential and a p+ region for grounding the substrate, respectively.

The current amplification factor α of the vertical parasitic bipolar transistor whose emitter is the source/drain 23 of the low-concentration p-channel transistor is 0.6, which is extremely small compared to 0.999 K when a normal concentration is used. became. The parasitic thyristor characteristics are determined by the breakover voltage 23'7 in the input/output circuit. Holding voltage TV, breakover voltage 42v in internal circuit.

The holding voltage was 1.8v. The reason why the breakover voltage of the input/output circuit is smaller than that of the internal circuit is because the junction breakdown voltage at the guard ring contact portion is small.

(10) When the above circuit was operated with a power supply voltage of 5 V and various noises were input to the input/output terminals to check for latch-up, no latch-up occurred at all.

This is because, as mentioned above, the breakover voltage of the parasitic thyristor in the input/output circuit is smaller than that in the internal circuit.
This is because the parasitic thyristor in the input/output circuit operates preferentially and the holding voltage is greater than the power supply voltage of 5V, so the turned-on state of the thyristor cannot be maintained by the power supply. Furthermore, since external noise is removed by the high-speed operating parasitic thyristor in the input/output circuit, there is no risk that the parasitic thyristor in the internal circuit will operate.

In addition, since the guard ring spacing in the input/output circuit portion can be set to 0, high density can be achieved.

FIG. 5 shows the relationship between the holding voltage v2 and the source/drain concentration NA of the p-channel transistor. As is clear from the figure, the normal source/drain concentration is 6×10”/cr
If n'' is used, the holding voltage will be less than the power supply voltage VDD5V and latch-up will occur.The source/drain concentration IJ in order to make the holding voltage higher than the power supply voltage is 2 x 101s.
/crn3 or less, and 6xlO”/(77+
It is clear that the number is not limited to 3. A metal or silicide Schottky contact may be used instead of providing a source/drain region. It is also obvious that the technique of reducing the substrate resistance and well resistance and increasing the holding voltage as described above can also be used.

In the input/output circuit in the embodiment, the breakover voltage is lowered by bringing the guard rings into contact with each other, but a suitable impurity region may be provided separately or the shape of the junction may be controlled.

In the example, the source and drain of the p-channel transistor are made low in concentration, but the source and drain of the n-channel transistor are
Exactly the same effect can be obtained by lowering the concentration of the drain or both the source and drain.

Further, in the embodiment, an n-type well was used, but it is clear that the same effect can be obtained even if a p-type well is used.

(Effects of the Invention) As explained above, according to the present invention, a specific parasitic thyristor can be operated against external noise, and since the holding voltage of the specific parasitic thyristor is higher than the power supply voltage, Since latch-up does not occur, there is an advantage that latch-up of the CMO8 integrated circuit can be completely prevented. The particular parasitic thyristor also functions as a protection circuit against external noise, thereby eliminating the need for a conventional junction-based protection circuit. Furthermore, as described in the embodiment, n-channel
If the holding voltage can be made higher than the power supply voltage even if the distance between the transistor and the p-channel transistor is made sufficiently close, there is an advantage that circuit parts such as input/output circuits, which have not been able to be densified in the past, can be densified.

[Brief explanation of drawings]

Figure 1 is a cross-sectional view of the main parts of the 0MO8 element, Figure 2 is a sectional view of the 0MO8 element.
The equivalent circuit diagram of the element, FIG. 3 is the current-voltage characteristics of the parasitic thyristor, FIG. 4 is a sectional view of the main part showing an embodiment of the present invention, and FIG.
The figure shows the relationship between the holding voltage and the source/drain concentration of a p-channel transistor. (13) 1...p-type silicon substrate% 2...n-type well, 3...ga-type source region and gate-type drain region of p-channel transistor, 4...n+-type of n-channel transistor Source region and n+ type drain region, 5...
n1 region for fixing well potential, 6... p+ region for substrate grounding 21... p- type silicon substrate, 22... n- type well, 23... Ge-type source region of p-channel transistor and p+ type drain region, 24... n+ type source region and n+ type drain region of n-channel transistor, 27... n+ region for fixing well potential, 28...
The area for grounding the board is VD? )...power supply potential level, ■
88...Ground level, In...Input terminal, Out
...output terminal b'rr, ...pnp type parasitic bipolar transistor, Tr2...npn type parasitic bipolar transistor s Re...substrate resistance, ...
・Well resistance % vl... Breakdown voltage, ... Noise current % v2... Holding voltage, 25.26... Guard link % NA... Source/drain concentration of p-channel transistor Patent applicant Figure 1 Figure 5: Mouth (τ Figure 3 Figure 4

Claims (2)

[Claims] (1) Among multiple parasitic thyristors associated with a CMO8 integrated circuit, the breakover voltage of a specific parasitic thyristor is smaller than the breakover voltage of other parasitic thyristors, and the holding voltage of the specific parasitic thyristor is A CMO8 integrated circuit characterized in that the voltage is greater than the voltage. (2) The CMO according to claim 1, characterized in that in the parasitic thyristor with a constant 4I, the guard ring of the p-channel transistor and the guard ring of the n-channel transistor are at least partially in contact with each other.
8 integrated circuits.