JPS607139A - Bonding method - Google Patents
Bonding methodInfo
- Publication number
- JPS607139A JPS607139A JP11452683A JP11452683A JPS607139A JP S607139 A JPS607139 A JP S607139A JP 11452683 A JP11452683 A JP 11452683A JP 11452683 A JP11452683 A JP 11452683A JP S607139 A JPS607139 A JP S607139A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- bump
- bonding
- lead
- bumps
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、半導体チップ（以下チップと称す）のボンデ
ィングバット（以下パッドと称す）と基板電極（以下リ
ードと称す）を接続するボンディング方法に関するもの
である。[Detailed Description of the Invention] Industrial Application Field The present invention relates to a bonding method for connecting bonding butts (hereinafter referred to as pads) of a semiconductor chip (hereinafter referred to as chips) and substrate electrodes (hereinafter referred to as leads). be.
従来例の構成とその問題点
従来のボンディング方法は第１図に具体例を示すように
、３ｉ、Ｇｅ等のチ、ノブ１に素子間を接続し、外部へ
導出するだめのアルミニウム膜で形成された所望形状の
パッド２を設け、更にとの＜ン２ ・ −
ド２とチンプ１の表面を低温で形成されたＣＶＤＳｉ○
２ 膜３で覆い、前記パッド２の伺近のみをウェットエ
ツチングあるいはドライエツチングにより開孔し１次い
で例えばＣｒ、Ｃｕから成る２層膜４を真空蒸着法によ
り被着し、パッド２の部分のみ残し他を除去する。次い
で感光性樹脂等を用いて１０〜１５μ７７Ｉの高さにＡ
ｕ、半田等の金属を電着せしめ、バンプ５を形成させる
。一方リード６はポリイミドを補強材としてＣｕ箔Ｔ上
にＳｎ又はＡｕ メッキ層８を形成したもので、このリ
ード６の図示せざる一方の端部は他の電子回路に接続さ
れるものとする。上述のバンプ５とリード６とを熱圧着
等の方法によりボンディングしていた。Structure of the conventional example and its problems The conventional bonding method, as shown in a specific example in Fig. 1, connects the elements to the knob 1 with 3i, Ge, etc., and is formed with an aluminum film that is not exposed to the outside. A pad 2 having a desired shape is provided, and the surfaces of the pad 2 and chimp 1 are coated with CVDSi○ formed at a low temperature.
2 Cover with a film 3, open a hole only in the vicinity of the pad 2 by wet etching or dry etching, and then apply a two-layer film 4 made of, for example, Cr and Cu by vacuum evaporation, leaving only the part of the pad 2. remove others. Then, using a photosensitive resin etc., A
u, metal such as solder is electrodeposited to form bumps 5. On the other hand, the lead 6 is formed by forming a Sn or Au plating layer 8 on a Cu foil T using polyimide as a reinforcing material, and one end (not shown) of this lead 6 is connected to another electronic circuit. The bumps 5 and leads 6 described above were bonded by a method such as thermocompression bonding.
しかしながら上記のような方法では、チップ上にバンプ
を形成する工程において、バンプの形成速度が小さく、
所定の厚さのバンプを形成するのにかなりの時間を要し
、工程時間が長くなる。またチップが長時間にわたり加
熱、エツチングその他バンプ形成のための各種工程を経
ることにより、３゜
チップの性能に悪影響が及ぶという欠点を有していた。However, in the above method, the bump formation speed is slow in the process of forming bumps on the chip.
It takes a considerable amount of time to form bumps of a predetermined thickness, increasing process time. Another drawback is that the performance of the 3° chip is adversely affected because the chip undergoes heating, etching, and other various steps for forming bumps over a long period of time.
発明の目的 本発明は上記欠点に鑑み、工程時間を短縮し。Purpose of invention In view of the above drawbacks, the present invention shortens the process time.
寸たチップの性能劣化が少ないボンディング方法を提供
するものである。The present invention provides a bonding method that causes less deterioration in performance of small chips.
発明の構成
本発明は、バンプをリード−Ｈの所定位置に形成し、リ
ートにのバンプブにチンツブをボンディングすることか
ら構成されており、バンプ形成工程をボンディング工程
と別ラインに設け、バンプ形成をボンディング工程と並
行して行うことにより、工程時間を短縮でき、斗た加熱
、エツチングその他バンブ形成の各種工程はリードに対
して行われるだめ、チップがボンディング工程を経るこ
とにより発生するチップの性能劣化が少ないという特有
の効果を有する。Structure of the Invention The present invention consists of forming a bump at a predetermined position on the lead H, and bonding a bump to a bump on the lead.The bump forming process is provided on a separate line from the bonding process, and the bump forming process is By performing this process in parallel with the bonding process, the process time can be shortened, and heating, etching, and other processes for forming bumps are not performed on the leads, thereby reducing the performance deterioration of the chip that occurs when the chip goes through the bonding process. It has the unique effect of reducing
実施例の説明
以下本発明の一実施例について、図面を参照しながら説
明する。DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.
第２図は本発明の一実施例におけるボンディング方法の
工程順を示すものである。FIG. 2 shows the process order of the bonding method in one embodiment of the present invention.
（ａ） Ｓｉ基板９上のチタン・パラジウム膜１０」二
に形成されたＡｕバンプ１１をリード１２に熱圧着工具
１３により熱圧着する。(a) The Au bumps 11 formed on the titanium-palladium film 10'' on the Si substrate 9 are thermocompression bonded to the leads 12 using a thermocompression bonding tool 13.
（ｂｌ） Ａｕバンプ１１をリード１２に転写する。(bl) Transfer the Au bumps 11 to the leads 12.
（ｃ）Ｓｉチップ１３のパッド１４を上記Ａｕバンプ１
１の上方に移送する。(c) The pad 14 of the Si chip 13 is connected to the Au bump 1
1 above.
（ｄ） Ｓｉ チップ１３上のバント１４を上記バンプ
１１にボンディングする。(d) Bonding the bunt 14 on the Si chip 13 to the bump 11.
以上のように本実施例によれば、バンプをチ。As described above, according to the present embodiment, the bumps are removed.
プ上でなくリード上に形成することにより、工程時間を
短縮でき、捷たチップの性能劣化が少ない。By forming the chip on the lead rather than on the chip, the process time can be shortened and the performance of the chip is less likely to deteriorate.
発明の効果
以」二のように本発明は、バンプ材料とリード材料との
結合力よりもバンプ材料との結合力の弱い材料の上に形
成したバンプをリードに転写し、前記リードをチップに
ボンディングすることにより。Effects of the Invention As described in 2., the present invention transfers bumps formed on a material whose bonding force with the bump material is weaker than the bonding force between the bump material and the lead material to a lead, and transfers the said lead to a chip. By bonding.
工程時間を短縮し、またチップの性能劣化を少なくする
のに有効であり、その実用的効果は犬なる６／、 −
ものがある。It is effective in shortening process time and reducing chip performance deterioration, and its practical effects are significant.
第１図は従来のボンディング装置の断面図、第２図（ａ
）〜（ｄ）は本発明の一実施例におけるボンディング装
置の各工程における断面図である。
１．１３ ・・チップ、２，１４・・・・パッド、５．
１１ ・ ・バンプ、６．１２・・・・・ＩＪ −ト。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名第１
図Figure 1 is a sectional view of a conventional bonding device, and Figure 2 (a
) to (d) are cross-sectional views at each step of the bonding apparatus in an embodiment of the present invention. 1.13...chip, 2,14...pad, 5.
11. ・Bump, 6.12...IJ-to. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
figure
Claims (1)
との結合力の弱い材料の」二に形成し７たバンプを基板
電極に転写し、基板電極上の前記バンプに半導体チップ
をボンディングするボンディング方法。Bonding in which bumps formed on a material whose bonding force with the bump material is weaker than the bonding force between the bump material and the substrate electrode material are transferred to the substrate electrode, and a semiconductor chip is bonded to the bumps on the substrate electrode. Method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11452683A JPS607139A (en) | 1983-06-24 | 1983-06-24 | Bonding method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11452683A JPS607139A (en) | 1983-06-24 | 1983-06-24 | Bonding method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS607139A true JPS607139A (en) | 1985-01-14 |
Family
ID=14639954
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11452683A Pending JPS607139A (en) | 1983-06-24 | 1983-06-24 | Bonding method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS607139A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01146337A (en) * | 1987-12-03 | 1989-06-08 | Matsushita Electric Ind Co Ltd | Assembling method for semiconductor |
| JPH01149569U (en) * | 1988-04-08 | 1989-10-17 | ||
| JPH03120736A (en) * | 1989-10-03 | 1991-05-22 | Matsushita Electric Ind Co Ltd | Semiconductor device |
| US6077725A (en) * | 1992-09-03 | 2000-06-20 | Lucent Technologies Inc | Method for assembling multichip modules |
-
1983
- 1983-06-24 JP JP11452683A patent/JPS607139A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01146337A (en) * | 1987-12-03 | 1989-06-08 | Matsushita Electric Ind Co Ltd | Assembling method for semiconductor |
| JPH01149569U (en) * | 1988-04-08 | 1989-10-17 | ||
| JPH03120736A (en) * | 1989-10-03 | 1991-05-22 | Matsushita Electric Ind Co Ltd | Semiconductor device |
| US6077725A (en) * | 1992-09-03 | 2000-06-20 | Lucent Technologies Inc | Method for assembling multichip modules |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4494688A (en) | Method of connecting metal leads with electrodes of semiconductor device and metal lead therefore | |
| JPH04326534A (en) | Chip bonding method of semiconductor device | |
| JPH11238763A (en) | Manufacture of wiring board for mounting semiconductor element | |
| JPH0322437A (en) | Manufacture of semiconductor device | |
| JPH10163401A (en) | Lead frame, semiconductor package, and manufacture of semiconductor package | |
| JPS607139A (en) | Bonding method | |
| JP2811741B2 (en) | Method for manufacturing semiconductor device | |
| JPH03101234A (en) | Manufacture of semiconductor device | |
| JP2721580B2 (en) | Method for manufacturing semiconductor device | |
| JP3267422B2 (en) | Bump transfer body and method of manufacturing semiconductor integrated circuit device | |
| JPS5824014B2 (en) | Manufacturing method of mounting body | |
| JP2734585B2 (en) | Method for manufacturing semiconductor device | |
| JPH11163019A (en) | Semiconductor device and manufacturing method thereof | |
| JPH0793329B2 (en) | How to fix semiconductor pellets | |
| JPS61225839A (en) | Forming method for bump electrode | |
| JP2002237500A (en) | Manufacturing method of semiconductor device | |
| JPH0350734A (en) | Integrated circuit manufacturing method | |
| JPH0715909B2 (en) | Method for manufacturing semiconductor device | |
| JPH02232947A (en) | Semiconductor integrated circuit device and mounting thereof | |
| JPH0595027A (en) | Flexible circuit board forming method | |
| JPH01136354A (en) | Semiconductor device | |
| JPH05109734A (en) | Semiconductor device and method of manufacturing semiconductor device | |
| JPH10242367A (en) | Semiconductor device and manufacturing method thereof | |
| JPS5815254A (en) | Manufacture of semiconductor element | |
| JPS61260648A (en) | Packaging method for semiconductor device |