JPS6059777A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable to simultaneously form a shallow source and drain region and a low diffused resistor and to perform a high density and high speed integrated circuit by forming an insulating film on the side of a gate electrode, and forming a diffused region much deeper than the source and drain diffused region with the gate electrode and the film as masks. CONSTITUTION:With a gate electrode 3 as a mask source and drain diffused regions 4, 5 which have N type conductive type are formed shallowly by ion implantation technique. A fluid silica film film 6 is formed on the overall surface, a silica film film 6 of the prescribed thickness is then removed on the overall surface, and silica films 6a, 6b inclined to the side of the electrode 3 remain. Then, with the electrode 3 and the films 6a, 6b as masks deep diffused regions 7, 8 which have an expanse in the depthwise direction of the ion implanted layer proportional in the thickness to the inclined films 6a, 6b are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a self-aligned MO8 (metal oxide semiconductor) semiconductor device.

A method of manufacturing a self-aligned MO8 semiconductor device, typified by a silicon silicon MO8 semiconductor device, involves forming a gate electrode on a semiconductor substrate, and then using this gate electrode as a mask to form a source and a drain. For this reason, an MO8 semiconductor device with less overlap between the gate electrode and the source/drain region, and therefore a small capacitance due to the overlap, can be realized and is widely used.

Recently, there has been a demand for high-density MO8 integrated circuits with short channel lengths, and by forming the source/drain more shallowly using ion implantation, etc., the overlap between the gate Ijt pole and the source/drain region can be further reduced. Technology has been put into practical use.

However, when forming the source/drain shallowly, the diffusion resistance can be reduced by forming the source/drain shallower. It is expensive, which is disadvantageous for speeding up the kL GC circuit.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that simultaneously realizes the contradictory elements of shallow source/drain regions and low diffusion resistance and is suitable for high-density and high-speed integrated circuits.

The present invention includes a step of forming a gate electrode on a semiconductor substrate via a gate insulating film, a step of forming a source-drain diffusion region using the gate electrode as a mask, and a step of forming an insulating film on the side surface of the gate electrode. and a step of forming a diffusion region deeper than the source/drain diffusion region using the gate polarization and the insulating film as a mask. .

Next, the present invention will be explained in detail with reference to the drawings. 1st
4 to 4 are cross-sectional views showing a method of manufacturing a semiconductor (4=device) according to an embodiment of the present invention in the order of steps.

First, a gate oxide film 2 is formed on a P-type nest crystal silicon substrate 1 in the same manner as in the manufacturing method of a conventional N-channel silicon MOS transistor, and then a gate 1Fc made of polycrystalline silicon ( The gate electrode 3 is selectively formed. Here, the gate electrode 3 is often doped with an impurity of N in advance. Next, using the gate electrode 3 as a mask, it is implanted using ion implantation technology. , 8M conductivity source/drain diffusion regions 4 and 5 are formed shallowly (FIG. 1).

Next, a fluid silica film 6 is formed on the entire surface to make the surface flat (FIG. 2). ) 111 Silica・
Instead of the film 6, a silicon oxide film containing phosphorus may be heat treated to make the surface flat in the same way.

Next, silica film j14 with a prescribed paste is applied to the entire surface!
6 is removed to leave inclined fucosilica films 196a and 6b on the side surfaces of the gate electrode 3 (FIG. 3).

As a method for removing the silica film 6 to a predetermined thickness, anisotropic dry etching such as reactive ion etching is often used because of its good control.

Next, using the gate electrode 3 and the remaining inclined silica film films 6a and 6b as a mask, the previously formed source/drain regions 4, 5. High JW and deep diffusion regions 7, 8 fully formed l~, N channel silicon gate Mos
Complete the transistor (Figure 4).

At this time, if ion implantation technology is used, the graded silica
a deep diffusion region 7 in which the ion implantation layer extends in the depth direction in proportion to the thickness of the mask of the film membranes 5a, 5b;
8 can be formed.

Therefore, even if the thickness of the silica film 6 to be removed is somewhat large, the overlap between the deep diffusion regions 7 and 8 and the gate electrode 3 is so small that it can be ignored.

The sloped silica film films 5a and 5b on the side surfaces of the gate electrode 3 can be left as they are and used as part of the interlayer insulating film with the upper wiring layer, and as a result, this is very advantageous in reducing the step difference.

According to the present invention, as described above, the child length is short,
In addition, the overlap between the gate electrode and the source/drain region is small, and a high-density, high-speed integrated circuit having an fviOs transistor with low diffusion resistance can be realized.

Note that the present invention is not limited to the N-channel silicon MO8 semiconductor device as in the above embodiment,
It can also be applied to C-MOS silicon gate semiconductor devices, and M can also be used as the material for the gate electrode. (Molybdenum) and W
Metals such as tungsten (tungsten), bonding films such as ferrite oxide crotch, etc. can be widely applied.

[Brief explanation of the drawing]

1 to 4 are cross-sectional views showing a method for manufacturing a semiconductor package according to an embodiment of the present invention in the order of steps. In the plan view, 1... silicon substrate, 2...
...Gate oxide film, 3...Gate electrode, 4,
5... Source/drain diffusion region, 6.6a,
(ib......to silica film Ii, 7,8-
...rKk diffusion area. Agent: Patent attorney Hi Uchihara, ＼：

Claims (1)

[Claims] a step of forming a gate electrode on a semiconductor substrate via a gate insulating film; a step of forming a source/drain diffusion region using the gate electrode as a mask; a step of forming an insulating film on the side surface of the gate electrode; A method for manufacturing a semiconductor device, comprising the step of forming a diffusion region deeper than the source/drain diffusion region using the gate electrode and the insulating film as a mask.