JPS6059599A - Non-volatile semiconductor memory - Google Patents

Abstract

PURPOSE:To test a manufactured non-volatile semiconductor memory and to obtain the high reliability of the device by forming a testing circuit consisting of dummy cell groups connected to row/column lines selected only at the testing time and a peripheral circuit selecting the dummy cell groups. CONSTITUTION:The testing circuit including a row dummy cell group selecting means consisting of row dummy cell groups 23, 24 to be driven by row lines selected only at the testing time, dummy row decoders 20, 21 selecting the cell groups 23, 24 and a testing row address buffer 18, and a column dummy cell group selecting means consisting of a column dummy cell group 25 connected to a column line selected only at the testing time and formed in one column every I/O bit, a dummy column selector 22 selecting the cell group 25, a dummy column decoder 19, and a testing column address buffer 17 is formed. Thus, information is inputted/outputted to/from a memory cell matrix 16 on the basis of address inputs A0-Am.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a non-volatile semiconductor memory, and more particularly to a non-volatile semiconductor memory whose memory contents can be erased by ultraviolet irradiation or the like.

[Prior art]

In recent years, with the rapid development of microcomputers, read-only memory (hereinafter referred to as R
It's called OM. ). ROM has a relatively simple structure, high degree of integration, low cost, and does not have a write function.
Even if there is, it is a memory that may have lower performance than random access memory.

The most basic type of ROM stores information in mask patterns used in the IC manufacturing process, and is called a mask ROM. Although it is impossible to change the memory contents, the reliability of writing and the stability of storage are very good, and when making large quantities of the same memory contents, the cost is low, but it is not possible to change the memory contents in small quantities. It is not suitable for use as a product, and it takes a considerable amount of time from the time the pattern information is obtained from the user until it becomes a product.

On the other hand, a ROM in which the user can freely write the memory contents in the field is a programmable ROM, and in the present invention, the non-volatile semiconductor memory IJ (1'J, lower EP -ROM) is one type of this type. EPROM requires a special package for ultraviolet irradiation, and has the drawback of being more expensive than ROM. However, it has excellent usability in the field and has formed a large market.

By the way, it is known that the storage stability of EPROM, that is, the retention characteristic after information is written, is extremely good, and that it can be used as a sufficient substitute for ROM.

Therefore, instead of using a special package, we use a package similar to a ROM, such as a plastic package, which eliminates the need to erase the memory contents and is used only for one-time writing.In addition to using a large number of products, we can However, the unit price is extremely low, and it is convenient in the field.
EPRO may take a short period of time for users to obtain all products.
M (hereinafter referred to as one-write lPROM) was considered. However, in this case, the function of the product as a product is checked only when the wafer is in the state before assembly, and after assembly, the check is limited to the state where no data is stored. Although the unit price is low, there is a high proportion of products that cause data write failure by users.Also, it is not possible to sufficiently check the normal data read time, so-called access time.

Figure N1 is a block diagram showing the configuration of an example of a conventional EPROM. This conventional example has an input/output 8-bit configuration, and the input/output of information to the memory cell matrix 6 is controlled by the input/output controller by the selection of the column decoder 2 and row decoder 3 using the address inputs A to Arn. : Done through. In the figure, 5 is a column selector, and C is a control signal, convex. ~6. is the input/output data signal.

In this configuration, a check function to check the function of KFROM is not added, so as mentioned above, the function of the product can only be checked with a probe in the wet state, and sufficient checks cannot be performed after assembly. [Objective of the Invention] An object of the present invention is to provide a high-yield, highly reliable non-volatile semiconductor memory equipped with a test circuit by eliminating the above-mentioned drawbacks. [Structure of the Invention] The nonvolatile semiconductor memory of the present invention includes a plurality of row dummy cell groups driven by row lines selected only during testing;
A row dummy cell group selection means for selecting the row dummy cell group, a column dummy cell group connected to a column line selected only during testing and provided for each input/output bit in at least one column, and a column for selecting the column dummy cell group. and die-cell group selection means.

[Explanation of Examples]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention. Note that this diagram shows an IP that consists of 2 bits of input and output.
6 is shown for one bit of ROM.

In this embodiment, two row dummy cell groups 23.24 are driven by row lines that are selected only during testing, and the row dummy cell groups 23.24 are connected to column lines that are selected only during testing. , a column dummy cell group 25 provided in one column for each person's output, and this column dummy cell group 25'f.
t-selecting dummy column group selection means. In this embodiment, address manual A is used. From A to A, selection of the column decoder 12 and row decoder 13 (memory cell), input/output of information to the +7x 16 is performed by the input/output controller 11 via the output cover 7a 14. In the figure, 15 is a column selector, C is a control signal, and 'oz is an input/output data signal. Figures 3 through 8 are partial detailed circuit diagrams for explaining the operation of this embodiment. , FIG. 3 shows the row dummy cell group, FIG. 4 shows the column dummy cell group and dummy column selector, FIG. 5 shows the row decoder, FIG. 6 shows the column decoder, FIG. 7 shows all the dummy row decoders, and FIG. The figures each show a dummy column decoder.

Next, the operation of this embodiment will be explained with reference to these figures.

In FIG. 2, the test column address buffer (BY) 17
is the address input A to the column decoder 12. When a certain voltage higher than the power supply voltage is input to An from An, the dummy column decoder 19 is activated and all column decoders 12 are deselected.
When a certain voltage higher than the power supply voltage is input to A from +1 to A□, the dummy row decoder 20.21
is activated, the row decoder 13 outputs a signal DAX and its inverted signal Dx such that all are unselected.

Now, consider a state in which a high voltage is input to the address input Arn and the dummy row decoders 20 and 21 are activated. In FIG. 2, two dummy row decoders are arranged, and one of them is selected by address input An+1. Cell groups 23 and 24 driven by the row line selected by the dummy row decoder 20 and 21 are arranged to sandwich the memory cell matrix 16.

FIG. 3 is a circuit diagram of the row dummy cell groups 23 and 24 shown in FIG. Memo consisting of M -M Yu - DM u -DM for Recell Matrix 16
l)' and H DM□ to DMly are - cell group 23
．． 24 are arranged at both ends. Now, assume that the column lines d11 of columns ado to d are selected by the column decoder 12. Column line d11 includes memory cells M3. ~M
The sources (or drains) of cells DMss and DM□ are commonly connected to each other. Further, each drain (or source) is commonly connected to the ground potential G, and a row line which is an output of the row decoder 13 or the dummy row decoder 20.9-21 is connected to their control gates. In normal use, the dummy cells DMII and DNli2I are ignored, and only the memory cells Mll to MX operate.

FL: When used as FROM, MI
The memory cells 1 to Mxl are in an erased state, and in read-only checking, the level of column line dll is always checked only at a constant level. Additionally, write function checks are completely ignored. Therefore, DMu.

The dummy cells of DM□ are used to check the function at the time of writing and continuous output, and at least two dummy cells for the column line dig are used to check the functions of DM, 1. By writing and reading contradictory data to DM and l, it is also possible to check the adverse effect that any defect in the memory cells from MH to MXi has on the column line d□.

Also, between the column lines dll and d□, the dummy cell DM
By writing contradictory data to u and 0M1, DMII and DMo, it is possible to check for short circuits between the column lines dll and d□, and at the same time, it is also possible to check the circuit function of the column decoder system.

Next, consider a state in which a high voltage is input to the address input An and the 10-dummy column f coder 19 becomes active. In FIG. 2, one dummy column decoder 19 is arranged, and the column dummy cell group 25 driven by the column line selected by this dummy column decoder 19 is arranged in one column at one end of the memory cell matrix 16. .

FIG. 4 is a circuit diagram of the column dummy cell group shown in FIG. 2. Output X1 of the row decoder 13. dummy memory cell DM selected by Xlx from
A group of column cells 25 are arranged in one row at one end of the memory cell matrix 16.

The source (or drain) of each cell in this column dummy cell group 25 is connected to the column line Dd selected by the dummy column decoder 19, and the drain (or source) of each cell is connected to the ground potential GIC! The control gates of the cells are connected to the output of the row decoder 13. Normally, one of the column lines d to dy is selected by the transistors Q, -Qy forming the column selector 15 according to the column decoder outputs Y11 to Y1y, and data is input and output. in this case,
The dummy cells DM1 to DMX connected to the column line Dd are
Since the output DY of the dummy column decoder 19 is not outputted to the gate of the transistor Qd forming the dummy column selector, it is ignored and not used. One light E3FROM
When used as a memory cell, the memory cell matrix 16 is all in an erased state, selected by the output of the row decoder 13, and the output data is read out only at a constant value in any case. Therefore, it is not possible to sufficiently check whether the row decoder 13 is operating normally or whether there is a short circuit between row decoder outputs. Therefore, the output D of the dummy column decoder 19
By setting Y to 1H" level, data is written to and read from the column dummy cells DM, to DMx connected to the column line Dd, thereby making it possible to check between the row decoder 13 and its output. By arranging at least one column of the column dummy cell group 25 selected by the dummy column decoder 19 for each input/output bit, it is possible to efficiently check the function by combining the data of each output bit. If the input/output is 2 bits, two columns of dummy cell groups are provided.

FIG. 5 is a circuit diagram of an example of the row decoder of the embodiment shown in FIG. 2.

In FIG. 5, number 26 is the row decoder output puffer. When the output DAX from the test row address buffer 18 shown in FIG. 2 is at the 1H# level, the row decoder becomes unselected because the transistor QDX is turned on, and enters the test mode. Therefore, the output DAX is normally "L" level.

FIG. 6 is a circuit diagram of column decoder 120. In FIG. 6, 27 is a column decoder output pad 7a. When the output DAY of the test column address buffer 17 is at the 1'' level, the transistor QDY is turned on, so the column decoder is not selected] and the test mode is entered. Therefore, normally the output 6' is "L". level.

7 and 8 are circuit diagrams of dummy row decoders 20, 21 and dummy column decoders 19.

13- The outputs DAX and DAY of the test row address buffer 18 and the test column address buffer 17 are normally both “H#”.
However, when the outputs DAX and DAY become "L" level in the test mode, the output corresponding to the address input is selected.

In FIG. 8, since the dummy cell group 25 in FIG. 2 is in one column, there is no address input, but if two or more columns are provided, selection can be made by address input as in FIG. Note that 28 and 29 are a dummy row decoder output buffer and a dummy column decoder output buffer, respectively.

Although the above embodiment has been described with respect to an N-channel type EPROM, it goes without saying that the same can be applied to a P-channel type and a CMO8 type lPROM.

〔Effect of the invention〕

As described above in detail, the nonvolatile semiconductor memory of the present invention includes a test circuit consisting of a dummy cell group connected to row lines and column lines that are selected only during testing, and a peripheral circuit that selects the dummy cells. Therefore, 14- It is possible to sufficiently test the product even after it has been commercialized.
If a non-volatile semiconductor memory whose memory contents can be erased (by high-speed, highly reliable ultraviolet irradiation, etc.) can be obtained, it will have an intoxicating effect.
The effect is particularly effective when applied to M.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an example of a conventional nonvolatile semiconductor memory, FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention, and FIGS. In the partial detailed circuit diagram of Figure 2, the third factor is the row dummy cell group, Figure 4 is the column dummy cell group and dummy column selector, Figure 5 is the row decoder, Figure 6 is the column decoder, and Figure 7 is the row dummy cell group. FIG. 8 is a detailed circuit diagram of the dummy row decoder. 1... Input/output controller, 2... Column decoder, 3... Row decoder, 4...
Input/output buffer, 5...Column selector, 6...
...-Memory cell matrix, 11... Input/output controller, 12... Group/column decoder, ]3...
... Row decoder, 14 ... River input/output buffer, 15
... Column selector, 16 ... Memory cell matrix, ]7 ... Test column address buffer (BY), 18 ... Test row address buffer ( BX), 19...Dummy column decoder, 2
0.21...Dummy row decoder, 22...Group...
Dummy column selector, 23.24...Row Dan cell, 25...Column dummy cell, 26...
Row decoder output buffer, 27 Old... Column decoder output buffer, 28... Dummy row decoder output buffer, 29... Dummy column decoder output buffer %A o, A-...・Address input, C...
- Control signal, 00-01. Oz...Input/output data signal, X11-X1K...Row decoder output signal, Yll-Y1y...Column decoder output signal, DXl, DX,...Dummy Row decoder output signal, DY,...Dummy column decoder output signal, Ml
, ~Mxy...Memory cell, DM11~DM,
, DM□~DMEy, DMI~DM,...D
AX, DAX, DAY, DAY...Test address buffer output, vo. ······Power-supply voltage,
G...Ground potential%Q* ・Qtue Q y e
Q(1# Q Bz * QDY *Qdx・Qdy
...N-channel MO8) transistor. 17-3 Figure 1, Figure 4, Figure 6, Garden 7, Figure 8

Claims (1)

[Scope of Claims] (1) A plurality of row dummy cell groups driven by row lines selected only during testing, row dummy cell group selection means for selecting all of the row dummy cell groups, and column lines selected only during testing. 1. A nonvolatile semiconductor memory comprising: a column dummy cell group connected to a column and provided in at least one column for each input/output bit; and column dummy cell group selection means for selecting the column dummy cell group. (Claim (1) in which the two dummy cells are insulated gate field effect transistors having a floating gate structure)
Non-volatile semiconductor memory as described in Section. (3) A plurality of dummy row decoders that select a plurality of row dummy cell groups, and a predetermined dummy row decoder that selects a row line when a predetermined voltage higher than the power supply voltage is input to at least one of the address inputs that select a row line. A row dummy cell group selection means consisting of a test row address buffer that selects and unselects the entire row decoder, a dummy column selector and a dummy column decoder that selects a column dummy cell group, and at least an address input that selects a column line. A column dummy cell group selection means comprising a test column address buffer that selects a predetermined dummy column decoder and deselects the entire column decoder when a predetermined voltage higher than the power supply voltage is inputted to the test device. A nonvolatile semiconductor memory according to scope (1). (4) A patent claim having a test row address buffer and a test column address buffer whose output signals are inverted when a predetermined voltage higher than the power supply voltage is input to the address input for selecting a row line and a column line. Non-volatile semiconductor memory described in item (3) within the scope of ◎