JPS6057731A - Two-way simultaneous communication method - Google Patents

Abstract

PURPOSE:To attain transmission and reception in time division efficiently in- dependently of a distance between an own station and an opposite station by measuring in advance a delay time required for a signal transmitted from the own station to the opposite station and deciding the proper period of transmission/reception from the delay time. CONSTITUTION:A measured pulse signal is transmitted from a delay time measuring circuit 11 to the opposite station, a response pulse signal is received by the circuit 11 and the delay time is obtained by measuring the time from the measured pulse signal transmission to the response pulse reception. A transmission/ reception control circuit 12 generates a pulse in the period obtained by dividing the delay time with a suitable integer N and since the flow of signal is interrupted and becomes discontinuous, the signal is transmitted while being subject to time axis compression by a time axis compression circuit 13 to avoid the discontinuity, and the reception side applies time axis expansion by a time axis expansion circuit 14 and extracts the original signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a two-way simultaneous communication system performed between a local station and a partner station.

[Background of the invention]

In recent years, microphones have been used as a means of transmitting information over short distances.
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It is being considered that this technology can be applied to teleconferences and teleconferences, but in the case of the latter, simultaneous communication is required in addition to bidirectional communication.

FIG. 1 shows a circuit configuration of a conventional general two-way simultaneous communication system in a pull-out diagram. Figure (a) shows a system using two antennas, which consists of an FM modulation circuit 1 that inputs a low frequency signal and outputs it as an FM modulated wave, and an up converter 2 that converts the output of the FM modulated wave to a high frequency. A transmitting antenna 7 and a receiving section 6 each include a transmitting section 3, a down converter 4 that inputs a high frequency FM modulated wave and converts the frequency to a low frequency, and a demodulating circuit 5 that demodulates the low frequency FM signal. It is equipped with an antenna 8.

The method shown in FIG. 2(b) uses one antenna for transmission and reception, in which the output of upconverter 2 is transmitted from antenna 10 through circulator 9, and antenna 1
The high frequency signal received at 0 is input to the down converter 4 through the circulator 9, and even if transmission and reception are performed at the same time, the transmitted signal and the received signal are separated by the circulator 9.

However, in such conventional communication systems, the antenna is
or because the isolation between the input and output ports of the circulator 9 is insufficient at about 2QdB, sufficient separation of the transmitted and received signals cannot be obtained.
For this reason, selecting different frequencies for the transmitting frequency and the receiving frequency has the disadvantage that the frequency utilization rate deteriorates.

[Purpose of the invention]

The present invention has been made in order to eliminate the drawbacks of the prior art as described above, and therefore, an object of the present invention is to eliminate the need for two antennas and the need to select different transmit and receive frequencies. It is an object of the present invention to provide a two-way simultaneous communication system in which there is no interference between transmitting and receiving signals, and the separation between transmitting and receiving signals is sufficient.

[Summary of the invention]

In order to achieve the above object, in the present invention, both the local station and the partner station perform transmitting and receiving operations alternately in time division, and transmission is performed by compressing the time axis of transmission No. 4, and expanding the time axis on the receiving side. We used the method of removing the The problem with time-division signal transmission and reception is the delay time, which is the time required for the signals of each of the five stations to reach the other station during communication. I have to throw it. The present invention is efficient regardless of the distance between the transmitting and receiving stations. It is distinctive in its decision making.

[Embodiments of the invention]

FIG. 2 is an explanatory diagram of the operating principle of the transmission/reception time division operation according to the present invention. As seen in the figure, both the own station and the other station
Assuming that transmission and reception are performed alternately with a period of t3 for the transmission period and t for the reception period, the local station starts transmitting, the other station receives the signal, and then the other station starts transmitting. The time until the own station starts receiving the signal is expressed as 2τ+tr (1) where τ is the delay time required for the signal to reach the other station. Therefore, in order to properly transmit and receive signals, the following relational expression needs to hold true.

N (t, + tr) + t, = 27 + tr, where N: positive integer, where the transmission period tS and reception period tr are equal, ts - t
If r=trs, then τ is obtained. In other words, the delay time τ and the transmission/reception period trs
The transmission and reception of signals is properly performed when the ratio of N to N is expressed as a positive integer (in the example of FIG. 2, N=3).

The present invention pays attention to this relational expression, transforms the above equation (3) into τ trs-1 . . . (4), and uses this. That is, the delay time τ is measured in advance, divided by an appropriate integer N, and the transmission/reception period trs
By obtaining the period trs and using the obtained period trs as the transmission/reception switching timing, time-division communication is possible regardless of the distance between the transmitting and receiving stations.

FIG. 3 is a block diagram showing one embodiment of the present invention.

In FIG. 3, the same numbers as in FIG. 2 indicate the same functional blocks.

In the figure, 11 is a delay time measuring circuit, 12 is a transmission/reception control circuit, 13 is a time-base compression circuit, 14 is a time-base expansion circuit, and 15 is a quadruple generation circuit. A delay time measuring circuit 11 measures the delay time required for a signal to propagate between the transmitting and receiving stations.

That is, the measurement pulse signal is sent from the same circuit 11 to the other station via the transmitting section 3 and the antenna 10, and at this time, the other station is in the receiving state and immediately upon receiving the measurement pulse signal, a response pulse signal is sent back from the other station without delay. The signal is input to the delay time measuring circuit 11 via the antenna 10 and the receiving section 6, and the delay time τ is obtained by measuring the time from the transmission of the measurement pulse signal to the reception of the response pulse.

The transmission/reception control circuit 12 generates a pulse at a period of trs obtained by dividing the delay time τ by an appropriate integer N, and switches the time axis compression circuit 13JP, time axis expansion circuit 14, ACUP converter 2, and down converter 4. Control. In addition, due to the fact that signals are exchanged in a time-division manner, the signal flow is interrupted and becomes discontinuous. To avoid this, the signal is compressed in time by the time-base compression circuit 16 and transmitted. A time axis expansion circuit 14 performs time axis expansion and extracts the original signal.

This will be explained in detail with reference to FIG.

Figure 4 (a) shows the transmission number, and its period length is 3T.

It is assumed that the This continuous signal is converted into a period To
If time-division communication is performed by dividing the signals into three signals, the signals that should normally be continuous will be interrupted and sent every period T0, so if the receiving side receives them as they are, the received contents will be different. becomes unnatural.

Therefore, as shown in FIG. 4 (b), the transmitting side expands the time axis of the signal by twice as much as the period T. Extract it as the original signal.

In this way, in the period from transmission to reception, a free time S that spans the same < button period is generated due to time axis compression, and this free time is used to perform time-division communication.

In this way, in the present invention, time axis compression for transmission signals,
Also, by extending the time axis for received No. 4,
This makes it possible to perform time-division communication without interrupting continuous signals to be transmitted.

FIG. 5 is a circuit diagram showing a specific example of the delay time measuring circuit 11 and the transmission/reception control circuit 12 in FIG. In the figure, the same numbers as in FIG. 6 indicate the same functional clocks.

In FIG. 5, 16 is a monostable multi-bicycle L/-ta,
17 is an input of a transmitter (not shown), 18 is an up counter circuit, 19 is a start terminal, 20 is an output of a receiver (not shown), 21 is a stop terminal, UC is an up counter control circuit, 22 is a shift control circuit, 23 is a shift register,
24 is a shift terminal, 25 is the output of the shift register 23,
26 is a run counter circuit, 27 is a register, 28 is a count end signal output, 29 is a latch terminal, 50 is a start terminal, 31 is a 7-rip fold circuit, 33° 34
is a clock input terminal, DC is a down counter control circuit,
52.35 is a control terminal, 36.37 is a reset terminal, 3
Day is a buffer element.

Next, the circuit operation will be explained. First, delay time τ measurement circuit 1
We will explain from operation 1.

When a trigger signal as a measurement start signal is applied to the control terminal 35 of the monostable multivibrator 16 and the reset terminal 36 of the up counter control circuit UC, a monostable pulse is output from the monostable multivibrator 16, and the pulse is It becomes transmitter input 17 and is transmitted to the other station,
At the same time, the up-counter control circuit UC is cleared (reset) by the trigger signal input from the reset terminal 36, and the clock signal supplied from the start clock generation circuit 15 is input to the terminal 63, thereby shifting the shift register. Counting up 23.

Next, when the other station receives the transmitter input 17 and sends back a signal, this return signal is received as the receiver output 20 and applied to the stop terminal 21, so the up counter control circuit UC starts the counting operation. Stop. At this time, the bit array (that is, the count-up value of the clock signal) shown in the shift register 23 represents the time required for the signal to travel back and forth between the sending and receiving stations ← delay time 2τ), and then this is expressed as an appropriate integer N. The transmission/reception period tr can be calculated by dividing by
s is recognized.

At this time, N-2'' (n=0, 1, 2...
), division by this integer N is performed in shift register 2.
3 bit shift operation. The bit length of the shift register 23 is determined by the period of the clock signal from the clock generation circuit 15 and the maximum value of the delay time, and the oscillation frequency of the clock generation circuit 15 is set to 10M.
If ILz, the cycle of the four-way signal is 0.1 μs, which is the minimum measurable unit time of the delay time τ.

In addition, the maximum possible value of the delay time is the maximum communication distance of 5
If it is 0 km, the round trip time is 333.4 μs. Therefore, the bit length of the shift register 26 only needs to be a bit length that can count 6664 bits or more, and 2" =
4096, a bit length of 12 bits is sufficient.

The shift register 2'5 is shifted by the shift control circuit 22 activated by the receiver output 20, so that the shift register 23 stores data representing the transmission/reception cycle trs.

Next, the operation of the transmission/reception control circuit 12 will be explained. As already explained, the transmission/reception control circuit 12 is a circuit that generates timing control pulses for transmission and reception according to the obtained transmission/reception period trs.

When a trigger pulse as a start signal for starting a transmitting/receiving operation according to the transmitting/receiving period bs is applied to the reset terminal 67 of the seven flip-flop 31, the flip-flop 31 is reset, and the pulse passes through the buffer element 38 to the down counter 26. When the voltage is applied to the latch terminal 29 of the shift register 23, data indicating the transmission/reception cycle trs of the shift register 23 is latched in the register 27, and the start terminal 30 of the down counter control circuit DC is turned on, and the down counter 26 starts counting down. When the register 27 becomes 0, the count end signal 28 is outputted from the down counter control circuit DC and inputted to the flip-flop 51 via the terminal 52, so that its output is inverted. Therefore, a timing control pulse for transmission and reception is sent to the transmission and reception section.

The count end signal 28 from the control circuit DC is also sent to the start terminal 30 of the control circuit DC, and also to the register 27.
Since the start signal and the latch signal are also applied to the launch terminal 29 of the shift register 23, the register 27 returns to the initial state in which the data in the shift register 23 was latched, and starts counting down again under the control of the control circuit DC. .

By repeating the countdown operation in this manner, a pulse is generated at the output side of the seven-day flip-flop 31 according to the transmission/reception period trs, and is sent to the transmission/reception section. Note that the down counter 2 shown in this example
It is obvious that the circuit configurations of the up-counter 6 and the up-counter 18 may be different from the configuration shown in FIG.

Next, the time axis compression and expansion Q carried out in the present invention will be explained.

The time axis compression and time axis expansion of a signal can be easily achieved by changing the writing and reading speeds of the signal to the memory. For example, reading the signal at a clock frequency n times the writing clock frequency to the memory. By doing this, it is possible to obtain a signal whose time axis is compressed to 1/n with respect to the original signal, and if the writing and reading clock frequencies are set in the opposite relationship to the above, the time is n times that of the original signal. A signal with axial extension can be obtained.

Figure 6 shows a time base compression circuit using two analog memories (
3) is a circuit diagram showing a specific example of the circuit (corresponding to 13 in FIG. 3). Here, 25 is the output of the shift register 26 shown in FIG.
40 is a first analog memory, 41 is a second analog memory, 42, 43, 4B are analog switches,
44 and 45 are clock signal input terminals of each analog memory, 46 and 47 are digital switches, 49 is the output of the transmission/reception control circuit 12 shown in FIG. 5, 50 is a decoder, 51 is an AND element, and 52 is the first clock Signal 53 is the second clock signal.

However, in the same figure G, analog switch 42, 45 and A
The ND element 51 is arranged one-to-one for each memory cell of the analog memory 40, 410, but is not shown for the sake of simplicity.

First analog memory 40 and second analog memory 41
Writing to and reading from is performed by clock signals applied to respective clock signal input terminals 44, 45, in this example the first clock signal 52 is used for writing and the second
At this time, by selecting the second clock signal 55 to have a frequency n times higher than that of the first clock signal 52, the read signal is the same as the written signal. In comparison, the time axis is compressed to -.

Next, the circuit operation will be explained with reference to the waveform diagram in FIG.

In the following description, for the sake of simplicity, an example will be given in which the time axis compression ratio is selected to be 1/2, but as will be described later, the invention is not necessarily limited to this.

FIG. 7 is for explaining the operation of the time base compression circuit according to the present invention, and shows the write and read operations of the 1st analog memory and the 2nd analog memory for transmission and reception operations.

In FIG. 7, in a transmission/reception operation, a convex portion indicates a transmitting operation, a concave portion indicates a receiving operation, a convex portion indicates a read operation, and a concave portion indicates a write operation with respect to the center line of the first and second analog memories.

First analog memory 40 and second analog memory 41
The writing and reading operations of are performed alternately. For example, if reading is performed first when the first analog memory 40 is transmitting, then when the second analog memory 40 is transmitting after the next receiving operation.
Reading is performed from the analog memory 41 of. Writing to one analog memory is performed during the period in which the other analog memory is reading for transmission and during the subsequent period (combining the reception period).Now, considering the case where the transmission period and reception period are the same, Time axis compression of 1/2 is required.

In the specific example of FIG. 6, switching between the first and second analog memories 40, 41 is performed by analog switches 42, 4548 based on the output 49 from the transmission/reception control circuit, and the clock signals for writing and reading are as described above. It can be switched using digital switches 46 and 47 as shown in FIG.

The capacity of the analog memories 40 and 41 is required to be the sum of the transmission period and the reception period as described above, that is, 2 trs. tr5 varies depending on τ and N, but conversely, by determining the maximum capacity of the analog memories 40, 41 and changing N, it is possible to prevent trs from exceeding the maximum capacity of the analog memories 40, 41. The maximum capacity of the analog memories 40 and 41 is about 2000 times the write clock signal frequency1, for example 0.1, because if it is too large, the price of the analog memory will increase.
200μs for μs (10MHz) clock signal
It is appropriate to have a capacity of about
It must be controlled to 0 μs or less.

In the analog memories 40 and 41, it is necessary to change the read position depending on the change in the transmission/reception period trs, and this read position is twice the number of bits represented by the output 25 of the shift register 27 mentioned above. In this example, this position is obtained by the decoder 50, and the output 49 of the transmission/reception control circuit 12 and the AND element 5
By performing an AND with 1, the analog switches 42 and 43 are controlled and a read operation is performed. 0N10F of analog switch 42 and analog switch 43
The F operations operate in reverse.

The above explanation deals with the case where the time axis compression ratio is 1/2, but it goes without saying that the same effect can be achieved even if other time axis compression ratios are selected, but in order to realize this, it is necessary to plan for the following reasons. A slightly higher time axis compression ratio is required.

FIG. 8 is a more precise view of the operation explanatory diagram in FIG. 7, and the waveform legend in FIG. 8 is the same as that in FIG. 7.

Since the transmission/reception cycle trs includes the time Δt required for the operation to change from reception to transmission or from transmission to reception, the actual transmission time trs' is trs'=trs-2Δt. Therefore, the read time of each analog memory (when the time axis compression ratio is 1/2) is t4. Even though the writing time is smaller than 2 trs, the writing time is still the same as 2 trs.
The actual time axis compression ratio needs to be higher than the planned one.

Referring again to FIG. 6, the circuit operation will be supplementarily explained.

A signal input is applied to the first analog output terminal 40 via switch 48 (switched to the solid position) and to the clock input terminal 44 via switch 46 (solid position R).
is written to the memory 40 according to a first clock signal 52 provided to the memory 40.

At this time, the second analogue clock signal 53 is supplied to the clock input terminal 45 via the previously written signal input terminal t and the switch 47 (solid line position). A signal read from the memory 41 via the switch 46 and compressed in the time axis becomes the signal output.

Next, the output 49 of the transmission/reception control circuit 12 causes the switch 4 to
6.47,4B is in a state where it has been switched from the solid line position to the broken line position. At this time, the signal input is sent to the second analog memory 41 via the switch 48 (dotted line position).
and is written in accordance with a first clock signal 52 applied to clock input terminal 45 via switch 47 (dashed line position). On the other hand, in the first analog memory 40, the previously written signal input is switched from the memory 40 according to a second clock signal 53 supplied to the clock input terminal 44 via the switch 46 (in the dashed line position). The signal read out via 42 and compressed in time axis becomes the signal output.

Note that in order to output a signal by extending the time axis of the signal input, all that is required is to switch the frequencies of the first clock signal 52 and the second clock signal 56 in the circuit shown in FIG. Good things will be easily understood.

Although the specific example of the time axis compression circuit described above uses an analog memory as the memory, it is obvious that the present invention is not limited to this, and a similar function can be obtained even if a digital memory is used.

〔Effect of the invention〕

According to the present invention, by measuring in advance the delay time τ required for a signal to reach the other station from the own station and determining the appropriate transmission/reception cycle trs from the delay time τ, Time-division transmission and reception can be performed efficiently regardless of distance, and by compressing the time axis of the signal on the transmitting side and expanding the time axis on the receiving side, simultaneous two-way communication with no signal loss is realized even in time-division. It has the advantage of being possible.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the circuit configuration of a conventional general two-way simultaneous communication system, Fig. 2 is a diagram illustrating the operating principle of the transmission/reception time division operation according to the present invention, and Fig. 6 is an illustration of an embodiment of the present invention. 4 is a diagram explaining the principles of time axis compression and expansion used in the present invention. Part 5 is a circuit diagram showing a specific example of the delay time measurement circuit and transmission/reception control circuit in Fig. 3. FIG. 6 is a circuit diagram showing a specific example of the time axis compression circuit, and FIGS. 7 and 8 are operation waveform diagrams of various parts in the circuit of FIG. 6, respectively. Description of symbols 11...Delay time measurement circuit, 12...
Transmission/reception control circuit, 13... Time axis compression circuit, 1
4... Time axis extension circuit, 15... Clock generation circuit, 16... Monostable multivibrator, 18... Up counter circuit, 22...
...Shift control circuit, 23...Shift register, 26...Down counter, 27 register, 31...Flip-flop circuit, 40.4
1...Analog memory, 42.45.48...
...Analog switch, 46,47...
Digital switch 150...Decoder, 51.
...AND element, prone patent attorney Akio Namiki Figure 1 Figure 2 Figure 30 Figure 4

Claims (1)

[Claims] 1) 1/N of the signal to be transmitted (N is an integer)
The local station and the other station are each equipped with a transmitting circuit that compresses the time axis and transmits it, and a receiving circuit that expands the time axis of receive signal 4 by N times and extracts it. When the time required for propagation is τ, transmission and reception is carried out in a time-division manner between the local station and the other station using the transmitting circuit and the receiving circuit at a time period of τ/N. A two-way simultaneous communication method.