JPS6057459A - Single-chip microcomputer - Google Patents

Abstract

PURPOSE:To observe easily the state of an inner data bus of a single-chip microcomputer by using a logical circuit to obtain an OR between read and write control signals and opening outside an extension port with the output of said logical circuit. CONSTITUTION:When a CPU12 performs reading actions to inner RAMs 14 and 16, an inner read control signal Ri is applied to a bi-directional buffer 18 via logical circuits G1 and G2. In this case, the G2 is activated by a test mode selection signal R given from outside. Thus the buffer 18 is opened outside. In other words, the state of an inner data bus DB is delivered outside via a data port Pb for extension. In a write mode the buffer 18 is also opened outside by the signal Ri and a logical circuit G3. That is, the conflict is avoided between write and read control signals at the buffer 18. Thus the buffer 18 delivers outside the state of the bus DB even in an inner read mode for easy observation of said state of the DB.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a technology that is particularly effective when applied to a 1 microφ computer technology, and more particularly to a single step microcomputer.

[Background technology]

For example% some kind of single. A chip microcomputer has an expansion board for accessing an external storage device (for example, a single chip microcomputer RFFI name HD 6305 XJ sold by Hitachi, Ltd.).

This type of single skewer micro computer has a storage device internally, but by having an external storage device via the expansion board mentioned above, its functions can be expanded and used. can do.

The inventor of the present application has developed the following technology for the above-mentioned single-chip microcollator based on microcomputer technology.

That is, by using the expansion board, the state of the internal data bus of the single Φ chip microcomputer, that is, the signals on the internal data bus, is observed from the outside, and the operation of the microcomputer is thereby tested. However, it has become clear to the inventor of the present invention that such a technique poses a problem in that the state of the internal data bus cannot be fully grasped.

The reason for this is that there are very limited cases in which the data bus inside a single fist, micro, or combination tool can be observed from the outside. FIG. 1 shows an example of a single chip e-microcomputer. The single chip microphone 08 computer 10 shown in the same figure is
The CPU (central processing unit) 12 also has a RAM 14 and a ROM 16 as internal storage devices. It also has an extended address baud)Pa and an extended data baud)Pb. The expansion data bus (Pb) is connected to the internal data bus DDK via a bidirectional path buffer 18. The bidirectional path buffer 18 includes two bidirectional path buffers connected in opposite directions.
It is constructed using a pair of tri-state buff knives 20 and 22. Tri-state buffers 20 and 22 are driven and controlled in a complementary manner by a write control signal W and a read control signal R.

That is, when writing to an external storage device, the buffer 20 facing the outside is activated by the write control signal W. Furthermore, when reading data from the external storage device, the read control signal R activates the flap 22 facing inside. This allows for a two-way pass buffer
18 is opened either to the outside lfB or to the inside. In this case, only when the bidirectional bus buffer 18 is opened toward the outside, the state of the internal data path DB is outputted to the outside, thereby making the internal data bus DB observable from the outside. However, in other cases, particularly when the internal RAM 14 (h) writes or reads from the ROMI 6, the state of the internal data bus DB is not output to the outside, and therefore the state cannot be observed from the outside. In this way, there are 9 problems in that the state of the internal data bus cannot be fully grasped from the outside.
For this type of single-chip microcomputer, for example, it was not possible to perform sufficient testing at the manufacturing or shipping stage. Or, they were unable to perform emulation attacks.

[Purpose of the invention]

An object of the present invention is to provide a microcomputer technology that makes it possible to easily observe the state of the internal data bus (signals on the internal 7'--path) of a single-chip microcomputer. It's something.

Even when a computer is reading its internal storage device, the state of the internal data bus (signals on the internal data bus) at that time can be observed via the expansion data boat. It provides microcomputer technology that enables

Furthermore, the present invention provides microcomputer technology that facilitates testing or emulation of the internal operation of single-chip microcomputers.

The above and other objects and novel features of the present invention will become clear from the description of this specification and the accompanying drawings.
It will be.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, by summing the internal bus status of a single-chip microcontroller with an internal storage device and outputting it to the outside, it is possible to fully understand the status of the internal path, and it is possible to perform operational tests or two-Rm storage cods. The goal is to harmonize them so that they can be used together.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS Representative embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 shows an embodiment of a single-chip micro-tatami combination to which the present invention is applied. In the drawings, the same parts h as those shown in FIG. 1 above are denoted by the same reference numerals. The single fist chip microphone 12e combination gourd-type device shown in the figure has a CPU (central processing unit) 12, a RAM 14 and a ROM 16 as internal storage devices. In addition, the expansion address board) Pa and the expansion data board) Pb
has. The expansion data boat pb is a bidirectional busbar,
, +7 18 to the internal data bus DB. The bidirectional bus buffer 18 is constructed by using two sets of triste shift blocks 20 and 22 that are connected in opposite directions.

Tri-state buffers 20 and 22 receive write control signal W.
The drive control is performed in a complementary manner by the readout control signal R and the readout control signal R.

That is, when writing to an external storage device, the buffer 20 facing the outside is activated by the write control signal WK. Furthermore, when reading from an external storage device, the buffer 22 facing the inside is activated in response to the read control signal R. This allows the bidirectional bus buffer 18 to be opened to either the outside or the inside. The read/write control signal R/W is output from the CPU 12.

Kov > Actual ts example single, thousand, pu, micro, computer lO [t! , further Vcl11a + logic circuit Gl,
G2.

G3 is provided. Logic circuit G1 is a logical sum (OR)
gate, and logic circuit G2. G3 is a logical product (AN
D) Geet. The above write control signal W is the logic circuit G
1 to the bidirectional data bus buffer 18. Moreover, the above read control signal R is logic 1.
The signal is supplied to the bidirectional bus bar 7-18 via the circuit G3.

As will be explained later with reference to FIG. 3, R4 is an internal read control signal generated when the CPU 12 performs a read operation on the internal RAM 14 or ROM 169.

This signal Rth, 70f (A M14 and ROMxc
In addition to ic%, it is also given as a write control signal to the bidirectional busper y7-18 via the logic circuits Gl and G2. In this case ~ the logic circuit G2 is
It is summed to be activated by an externally applied signal RX. This external signal RX functions as a test mode selection signal. That is, when the test mode selection signal RX is input, the internal read signal Ri is output to the logic circuit G2. The above bidirectional bus buffer I via Gl
BK write frJg is given as a signal ◎ Due to this trap, the bidirectional bus buffer 18 not only receives the normal write control signal W but also receives the internal read control signal RI.
It is also opened to the outside when it is uttered. In other words, the state of the internal data bus DB is
The signal is output to the outside via the IC. As a result, CP[J12 is connected to internal RAM14 or ROMI.
VCfL is set so that the state of the internal data bus DB at that time is outputted to the outside even when data is being read from the data bus 6, that is, even when no write operation is being performed to the outside.

On the other hand, the internal read control signal R1 is configured to be inverted and input to the logic circuit 03. This logic circuit G3 is an AND gate.

When the internal read control signal Ri is input to one of the input nodes, the logic circuit G35c prohibits transmission of the normal continuous read control signal R to the bidirectional path buffer 182. As a result, the bidirectional bus buffer 18 is used not only when the CPU 12 writes to an external storage device, but also when writing to the internal RAM 14 or ROM.
16 is also opened to the outside. That is, in the bidirectional bus buffer 18, conflict between the write control signal and the read control signal is avoided. Due to this.

Bidirectional path buffer 18 can output the state of internal data bus DB to the outside even during internal reading.

FIG. 3 shows an example of a circuit for generating the internal read control signal Rf. The circuit shown in the figure is provided inside a single-chip microcomputer 410. This circuit is composed of an address decoder 24 and a logic circuit G4. The address decoder 24 is connected to the address bus AB.
decodes the address data supplied via the This address decoder 24 outputs a decode output D when specific address data, that is, address data that selects the internal RAM 14 or ROM 16, is supplied.
It is set to output a.

This decode output Da is input to the logic circuit G4 together with the read control signal R issued from the CPU 12. This logic circuit G4 is an AND gate, and its logical product output is used as the internal read control signal Ri.

Now, as above 1, CPU 12 uses internal RAM 1.
When performing a read operation only to 4 or ROM 16, by applying the test mode selection signal RX from the outside, the state of the internal data bus DB changes to the above bidirectional bus rough 18 and expansion. data (4 baud) will be output to the outside via Pb. This allows the state of the internal data bus DB to be easily observed from the outside. From this button,
Using the expansion data boat Pb, an internal operation test or an emulation process can be easily and reliably performed.

Further, by not supplying the test mode selection signal RX at times other than during testing, it is possible to prevent the state of internal data bus DB during internal reading from being output to the outside. For example, after the necessary test is completed, by fixing the potential of the test mode selection signal RX to a value that makes the logic circuit G2 inactive, the state of the internal data bus DB is changed to the external state. It is possible to prevent output to .

〔effect〕

By making it possible for the 1110Ptl to output the state of the internal data bus (signal on the internal data bus) to the outside not only when writing to the internal storage device but also when reading. Easy access to the internal data bus status of a single bone chip and micro comviator
CI! This has the effect of being able to be measured.

When the 127 CPU reads the internal storage device, it is possible to output the status of the internal data bus to the outside even when the CPU is busy.Since K, the single-chip microcomputer is reading the internal storage device. Even in this case, it is possible to observe the state of the internal data bus at that time via the expansion data port.

13) By making it possible to output the state of the internal data bus to the outside even when the CPU reads the internal storage device, it is possible to test the internal operation of the single-channel microcomputer 4 or perform emulation. This has the effect of making it easier to perform.

Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that this invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Nor.

[Application field]

In the above description, the invention made by the present inventor has mainly been explained with reference to a specific microcomputer technology, which is the field of application behind the invention, but the invention is not limited thereto. The present invention is applicable to at least a single-chip microcomputer computer having an internal storage device under technical conditions such that the state of the internal bus (signal on the internal bus) is outputted to the outside.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an example of the main part of a single-chip microcomputer, and FIG. 2 is a circuit diagram showing an example of the main part of a single-chip microcomputer according to the technology of the present invention. FIG. 3 is a circuit diagram showing an example of a circuit that generates an internal read control signal. lO...Single chip micro combination 4% 12...CPU (Central Processing Unit), 14...Internal storage device (RAM), 16...Internal storage device (1 (
OM), 18... Two-way bus bavvu, 20.22...
・Tristate 797th, 24... Address decoder, Da... Decode output, R/W... Read/W included control signal, R... Read control signal, W... Yoikoshi ff1l
J control signal, Ri...internal read control signal, RX...dest mode selection (No. 1, AB...address bus, lJl
] River day bus, Pa...address port for expansion,
)' l)...Expansion data port, Gl, G2. G
3. G4...Logic [C11 path. Figure 1 β exemption

Claims (1)

[Claims] (1) A single-chip 9-microΦ computer having an internal storage device and an expansion board for accessing an external storage device, wherein when the internal storage device is continuously installed, A single-chip microcomputer characterized in that the state of a data bus inside the microcomputer is output to the outside via the expansion board. 2. The single-step microcomputer according to claim 1, wherein the expansion boat includes a bidirectional bus bar and a sofa interposed between the internal data bus and the external data bus. . 8. A logic circuit is provided internally for calculating the logical sum of a read control signal for reading the internal storage device and a write control signal for writing to the external storage device, and the logic output of this logic circuit is 3. The single-chip microcomputer according to claim 1, wherein said expansion boat is opened to the outside.