JPS605548A - Integrated circuit and manufacture thereof - Google Patents
Integrated circuit and manufacture thereofInfo
- Publication number
- JPS605548A JPS605548A JP10010483A JP10010483A JPS605548A JP S605548 A JPS605548 A JP S605548A JP 10010483 A JP10010483 A JP 10010483A JP 10010483 A JP10010483 A JP 10010483A JP S605548 A JPS605548 A JP S605548A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- base material
- cooling
- passages
- grooves
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 238000001816 cooling Methods 0.000 claims abstract description 39
- 239000000463 material Substances 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 14
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 7
- 238000005520 cutting process Methods 0.000 claims description 4
- 238000009792 diffusion process Methods 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052710 silicon Inorganic materials 0.000 abstract description 8
- 239000010703 silicon Substances 0.000 abstract description 8
- 239000013078 crystal Substances 0.000 abstract description 4
- 239000002826 coolant Substances 0.000 abstract 1
- 239000003507 refrigerant Substances 0.000 description 10
- 238000004806 packaging method and process Methods 0.000 description 6
- 239000010931 gold Substances 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 235000012431 wafers Nutrition 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 241000283973 Oryctolagus cuniculus Species 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
- 230000002747 voluntary effect Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
- H01L23/473—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids by flowing liquids
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、一般にＩＣやＬＳＩさらに超ＬＳＩと称され
る集積回路及びそれの製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated circuit generally referred to as an IC, LSI, or even VLSI, and a method for manufacturing the same.
近年のコンピュータの進展は著しく、今後は高速性をめ
て集積回路を高密度実装する方向にあり、この高密度実
装を実現できるか否かは、高密度実装に伴って発生する
膨大な熱を如何に冷却させるかにかかつていると言って
も過言でない。Computers have made remarkable progress in recent years, and the future trend is to achieve high speed and high-density packaging of integrated circuits.Whether this high-density packaging can be achieved depends on the huge amount of heat generated by high-density packaging. It is no exaggeration to say that it depends on how it is cooled.
ところで、これまでの集積回路に対する冷却技術には、
集積回路に空気を流す強制空冷方式と、フレオンやチッ
ソ等のガスや冷却された水などの冷媒を流す流路が形成
された冷却板に集積回路を接触させる冷媒冷却方式とに
大別されるが、強制空冷方式は、冷媒冷却方式に比べて
冷却効率が低いもので、冷媒冷却の方式に主流が移行す
る傾向にある。By the way, conventional cooling technologies for integrated circuits include:
There are two main types of cooling methods: forced air cooling, in which air is passed through the integrated circuit, and refrigerant cooling, in which the integrated circuit is brought into contact with a cooling plate that has channels formed to flow a refrigerant such as Freon or Nisso gas or cooled water. However, the forced air cooling method has lower cooling efficiency than the refrigerant cooling method, and there is a tendency for the mainstream to shift to the refrigerant cooling method.
しかしながら、上記の冷媒冷却方式は、冷却板を介して
の冷媒による間接冷却であって、冷媒の冷却能力の割に
冷却効率が低く、上記何れの冷却方式を採るにしても、
集積回路の高密度実装を実現させるにほど遠い状況にあ
る。However, the above refrigerant cooling method is indirect cooling using the refrigerant through a cooling plate, and the cooling efficiency is low compared to the cooling capacity of the refrigerant.
We are still far from achieving high-density packaging of integrated circuits.
本発明は、上述の実情に鑑みて成されたものであって、
効率の高い直接冷却の方式を採ることのできる、従前に
全く無い新規な集積回路の提供を第１の目的としており
、そして本発明の第２の目的は、上記の集積回路を量産
するに適した製造方法の提供にある。The present invention has been made in view of the above-mentioned circumstances, and
The first object of the present invention is to provide a completely new integrated circuit that can employ a highly efficient direct cooling method, and the second object of the present invention is to provide an integrated circuit that is suitable for mass production of the above-mentioned integrated circuit. The objective is to provide a manufacturing method.
以下、本発明による集積回路の製造手順について説明す
る。Hereinafter, a procedure for manufacturing an integrated circuit according to the present invention will be explained.
■ 先ず、第１図（イ）に示すように、深さ並びに巾が
ほぼ同寸法の複数個の溝ａ・・を互いに平行に形成した
シリコン結晶製の基板１と、該基板１の前記溝ａ・・を
閉じる同じくシリコン結晶製の蓋板２を用意する。First, as shown in FIG. 1(a), a silicon crystal substrate 1 is formed with a plurality of grooves a... having substantially the same depth and width formed in parallel to each other, and the grooves of the substrate 1 are A lid plate 2 also made of silicon crystal is prepared to close a.
これら基板１並びに蓋板２の夫々は、シリコツインゴツ
トをスライスしたウェハを使用しており前記基板１とし
て、ダイヤモンドカッターを備えたダイシングマシンに
よって、４５０μ厚さのシリコンウェハに４００μ深さ
・８００μ中・１，１００μピツチの溝ａ・・・を加工
したものを用い、蓋板２として、前記溝ａの両端側に対
応する箇所に、外部流路接続用の孔ｂ・・・を形成した
４５０μ厚さのシリコンウェハを用いているが、これら
の寸法設定は各種変更ｉｏ１″能である。Each of the substrate 1 and the lid plate 2 uses a wafer obtained by slicing silicon twingots, and as the substrate 1, a silicon wafer with a thickness of 450μ is diced to a depth of 400μ and a diameter of 800μ in a dicing machine equipped with a diamond cutter.・A 450 μm plate with holes b for external flow path connection formed at locations corresponding to both ends of the grooves a as the cover plate 2. Although silicon wafers with different thicknesses are used, these dimensions can be changed in various ways.
■ 次に、同図（ハ）に示すように、蓋板２によって前
記溝ａ・・・を閉じる状態で、該蓋板２と基板１（！ｌ
−を接合し、多数の冷却流路Ａ・・・を並列に備える集
積回路用基材３を作製する。■Next, as shown in FIG.
- to produce an integrated circuit substrate 3 having a large number of cooling channels A in parallel.
前記基板１に対して蓋板２を接合するに際して、同図（
ロ）に示すように、基板１と蓋板２の接合面に、真空蒸
着法やスパッタリング法などによって金の膜Ｃ１ｃを予
め形成し、そして両者１，２間に、蓋板２の孔ｂ・・と
同一パターンの孔ｅを形成した金箔ｄを介在させ、かつ
該孔ｅとｂを溝ａの両端側に対応する箇所に位置させて
、これらを高温・高真空下に保ち、かつ、上下から加圧
し、もって金膜Ｃと金箔ｄとを介して基板１と蓋板２と
を拡散によって接合しである。When joining the cover plate 2 to the substrate 1, the steps shown in the same figure (
As shown in b), a gold film C1c is formed in advance on the bonding surface of the substrate 1 and the cover plate 2 by vacuum evaporation or sputtering, and between the two 1 and 2, the hole b of the cover plate 2 is A gold foil d with holes e in the same pattern as . Then, the substrate 1 and the lid plate 2 are bonded by diffusion through the gold film C and the gold foil d.
而して、かかる拡散接合によれば、その接合面が合金化
するので機械的強度を高く期待でき、かつ金箔ｄの存在
によって金膜Ｃが粗面であっても高いシールを期するこ
とができ、優れた接合を図り得るものとして採用してい
る。According to such diffusion bonding, high mechanical strength can be expected because the bonding surfaces are alloyed, and even if the gold film C has a rough surface, high sealing can be expected due to the presence of the gold foil d. It has been adopted as a material that can achieve excellent bonding.
■ 次に、第２図に示すように、前記集積回路用基材３
の一側平面でかつ前記冷却流路の夫々に対応する箇所に
、現在の技術をもって集積回路パターンＢ・・・を形成
する。■Next, as shown in FIG. 2, the integrated circuit base material 3
An integrated circuit pattern B is formed using current technology on one side of the plane and at a location corresponding to each of the cooling channels.
■ 次いで、同じく第２図に示すように、前記基材３を
ｘｌ、ｘ２．Ｘ］で示す線に活って切断分離することに
より、内部に冷却流路を備えた集積回路４の複数個を製
造するのである。(2) Next, as shown in FIG. 2, the base material 3 is heated to xl, x2. By cutting and separating along the lines indicated by X], a plurality of integrated circuits 4 having internal cooling channels are manufactured.
上記構成の集積回路４によれば、所定数の集積回路４・
・・の冷却流路Ａどうしを外部流路によって接続し、こ
れらの流ｂ’８Ａ・・に冷媒を流すことによって、集積
回路４そのものを直接的に高効率で冷却でき、従って、
コンピュータにおいて、高速性を追求する上での高密度
実装を実現できる。According to the integrated circuit 4 having the above configuration, the predetermined number of integrated circuits 4.
The integrated circuit 4 itself can be directly cooled with high efficiency by connecting the cooling channels A of... by an external channel and flowing the refrigerant through these flows b'8A...
In computers, high-density packaging can be realized in pursuit of high speed.
尚、内部に１本あるいは複故木の冷却流路Ａを形成した
基材３に、１個の集積回路用パターンＢを形成して、集
積回路４を単品で製造することも可能であり、また必要
に応じて、集積回路用パターンＢを基材３の両側平面に
設けるも良い。更に、基板１と基材２との間に金箔ｄを
介在させたが、これを省略するも良く、かつ、基材３と
してこれの材質をシリコンとしたが、ゲルマニウム、ガ
リウムひ素等を利用することもできる。Note that it is also possible to manufacture the integrated circuit 4 as a single item by forming one integrated circuit pattern B on the base material 3 in which one or multiple cooling channels A are formed. Further, if necessary, the integrated circuit pattern B may be provided on both sides of the base material 3. Further, although the gold foil d is interposed between the substrate 1 and the base material 2, it may be omitted, and the material of the base material 3 is silicon, but germanium, gallium arsenide, etc. may be used. You can also do that.
また、基材３に対してそれの冷却流路Ａの長手方向に複
数個の集積回路用パターンＢを設ける構成をとるも良く
、この場合、第３図に示すように、短かい溝ａを長手方
向で断続させて基材３に形成すれば良く（図中のＸ、は
切断分離線である）、あるいは、外部流路の接続部を冷
却流路Ａの両端とする場合にあっては、１木の長い冷卯
”、流路１に漕わせて集積回路用パターンＢを断続させ
て形成し、隣接するパターンＢの隣接中間で基材３を切
断分離させれば良い。Alternatively, a configuration may be adopted in which a plurality of integrated circuit patterns B are provided in the longitudinal direction of the cooling channel A of the base material 3. In this case, as shown in FIG. It may be formed in the base material 3 intermittently in the longitudinal direction (X in the figure is a cutting separation line), or in the case where the connecting portions of the external flow path are at both ends of the cooling flow path A. It is sufficient to form the pattern B for an integrated circuit intermittently by running one long cold rabbit through the flow path 1, and to cut and separate the base material 3 at the intermediate point between adjacent patterns B.
以上説明したように本第１発明の集積回路は、内部に冷
却流路を形成した基材の外面に集積回路用パターンを設
けた点に特徴を有し、而して上記構成の集積回路によれ
ば、集積回路そのものを直接的に冷却することができる
もので、従来の冷媒冷却方法による間接冷却に比べて、
その冷媒の冷却能力を同じくしながらも高い冷却効率を
指示させることができ、従って集積回路の高密度実装を
実現できるようになったのである。As explained above, the integrated circuit of the first invention is characterized in that an integrated circuit pattern is provided on the outer surface of the base material in which a cooling channel is formed. According to this method, it is possible to directly cool the integrated circuit itself, compared to indirect cooling using conventional refrigerant cooling methods.
Although the cooling capacity of the refrigerant remains the same, it is possible to specify high cooling efficiency, thus making it possible to realize high-density packaging of integrated circuits.
そして本第２発明による集積回路の製造方法は、複数個
の溝を互いに平行に形成した基板と、該基板の溝を閉じ
る蓋板とを拡改接合して、多数の冷却流路を並列に備え
た基材を作製し、該基材の少なくとも一側平面でかつｔ
ｉｔＪ記冷却流路の夫々に対応する箇所に、集積回路用
パターンを形成すると共に、前記基材を冷却流路の隣接
中間において切断分離して、複数個の集積回路を製造す
る点に特徴を有し、これによって、自身を直接的に冷却
することのできる新規な集積回路の複数個を一挙に得ら
れるようになり、延いては、直接冷却タイプの集積回路
を安価に提供できるようになった。In the method for manufacturing an integrated circuit according to the second aspect of the present invention, a substrate having a plurality of grooves formed in parallel to each other and a cover plate that closes the grooves of the substrate are expanded and joined to form a large number of cooling channels in parallel. t
It is characterized in that a pattern for integrated circuits is formed at a location corresponding to each of the cooling channels, and the base material is cut and separated in the middle between adjacent cooling channels to produce a plurality of integrated circuits. As a result, it has become possible to obtain multiple new integrated circuits that can directly cool themselves at once, and by extension, it has become possible to provide direct cooling type integrated circuits at low cost. Ta.
図面は本発明による集積回路及びその製造方法に係り、
第１図（イ）、（ロ）、（ハ）は集積回路製造手順を示
す説明図、第２図は集積回路として切断分離する以前の
全体平面図、第３図は別実施例の断面図である。
１・・・基板、２・・蓋板、３・・・基材、４・集積回
路、ａ、・溝、ｂ、ｅ・・・外部流路接続用孔、Ｃ・ｒ
Ｔｈ膜、ｄ−・金箔、Ａ・・冷却流路、Ｂ・・集積回路
パターン。
自発手続補正書
昭和５８年７月Ｓ日
特許庁長官 殿
３、 補正をする者
事件との関係 特許出願人
（ＪＥ”’ｉＴｉ 京都市南区吉祥院宮の来町２香地氏
名（名称）株式会社スタンダードテクノロジ代表者堀
場雅夫
４、代理人The drawings relate to an integrated circuit and its manufacturing method according to the present invention,
Figures 1 (a), (b), and (c) are explanatory diagrams showing the integrated circuit manufacturing procedure, Figure 2 is an overall plan view before cutting and separation as an integrated circuit, and Figure 3 is a cross-sectional view of another embodiment. It is. DESCRIPTION OF SYMBOLS 1... Substrate, 2... Cover plate, 3... Base material, 4... Integrated circuit, a, Groove, b, e... External flow path connection hole, C/r
Th film, d-.gold foil, A.. cooling channel, B.. integrated circuit pattern. Voluntary procedure amendment July S, 1980 Director General of the Patent Office 3. Relationship with the case of the person making the amendment Patent applicant (JE"'iTi 2 Koji Kimachi, Kisshoinnomiya, Minami-ku, Kyoto City Name) Standard Technology Co., Ltd. Representative Masao Horiba 4, Agent
Claims (1)
用パターンを設けであることを特徴とする集積回路。 （の 複数個の溝を互いに平行に形成した基板と、該基
板の溝を閉じる蓋板とを拡散接合して、多数の冷却流路
を並列に備えた基材を作製し、該基材の少なくとも一側
乎面でかつ前記冷却流路の夫々に対応する箇所に、集積
回路用パターンを形成すると共に、前記基材を冷却流路
の隣接中間において切断分離して、複数個の集積回路を
製造することを特徴とする集積回路の製造方法。 （■ 前記溝を長手方向で断続して形成し、該溝を閉じ
る蓋板には、６溝の両端側に対応する箇所に外部流路接
続用の孔を形成しである特許請求の範囲第０項に記載の
集積回路の製造方法。 （少 前記基板と蓋板との拡散接合に先立って、両者の
拡散接合面に金膜を形成すると共に、当該基板と蓋板と
の拡散接合に際して両者間に金箔を介在させることを特
徴とする特許請求の範囲第■項又は第０項に記載の集積
回路の製造方法。[Scope of Claims] (D) An integrated circuit characterized in that an integrated circuit pattern is provided on the outer surface of a base material in which a cooling channel is formed. and a lid plate that closes the grooves of the substrate are diffusion bonded to produce a base material having a large number of cooling channels in parallel, and each of the cooling channels is disposed on at least one side of the base material. A method for manufacturing an integrated circuit, comprising: forming an integrated circuit pattern at a location corresponding to the above, and cutting and separating the base material at an intermediate point between adjacent cooling channels to manufacture a plurality of integrated circuits. (■ The grooves are formed intermittently in the longitudinal direction, and the cover plate that closes the grooves is provided with holes for external flow path connection at locations corresponding to both ends of the six grooves. The method for manufacturing an integrated circuit according to item 0. A method of manufacturing an integrated circuit according to claim 1 or 0, characterized in that a gold foil is interposed between them.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10010483A JPS605548A (en) | 1983-06-03 | 1983-06-03 | Integrated circuit and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10010483A JPS605548A (en) | 1983-06-03 | 1983-06-03 | Integrated circuit and manufacture thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS605548A true JPS605548A (en) | 1985-01-12 |
| JPS6361781B2 JPS6361781B2 (en) | 1988-11-30 |
Family
ID=14265077
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10010483A Granted JPS605548A (en) | 1983-06-03 | 1983-06-03 | Integrated circuit and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS605548A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54125210A (en) * | 1978-03-09 | 1979-09-28 | Bosch Gmbh Robert | Ceramics of zirconium oxide* formed body therefrom* preparation thereof* and detector for oxygen in exhaust gas |
| JPS6380856U (en) * | 1986-11-17 | 1988-05-27 | ||
| US6174489B1 (en) | 1995-09-01 | 2001-01-16 | Denso Corporation | Method for manufacturing a gas sensor unit |
| WO2003025476A2 (en) * | 2001-09-07 | 2003-03-27 | Raytheon Company | Microelectronic system with integral cyrocooler, and its fabrication and use |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4943875U (en) * | 1972-07-20 | 1974-04-17 |
-
1983
- 1983-06-03 JP JP10010483A patent/JPS605548A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4943875U (en) * | 1972-07-20 | 1974-04-17 |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54125210A (en) * | 1978-03-09 | 1979-09-28 | Bosch Gmbh Robert | Ceramics of zirconium oxide* formed body therefrom* preparation thereof* and detector for oxygen in exhaust gas |
| JPS6324951B2 (en) * | 1978-03-09 | 1988-05-23 | Bosch Gmbh Robert | |
| JPS6380856U (en) * | 1986-11-17 | 1988-05-27 | ||
| US6174489B1 (en) | 1995-09-01 | 2001-01-16 | Denso Corporation | Method for manufacturing a gas sensor unit |
| WO2003025476A2 (en) * | 2001-09-07 | 2003-03-27 | Raytheon Company | Microelectronic system with integral cyrocooler, and its fabrication and use |
| WO2003025476A3 (en) * | 2001-09-07 | 2004-02-05 | Raytheon Co | Microelectronic system with integral cyrocooler, and its fabrication and use |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6361781B2 (en) | 1988-11-30 |
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