JPS6052364B2 - postal scales - Google Patents

Description

[Detailed description of the invention] TECHNICAL FIELD This invention relates to electronic postal scales.

More particularly, the invention provides for postage charges to be stored in various memory sections, each of the memory sections generally corresponding to the type of shipment of the parcel to the destination area, and each of the memory sections to store the postage charges. The present invention relates to such a postal scale that is configured with a plurality of memory locations that can be stored and addressable as a function of the weight of the parcel and the particular destination area. The invention further relates to various control mechanisms incorporated into postal scales to eliminate the possibility of incorrect or erroneous postage display. The invention also relates to an electronic postal scale which has a relatively simple construction, is low in cost and is able to take full advantage of the advantages of digital circuitry available in the form of IC circuits. Generally speaking, when trying to calculate the postage cost for a parcel to be mailed to a required destination, this fee (postage stamps) is determined not only by the weight of the parcel, but also by the area of its destination and the transportation. It must also be determined by the type of

In particular, each type of shipping has a specific postage rate. Before the advent of automatic postal calculation machines, individuals would weigh the parcel to be sent, and once this was determined, they would consult a reference table for the type of transport chosen and record the charges specified by the required destination area. Appropriate postage rates were determined through this procedure. Comparing each type of transport required the individual to consult each reference table and record the corresponding charges obtained therefrom. Such postage calculation procedures were not only time-consuming, but also introduced various errors that would not have occurred if such look-up tables were used correctly. Therefore, the introduction of automatic postal scales and calculating devices was a fairly adequate solution to certain requirements. One such scale is US Patent No. 1986-523643738438.
Disclosed in the issue.

The postage scale uses digital technology to automatically determine the required postage for the required destination and type of transport according to the weight of the parcel to be transported. Postage data for each type of shipment and destination area is provided as a coded perforation of an adjustable postage code roll. That is, the postage codes are arranged on the roll in groups, each group representing a charge for a particular region and type of shipment combination. The operator advances the roll to select the appropriate rate group. When the appropriate rate group is selected, this group has a set of codes representing postage rates for various parcel weights.
A particular set of data is selected according to the weight of the parcel and the postage it represents is read out and displayed. When using such coded postage rolls, an operator or auxiliary automatic machine must advance the roll until the appropriate postage for the given type of transport and required destination area is obtained. . Of course, doing this requires careful operator management, and data roles take up a lot of space. Thus, while the overall time required to price a parcel has been significantly reduced compared to traditional mechanical scales that relied on the use of an operator's table, there is still room for reduction. Another example of an electronic postal scale is U.S. Pat.
No. 692988 I. In this system, the weight of the parcel is digitally displayed and an optical drum is used to store postage data. The addressable portion of this optical drum is selected as a function of parcel weight and destination area. Once addressed, the data stored at that location on the drum can be read out and used for display or to automatically control an appropriate fare indicating device. Another postal scale is disclosed in U.S. Pat. No. 3,635,297.

In this scale, a suitable selector switch is provided, by means of which the operator can select a particular type of transport and enter the Schiff code (ZIP code) corresponding to the region of destination.
e) can be specified. A postal scale according to claim 1, which includes a read-only memo.
5. said first means further comprising a type encoder connected to all said type selection switches for forming encoded information of an operated type selection switch, said encoded information being at least as part of an address of a memory portion; said type encoder generates an output signal that changes state when said encoded information is formed, and said detection means included in said inhibiting means typically generates an inhibiting signal and said 5. A postal scale according to claim 4, further comprising means for terminating the inhibition signal in response to a change in the state of the output signal.

6 said second means comprises a plurality of individually manually operable region selection switches, each of said region selection switches generating a corresponding signal when operated; and said inhibiting means The mailbox according to claim 1, further comprising means for detecting that the display unit is not operated, and upon detecting this, sends a prohibition signal to the memory reading unit to prohibit the display unit from displaying the display unit. Scales.

7. said second means further comprising a region encoder connected to all said region selection switches for forming coded information of the operated region selection switch, said coded information being at least as part of the address of the memory portion; said regional encoder generates an output signal that changes state when said encoded information is formed, and said detection means included in said inhibiting means -
7. A postal scale as claimed in claim 6, including means for normally forming an inhibit signal and terminating the inhibit signal in response to a change in the state of said output signal.

8. The prohibition signal further indicates that the region selection screen is operated. comprising comparator means for accepting a signal indicative of a selected area and a signal indicative of a selected type of transport and producing an output when these do not correspond, the comparator output signal being read out as a prohibition signal indicative of an improperly selected region; 7. A postal scale as claimed in claim 6, wherein the postal scale is supplied to the postal scale to inhibit displaying by said displaying means.

9. Each of the storage addresses in the memory means that does not contain postage data is provided with a predetermined storage signal, and the inhibiting means detects this predetermined storage signal when it is read from the memory means. 2. The postal scale according to claim 1, wherein a prohibition signal indicating an inappropriate address is sent to the memory reading means to inhibit displaying by the display means.

10. A method for determining and displaying postage charges for sending a parcel to a destination area according to the selected type of transport, comprising:
The postage charges for a given weight increment are then stored in addressable addresses in the memory, each of which addresses being provided in the memory portion corresponding to said type and being addressed as a function of the weight of the parcel and the region of destination. The method comprises performing a digital count as a function of the weight of the parcel, selecting said type and making it a digitally coded signal, selecting said destination area and making it a digitally coded signal, and selecting said destination area and making it a digitally coded signal; select a memory portion as a function of said coded signal of said destination area, address an address of said memory portion by combining said digital count and said coded signal of said destination area, and address a postal address from said address addressed by time sharing. reading rate data and providing said data to a display means by time sharing to display the appropriate postage rate depending on the type of transport, destination area and weight of the parcel; and {a) said digital count; (b) when the digital count indicates a negative weight; (c) when the type is not selected; {
d) when said destination region is not selected; {e) when said destination region and said type selection are not compatible; and (
f) the provision of data to said display means is inhibited when at least one or more of the following conditions exists: when no postage is stored at said address.

11 said digital counting process generates a first set of consecutive pulses when the parcel is placed on the scale and a second set of consecutive pulses when the parcel is removed from the scale; incrementing a count of a counter from a reference count in response to a group of pulses and decreasing a count of a counter in response to a second group of pulses, generating an output signal when the count falls below a reference count, and 11. The method of claim 10, wherein said inhibiting step uses said output signal as an inhibiting signal.

Detailed description of the invention TECHNICAL FIELD This invention relates to electronic postal scales.

More particularly, the invention provides for postage charges to be stored in various memory sections, each of the memory sections generally corresponding to the type of shipment of the parcel to the destination area, and each of the memory sections to store the postage charges. The present invention relates to such a postal scale that is configured with a plurality of memory locations that can be stored and addressable as a function of the weight of the parcel and the particular destination area. The invention further relates to various control mechanisms incorporated into postal scales to eliminate the possibility of incorrect or erroneous postage display. The invention also relates to an electronic postal scale which has a relatively simple construction, is low in cost and is able to take full advantage of the advantages of digital circuitry available in the form of IC circuits. Generally speaking, when trying to calculate the postage cost for a parcel to be mailed to a required destination, this fee (postage stamps) is determined not only by the weight of the parcel, but also by the area of its destination and the transportation. It must also be determined by the type of

In particular, each type of transport has a specific postage rate. Before the advent of automatic postal calculation machines, individuals would weigh the parcel to be sent, and once this was determined, they would consult a reference table for the type of transport chosen and record the charges specified by the required destination area. Appropriate postage rates were determined through this procedure. Comparing each type of transport required the individual to consult each reference table and record the corresponding charges obtained therefrom. Such postage calculation procedures were not only time-consuming, but also introduced various errors that would not have occurred if such look-up tables were used correctly. The introduction of automatic postal scales and calculating devices was therefore quite advisable for certain requirements. One such scale is disclosed in US Pat. No. 3,738,438. The postage scale uses digital technology to automatically determine the required postage for the required destination and type of transport according to the weight of the parcel to be transported. Postage data for each type of shipment and destination area is provided as a coded perf of an adjustable postage code roll. That is, the postage codes are arranged on the roll in groups, each group representing a charge for a particular region and type of shipment combination. The operator advances the roll to select the appropriate rate group. When the appropriate rate group is selected, this group has a set of codes representing postage rates for various parcel weights. A particular set of data is selected according to the weight of the parcel and the postage it represents is read out and displayed. When using such coded postage rolls, an operator or auxiliary automatic machine must advance the roll until the appropriate postage for the given type of transport and required destination area is obtained. . Of course, doing this requires careful operator management, and data roles take up a lot of space. Thus, while the overall time required to price a parcel has been significantly reduced compared to traditional mechanical scales that relied on the use of an operator's table, there is still room for reduction. Another example of an electronic postal scale is U.S. Patent No. 369
2988 No. 1.

In this system, the weight of the parcel is digitally displayed and an optical drum is used to store postage data. The addressable portion of this optical drum is selected as a function of parcel weight and destination area. Once addressed, the data stored at that location on the drum can be read out and used for display or to automatically control an appropriate fare indicating device. Another postal scale is disclosed in U.S. Pat. No. 3,635,297.

The scale is equipped with a suitable selector switch, which allows the operator to select the particular type of transport and select the Schiffcoat (ZIPcOd) corresponding to the region of destination.
e) can be specified. Read-only memories are typically partitioned according to the type of transport available. In the storage portion, postage is stored in individual addressable addresses, with the postage at each address being a function of weight and region. The above-mentioned postal scales, briefly described as prior art, have the common drawback of not being equipped with a satisfactory control system.

That is, these scales provide a weight display even when there is insufficient data to determine an appropriate charge. For example, some postal scales display rate fluctuations due to movement of the baseplate when a parcel is initially placed on or moved from the baseplate, but many of these scales do not When the scale base plate returns and passes through the initial reference position, it gives an unclear display. Preferably, this display is a negative weight display to prevent confusion for the operator or other persons. Additionally, some conventional postage scales will display the postage rate once the type and region have been determined, even if the parcel has not yet been weighed. This zero weight display is often confusing and it is preferable not to display the charge until the weight of the parcel has been determined. Still other conventional postal scales display charges without the data necessary to determine the charges being entered into the scale. For example, the display may occur even if the type of transport or destination area is not included. Since such a display is essentially meaningless, it is preferable not to display it until all necessary data has been entered. Conventional postal scales also suffer from the disadvantage that they have not adequately developed the possibility of using relatively inexpensive integrated circuits.

For example, for scales that use electronic or electromagnetic memory to store postage information, these memories store weight information at their addressable addresses! Usually, a type is used that stores all digital words representing everything. Postage is expressed in dollars and cents in the United States, so each
Typically a 2-digit decimal number, for example such a number can be represented in a 16-bit digital world. However, memories that can store 16-bit words are usually expensive. These expenses could be saved significantly if the digital world were made smaller and if time sharing or multiflex techniques could be used when reading postage from memory. For example, the above savings would be significant if the memory could be configured to have 8-bit storage, with each address location containing two words that are read out in a time-sharing manner. Therefore, it is an object of the present invention to provide an electronic postal scale that eliminates the drawbacks of the prior art.

Yet another object of the present invention is to provide an electronic postage scale having a rate display that inhibits display when one or more predetermined conditions occur.

Yet another object of the invention is to provide a postage scale having a rate display which inhibits display of the rate until all information necessary to determine the correct rate has been provided.

It is a further object of the invention to provide a postal scale which prohibits the display of charges until the parcel is placed on the scale.

It is further an object of the invention to provide a memory for storing postage data at addressable addresses, the postage being read from this memory when the parcel is placed on the scale and the necessary shipping information is provided. To provide a postal scale in which the display of charges is prohibited when the memory is improperly addressed. A further object of the present invention is to provide a low-cost electronic postal scale that uses solid-state integrated circuits throughout and has a simple structure.

A further object of the invention is to provide an electronic postage scale with a memory for storing charge data, which can be used in time-sharing or multiflex form and is thereby made inexpensive.

A further object of the present invention is to provide a data processing technique and its configuration that are particularly useful for use in electronic postal scales.
In accordance with the present invention, a method and apparatus are provided for determining and displaying postage charges for packages sent to a destination area by one of a plurality of types of transportation.

The memory then consists of a plurality of sections, each section corresponding to a particular type of transport and storing at an addressable address the postage rate corresponding to a given parcel weight. This address is determined by the weight of the parcel and the region of destination. Each address in this memory is comprised of a first portion and a second portion that respectively store a first portion and a second portion of postage data. Each portion of these data is read out and displayed in a time-sharing or multi-flex format. This postage readout and display may occur if there is no parcel on the scale, if the parcel is removed from the scale, if the destination area is incorrectly selected, if the transport type is incorrectly selected, or if the memory address is incorrectly selected. Specified which are prohibited when certain various conditions occur. The present invention will be described in detail below with reference to embodiments shown in the accompanying drawings.

Overall System FIG. 1 shows a block diagram of an electronic mail scale according to the present invention.

The scale has a base plate (not shown), on which the parcel is placed. Of course, this base plate is moved as a function of the parcel weight. Similarly, the encoder 10 is driven directly when the scale base plate is moved by a suitable movement mechanism (not shown). The encoder 10 is therefore moved as a function of the parcel weight. In the illustrated embodiment, encoder 10 is a rotatable disk consisting of two preferably concentric circular tracks 10a, 10b. Each of the tracks has a coded indicator. This coded indicator is
Directly proportional to the predetermined weight increment of the parcel, a number of indicators are rotated past the reference point in response to the weight of the parcel.
This indicator is detected by optical, electromagnetic, mechanical or electro-mechanical methods. For example, optical detection is preferred. In this case, the track 10a is formed by a repeating light and dark pattern of equal width. Similarly, the track 10b also has a pattern of equal width of light and dark, and the track 10a
There is a positional deviation from the pattern. Each track of this light-dark pattern is periodic, with the cycle being initiated by a dark pattern. For this cycle, the periodic pattern of track 10b is 90C' out of phase from the pattern of track 10a. When the parcel is placed on the base plate, the pattern of tracks 10a precedes the pattern of tracks 10b, assuming that the disk 10 is rotating counterclockwise. The phase difference between these tracks is used to detect the direction of rotation of the disk 10, ie whether a parcel has been placed or removed. Two optical detectors may be used in a single track to detect the direction of rotation of the disc. In the embodiment of FIG. 1, photodetectors 12a and 12b are arranged at reference points and correspond to tracks 10a and 10b, respectively.

These photoelectric detectors may be of any type known in the art and serve to detect light and dark patterns passing through them at fixed locations. Each of the photodetectors thus generates a pulse corresponding to the respective light/dark pattern of the tracks 10a, 10b. A weight encoder 14 is connected to these photoelectric detectors 12a, 12b and produces a digital output representative of the weight of the parcel in response to the pulses provided by the photoelectric detectors. For example, if the width of the dark pattern (or light pattern) has a weight increment of 1.5 ounces (approximately 42.5 f), the weight encoder 14 counts the number of increments and converts the number into a digital signal. occurs as. This of course corresponds to the effective weight of the parcel. Also, the width of each dark pattern (each light pattern) can be made in weight increments of 0.05 pounds (approximately 22.7 y).
In this case, weight encoder 14 serves to generate a digital signal indicative of the total number of 0.05 pound pulses produced by the photoelectric detector. The weight encoder 14 is
It is coupled to a zero weight detector 16 and a bed plate lowering detector 18 .

The zero weight detector 16 detects the condition in which the scale baseplate and thus the disc 10 has not moved from its original reference position, ie, when no parcel is placed on the baseplate. This means that when the disc 10 is in its reference position, the digital signal by the weight encoder 14 will indicate a parcel weight of zero. This particular digital signal is transmitted to the zero weight detector 16.
, which generates an appropriate inhibit output signal. This prohibition output signal is applied to prohibition circuit 60 as shown in FIG. It is clear that the base plate of the scale must be sufficiently sensitive so that it will move accordingly even if a lightweight parcel is placed on it. This limits the mechanical damping properties of the base plate. Therefore, when the parcel is removed from the base plate, the base plate returns to its original or zero weight position and, due to its inertia, overshoots this position to some extent. This overshoot at the zero weight position is considered to be the response of the scale plate to one negative weight of the parcel. The bed plate lowering detector 18 is provided to detect when the digital signal generated by the weight encoder 14 indicates this negative weight. Therefore, when the parcel is removed from the base plate and when the base plate is no longer pressed down and is in the downward position,
This bed plate lowering detector 18 issues an inhibit output signal. The prohibition output signal from this detector 18 is transmitted to the prohibition circuit 6 in FIG.
given to 0. The weight encoder 14 is also connected to an address generator 20.

This address generator 20 is connected to the weight encoder 14
converts the digital signal formed by the encoder into a format compatible with the memory 50 so that the stored postage information corresponding to the weight of the parcel as indicated by the output of the weight encoder 14 is read from the memory. The configuration and operation of memory 50 is detailed below. The memory stores the postage charges for each increment in the weight of the parcel, each destination area to which it can be transported, and the type of transport applicable. For example, if there are six applicable shipping types and nine possible shipping locations, there are up to 54 different postage rates for each weight increment. Of course, this theoretical maximum cannot be used in its entirety, as described below, and there are many transport types for which only a selected few of the nine ranges apply. In any case, the address generator 20 serves to form part of a memory address in which postage information corresponding to a given parcel weight is stored. When the digital signal produced by weight encoder 14 matches the memory address parameters, address generator 20 is not required and the signal from the weight encoder is used directly as part of the memory address. As mentioned above, the parcel is routed to the required destination according to the selected transport type.

In order to describe the postal scale according to the invention, the types of transport are priority mail,
UnitedParc
elService) (UPS) and ParcelPOst (PP). Furthermore, depending on the nature of the parcel, it may be placed in a BOOkrate.
) or blue label service (Bluelabel
service). A set of selection switches 30 are provided to correspond to these types of transportation and to enable selection of the necessary type. These switches include a priority selection switch 30a,
It includes a UPS interstate selection switch 30b, a UPS intrastate selection switch 30c, a PP selection switch 30d, a book rate selection switch 30e, and a blue label selection switch 30f. Although not necessary for an understanding of the invention, more or less types may be used. Switch 30a-30
f are conventional push button switches, mechanically or electrically coupled together so that only a single switch can be actuated whenever necessary. A suitable indicator light may also be provided to indicate which selection switch has been actuated. If necessary, this indicator light can be constructed as an integral unit with a selection switch, such switches being commercially available. Type encoder 3
2 is connected to all of the selection switches 30 and generates a coded digital signal representative of the particular type selection switch that has been actuated.

Therefore, the type encoder 32 is constituted by a discrete logic gate circuit or a commercially available encoder circuit. In any case, the type encoder generates a coded digital signal and supplies it to the address generator 34 by actuation of one of the switches 30.
However, when none of the type selection switches are actuated, type encoder 32 is activated and an inhibit signal is generated and provided to inhibit circuit 60 indicative of this.
Address generator 34 is configured to convert the encoded digital signal from encoder 32 into a suitable address signal and provide this to memory selection circuit 36.

This address generator 34 can be omitted if the encoded digital signal from the type encoder meets the input requirements of the memory selection circuit 36. As briefly mentioned above, memory 50 stores postage information stored according to the parcel's weight increment, destination, and type of shipment.

This memory 50 is divided into sectors, which correspond to the types of transport available. For example, one sector in the memory 50 corresponds to a priority mail. Also, other sectors are UP
Compatible with S. Therefore, in order to facilitate memory access and simplify the memory addressing circuitry, it is preferable to access only a single sector of the memory depending on the particular transport type chosen. This is the purpose of providing the memory selection circuit 36. Thus, when a particular type selection switch is actuated, the memory selection circuit 36 accesses the corresponding sector in memory, allowing the postage stored in the sector and determined by the parcel weight to be read out. . It will be clear to anyone knowledgeable about parcel shipping that the distance the parcel is transported determines the postage cost. This transportation distance is distributed to selected regions. As an example, the United States is divided into eight separate regions, which are connected to regional mail distribution centers.
Parcels are therefore sent from these regions, the shipping region, to other regions, ie, the destination region. Furthermore, parcels may be sent from one part of a shipping region to another part of the same region. In this case the parcel will be sent within the local area. Therefore, it is necessary to select the destination area of the parcel in order to determine the appropriate postage for shipping the parcel. To do this, a set of region selection switches 40 is provided, which include local region selection switches 40a1 region 1
Selection switch 40b1...Region 8 selection switch 40
It starts from 1. All of these region selection switches 40 are connected to a region encoder 42 similar to type encoder 32 described above. Therefore, the purpose of providing this regional encoder 42 is to generate a coded digital signal indicative of the particular regional selection switch that has been activated. Similar to the type encoder, when neither region selection switch is activated, the region encoder 4
2 is in an inactive state and supplies an inhibition signal to the inhibition circuit 60. The encoded digital signal from regional encoder 42 is provided to address generator 44 .

This address generator is the generator 3 mentioned above.
The address generator 20 may be similar to the address generator 20 if necessary. The generator is provided to generate a portion of the memory address signal and send this signal to the memory 50 to cooperate with the address signal from the weighted address generator 20 to access a particular address in the selected memory sector. ing. This allows reading of the postage at the addressed address of the selected memory sector. Address generator 44 may be similar to address generator 20, but may also be omitted if the regional encoder digital output signal is compatible with the memory address parameters. The output of the area address generator 44 is also provided to an error area detector 46.

Another input to this generator 44 is provided by memory selection circuit 36. The error area detector 46 is
It is configured to detect when an inappropriate region selection switch 40 is activated. As an example, it is known that only certain destination regions are applicable when UPS Interstate is selected as the shipping type. However, if UPS interstate switch 30b is actuated and an inappropriate region selection switch is pressed, false region detector 46 will generate an inhibit output signal indicating the inappropriate region. Similarly [? When S Blue Label shipping is selected, only some of the region selection switches can be properly pressed. If an inappropriate region selection switch is activated, the erroneous region detector 46 generates an appropriate inhibit output signal indicative of such improper selection. Therefore, this error area detector 4
6 may consist of a comparator 7 circuit which is driven by the memory selection circuit 36 when a predetermined type selection switch 30 is activated. When activated, the error area detector 46 compares the selected area indicated by the address signal from the address generator 44 to a preset area for a given transport type. When the selected area is outside the preset area, an inhibit output signal is generated from the error area detector. This prohibition output signal is supplied to the prohibition circuit 60. As mentioned above, memory 50 is preferably comprised of a plurality of sectors, each associated with a corresponding transport type.

The reason for this division of memory is explained below.
It is known that postage rates are subject to constant revision.

Typically, such revisions do not follow a fixed pattern. For example, postage rates for some types of shipping may be significantly higher than for others. Also, postage rates for transportation between some regions may be significantly higher than those for transportation between other regions. Furthermore, the charges for parcels over a certain weight may be significantly higher than the charges for parcels of lesser weight. . Therefore, in order to accommodate all of these revised postage changes and to anticipate future changes in postage rates, memory 50 may be divided into individually replaceable sectors. preferable. For example, the memory 50 is preferably a read only memory (ROM) of a semiconductor device such as MOS or CMOS. Preferably, these semiconductor sectors are located on a replaceable circuit board, such as a printed circuit card, to allow for easy removal and replacement of sectors requiring revisions. As an example, ROM is programmable ROM
and the stored postage rates are made reprogrammable when necessary, such as rate revisions. Such replaceable programmable ROM sectors are commercially available, and the contents of such ROMs can be changed, for example, by irradiation with ultraviolet light. Typically, sectors of memory 50 are divided into 50 sectors according to the type of transport. Although related, some of these types require relatively low memory capacity.

For example, a book crate has only a single destination region. The postage data that must be stored for the book crate is therefore for each weight increment! limited to postage charges. This relatively small amount of postage storage data can be located in other sectors of memory 50 and no separate sector need be provided for this booklet alone. However, apart from the intention of merging memory sectors and reducing the number of addressable memory locations, some memory locations are provided which are not needed for the storage of postage data. These addressable addresses are not used during normal postage determination operations. However, if an error occurs due to inadvertent operation of the postal scale, or if the scale is not functioning satisfactorily, such an unused address will be addressed. The contents of this address are not displayed, and an appropriate indication of the error or insufficient function is provided. To do this, this unused address in memory 50 is provided with a predetermined signal that is detected when this address is addressed. Such an address instruction of an irregular memory address in the memory 50 is supplied to the prohibition circuit 50 as a prohibition signal. As shown in Figure 1, memory 5
The output of 0 is connected to a display 80 via a suitable display drive circuit 70.

In a preferred embodiment of the invention, the display 8
0 is configured as a suitable observable optical display of the type in which the charge for the weighed parcel is shown in dollars and cents. Such displays include photodiode arrays, light emitting diode arrays, commercially available seven segment arrays, and the like. According to the configuration of the display 80, the display drive circuit 70 is adapted to the configuration and is configured to convert the data read from the memory 50 into a form suitable for driving the display. . If display 80 is a 7 segment array, drive circuit 70 is a code converter and a 7 segment driver.
If the data stored in the memory 50 is binary,
Drive circuit 70 converts this binary number into another form suitable for display. Alternatively, when memory 50 stores particular encoded data, drive circuit 70 converts the encoded format into a form suitable for display. Furthermore, the drive circuit 70 has an inhibit (or enable) input terminal connected to the inhibit circuit 60 and is configured to accept the appropriate signal generated by the inhibit circuit 60. Therefore, when an inhibit signal enters the inhibit circuit 60 from any of the circuits described above, a corresponding inhibit signal is applied to the drive circuit 70 to inhibit operation of the drive circuit. Or if no inhibit signal is output from any circuit connected to the inhibit circuit,
Inhibit circuit 60 provides an enable signal to drive circuit 70 . This interconnection of the inhibit circuit and the display drive circuit serves to prevent errors or insufficient display when certain conditions occur. Also, instead of the display and display drive circuit, the output of the memory 50 can be connected to a postage printing device, a billing calculator, an inventory calculator, and the like.

These additional devices allow automatic determination and application of the correct postage for the parcel to be transported and can simplify the calculation procedure. The operation of the entire system shown in the program diagram in FIG. 1 will be explained below.

First, the parcel is placed on the scale base plate, and one of the transport type selection switches 30 and one of the region selection switches 40 are pressed. The order of actuation of the switches is not relevant for proper operation of the illustrated device. Therefore, either of the above-mentioned switches may be operated first, or both switches may be operated simultaneously. Furthermore, the order of placing the parcel on the base plate and operating the switch does not matter. In any case, when one of the type selection switches 30 is pressed, the type encoder 3
2 generates a code signal representing a particular switch. This signal is converted into an appropriate address by address generator 34. In response to this addressing, the memory selector 36 selects the corresponding sector of the memory 50. When the region selection switch 40 is operated,
Regional encoder 42 generates a coded signal indicative of this, and in response address generator 44:
Generates part of a memory address.

If the destination area for the selected transport type is of a limited number, the output of the area address generator 44 (indicating the selected area) is preset for this type of transport in the error area detector 46. compared to other regions. If the selected region is compatible with the type of transport, the false region detector 46 will not send an inhibit signal to the inhibit circuit 60. However, if the selected region is not compatible with the selected transport type, e.g. if a Blue Label type is selected and the region 8 switch 401 is inadvertently operated (Blue Label for such region will not be available). ), the error region detector 46
An inhibit signal is generated and provided to inhibit circuit 60 to inhibit display of postage. When a parcel is placed on the scale base plate, the encoding disk 10 pivots in a direction indicating an increase in weight.

For example, disc 10 is rotated counterclockwise and track 1
The alternating bright and dark pattern of 0a and 10b is the photoelectric detector 12a.
, 12b, and a pulse is generated in response. This weight increment pulse enters the weight encoder 14 and is converted into a coded signal representing the parcel weight. For example, a weight encoder includes a pulse counting device whose count increases in response to transitions in the light-dark pattern. Therefore, when the scale base plate is pressed, the parcel weight encoding signal changes drastically. Changes in this encoded weight signal change the addressing provided to memory 50 by address generator 20. At this time, assuming that the memory sector is selected by the operation of the type selection switch 30 and the region data portion of the memory address is formed in accordance with the operation of the region selection switch 40, the change in the output of the address generator 20 will change the memory address. The addresses are sequentially designated, and the contents are read out and displayed on the display 80 via the drive circuit 70. The displayed postage therefore increases continuously with the placement of parcels on the scale platform. Due to the mechanical construction of the postal scale (which is not the subject of this invention), the coded disc is configured to pass through and return to the final point of its rotation.

Therefore, when the disk 10 is then rotated clockwise, the light and dark pattern of the tracks 10a, 10b will change to the photodetector 12a.
, 12b and changes in accordance with the weight code signal generated by the weight encoder 14. It is clear that this change in the weight code signal causes a corresponding change in the weight portion of the memory address by the address generator 20. Of course, this means a change in the displayed postage charges. Once the coding disk 10 is stable, the correct postage for the selected parcel weight for the type of transport, destination area is read from memory and displayed on the display 80. Once the correct postage is displayed, the parcel is removed from the scale bed.

This removal returns the scale base plate to its original reference position,
The coding disc 10 rotates clockwise. Due to this rotation of the coding disk, the coded signal by the weight encoder 14 decreases and the weight part by the address generator 20 also changes. Therefore, when the disk 10 rotates, the memory 5
0 different addresses are designated and the postage charges stored there are displayed accordingly. When the scale base plate reaches the reference position, the pattern detected by the photoelectric detectors 12a, 12b also occupies a position corresponding to zero weight. A suitable coded signal of zero weight is generated by the weight encoder 14;
This is detected by the zero weight detector 16. This zero weight detector 16 sends a prohibition signal to a prohibition circuit 60 and
0 prevents drive circuit 70 from activating display 80 no matter what data is read from memory 50. It is clear that due to the mechanical construction of the postal scale, the base plate and disk 10 do not come to a sudden stop in the reference position.

On the contrary, the coding disk 10 continues to move slightly clockwise. This results in a weight of 1 negative weight, and the appropriate code signal for this negative weight is sent to the weight encoder 14.
and is detected by the bed plate lowering detector 18. For example, if weight encoder 14 generates a signal between O and 100 pounds, this signal will change from a value of 0 pounds toward 100 pounds as the disk rotates past the reference point. The bedplate lowering detector 18 detects a coded signal with a value of 100 pounds, which in this case means that the bedplate is not depressed and has not been moved down one step. This is transmitted to the inhibit circuit 60 and the drive circuit 70 does not drive the display 80. Of course, once the coding disc 10 returns to its reference point, the output of the bedplate lowering detector 18 will also cease. Once the scale base plate and coding disc 10 have returned to their reference points, the postal scale is ready for the next rate determination. If the type selection switch 30 or region selection switch 40 is not operated due to inadvertence even though the parcel is placed on the base plate, the appropriate prohibition is sent from either switch to the prohibition circuit 60. It is clear that a signal will be provided.

This prevents confusing or half-hearted displays. Although not shown in FIG. 1, the display 80 or other display may display the actual weight of the parcel placed on the scale.

To do this, another display device may be connected to the output of weight encoder 14. Alternatively, the output of the weight encoder 14 may be further supplied to the display 80 via the drive circuit 70 via a suitable switching device. The weight display may be equipped with a tare circuit to display the net weight of the parcel. Weight Encoder FIG. 2A shows a logic circuit that is one embodiment of a weight encoder.

This logic circuit includes Schmitt triggers 106a and 106.
The b1 edge trigger 108a, 108b1 consists of a steering circuit 110, counters 112, 114, and a code conversion circuit 134. Shumit trigger 106a, 1
06b is the track 10a, 10b of the coding disk 10.
It accepts pulses formed according to the light-dark pattern of the The pulses supplied to the shot trigger 1 are generated by a photoelectric converter consisting in this embodiment of tracks 10a, 10b and respective phototransistors 104a, 104b. Phototransistor 104a
, 104b correspond to the light emitting diodes 102a and 102b, respectively. Other suitable light emitting devices may be used instead of light emitting diodes if desired. The light from such a light source to the phototransistor is blocked by the dark pattern on the coding disk, and the pulses produced thereby are fed from the phototransistor to the Schmitt trigger. Light sources 102a, 102b and phototransistor 10
4a, 104b are arranged on opposite sides with respect to the coding disk 10, so that light passes directly through the bright pattern of the encoder 10 and is blocked by the dark pattern. Alternatively, the light source and the phototransistor may be placed on the same side of the encoder 10 to achieve the same effect as described above with a reflected optical path. Shumit trigger 106a, 106b
has a conventionally well-known configuration and is configured to generate an output pulse when the output from the phototransistor exceeds a predetermined threshold level or trigger level. In the embodiment of the present invention, the Schmitt trigger 1 is used as a waveform shaping circuit that forms appropriate pulses in response to the phototransistor output determined by the bright/dark pattern on the encoder 10. Schmidt trigger 1
Outputs from 06a and 106b are designated A and B, respectively, and are supplied to steering circuit 110. Furthermore, the output pulse of the Schmitt trigger 1 is the edge trigger circuit 1.
08a and 108b. Edge trigger circuits 108a and 108b are well known in the art and each generates an output pulse in response to a transition in the output from the Schmitt trigger to which it is connected. For example, if the Schmitt trigger detects a bright-to-dark pattern transition and makes a positive transition, the edge trigger circuit will produce an output pulse at that transition time. Since the pattern of track 10a has a phase difference with respect to the pattern of track 10b, the pulses from each of the shot triggers and each of the edge triggers have a time difference from each other. This time difference between the edge pulse and the trigger pulse indicates the direction of rotation of encoder 10, ie, whether a parcel has been placed on or removed from the scale bed. As mentioned above, this indication can also be obtained by cooperating two phototransistors to a single track. The steering triggers 106a, 106b and the edge triggers 108a, 108b are all connected to the steering circuit 1.
10.

This steering circuit consists of a conventionally known gate circuit, which supplies a pulse to its first output when the encoder 10 is rotated counterclockwise, and supplies a pulse to its first output when the encoder 10 is rotated clockwise. It is configured to supply pulses to the output terminal of 2. These pulses are
The trigger output pulse generated by the trigger trigger 106a or 106b or the edge trigger 1
It can be an edge pulse formed by 08a or 108b. In any case, each pulse applied to the output of steering circuit 110 will represent a predetermined weight increment. For example, encoder 10
The dark-to-light or light-to-dark transition of the light-dark pattern is 1/1/
For a 2 oz increment, the number of pulses produced at one or the other output of steering circuit 110 is equal to the number of said transitions detected by phototransistor 104a or 104b, i.e. equal to the weight of the parcel. Become. For convenience of explanation, one output of the steering circuit will be referred to as an UP output, and the other output will be referred to as a DN output. In this case, an output is produced in the steering circuit 110 when the encoder 10 is rotated counterclockwise, i.e. for each 10f increment of parcel weight when the scale bedplate is lowered, and also when the baseplate is raised. Assume that a DN output occurs for each 1/2 oz. Of course, it will be appreciated that encoder 10 may be segmented to accommodate other suitable weight increments, if desired. For example, the width of each light or dark pattern, ie, the spacing between a light-to-dark and an adjacent dark-to-light transition, may correspond to 0.05 pounds. The UP output of the steering circuit 110 is connected to a pulse counter, which in this embodiment is connected to a series of counters 1
12, 114 and 116.

Each of these counters has a conventional up-down (UP) input and a down (DN) input.
/DN) counter. A pulse applied to the UP input increases the count of the UP/DN counter, and a pulse applied to the DN input decreases the count. If encoder 10 is configured to have 1/2 ounce increments, counter 112 counts the number of pulses in ounces and generates a 1 pound pulse when 16 ounces are counted. The force L counter 112 is therefore a gram counter and is configured as a binary counter. Since 1 pound is 16 ounces, and since the binary counter is configured to count 16 ounces before being set, conventionally known binary counters count 16 ounces.
Suitable as an X counter. The one pound pulses generated by counter 112 are counted by counter 114.

Counter 114 is preferably configured as a decimal counter that counts in decimal numbers the one pound pulses applied to it. This decimal counter 114 is 0~
It counts in increments of 9 pounds and when 9 pounds is counted it is reset to 0 when the next 1 pound pulse comes.
When reset, counter 114 generates a 10 pound pulse. This 10 pound pulse is counted in decimal notation by counter 116, which is a decimal counter. Counter 116 is substantially identical to counter 114. Therefore, counter 116 counts increments of 0 to 9 for each 10 pound pulse. Counting 9,
The next 10 pound pulse sets counter 116 to 100.
Generates a pulse of pounds.

As is clear from the counter row in FIG. 2A, counter 1
14 and 116 are shown as a one pound counter and a ten pound counter, respectively. The progressive counts obtained by these 1 pound and 10 pound counters represent the window weight of the parcel in decimal notation. Thus, the combination of 1 ounce counter 112, 1 pound counter 114, and 10 pound counter 116 allows for counting the total weight of the parcel in pounds and ounces. The contents of counters 112, 114 and 116 are:
The package is configured to provide a visual indication of parcel weight.

Each stage of the counter has a display drive circuit 120.
, 124 and 128, these circuits also drive weight displays 122, 126 and 130. Each of the display 1 is a conventionally well-known 7
The segment display may be a segment display, and each of the display drive circuits has a binary w-adic code (
The display circuit is configured to be driven by the BCD) signal. Therefore, decimal counters 114 and 11
6 are connected directly to drive circuits 124 and 128, respectively. However, since ounce counter 112 is preferably a binary counter, each stage of this counter is connected to display drive circuitry 120 via a suitable decoder 118. Decoder 118 may be a binary to W-base converter as is well known in the art. 1 of each
Depending on the contents of the ounce, one pound and ten pound counters, these are displayed by displays 122, 126 and 130. counters 112, 114
Since 116 and 116 are UP/DN counters, the total count number displayed will decrease to 0 or less depending on the number of countdown pulses applied to the counter column.

For example, when a pulse is applied to the DN output of steering circuit 110, the ounce, pound, and 10 pound counters decrease, for example, from 0 pounds, 1 ounce to 0 pounds, 0 ounces, and then to 99 pounds, 15 ounces. The transition from 0 pounds 0 ounces to 99 pounds 15 ounces corresponds to a negative weight of -1 ounce.

To detect this transition, the appropriate output terminal of ten pound counter 116 is used as an overflow terminal. 0 when the 10 pound counter 116 is decremented.
A change in count from 9 to 9 (meaning a weight change from 10 pounds to 99 pounds) provides an output pulse at B output terminal 117.

When the 10 pound counter 116 increases its count from 9 to 0 (change from 99 pounds to O pounds)
, the output pulse is applied to terminal 119.

These overflow output pulses are detected by flip-flop circuits 132 connected to respective overflow terminals 117 and 119. Flip-flop circuit 132 is a conventional set-reset bistable multivibrator having a set-reset input and 1 and 0 outputs. As is well known in the art, flip-flop circuit 132 is set in response to a pulse applied to its set input and reset in response to a pulse applied to its reset input. At the time of setting, a predetermined potential is applied to one output of the flip-flop circuit 132. Second
To facilitate understanding of the embodiment shown in Figure A, it is assumed that a relatively positive potential corresponds to the binary RlJ and a relatively negative potential corresponds to the binary RO. Alternatively, it may be considered that the binary RL indicates a relatively higher voltage than the voltage indicating the binary ROJ. Of course, you can also think the opposite way if necessary. In the former setting, when flip-flop circuit 132 is set, binary RlJ
is given to the output. This burner 1Jr1 is applied to each of the drive circuits 120, 124 and 128 and used as a prohibition signal. That is, when flip-flop circuit 132 generates the inhibit signal, the display driver circuits are inhibited from performing their respective displays. Therefore, when the counter column is reduced below the zero weight level, all display drive circuits are inhibited and any negative weights applied to the counter column will not be displayed. The inhibit signal formed at one output of flip-flop circuit 132 is further provided to the inhibit circuit described in more detail below with respect to FIG. 2C. When the increment signal enters the counter column and the negative count becomes O count, the overflow signal formed at the overflow terminal 119 resets the flip-flop circuit 132 and stops generating the inhibit signal. As mentioned in the embodiment of FIG.
The encoded parcel weight is used as part of the memory storage address.

Many of the memory devices available in postal scales are mostly compatible with binary code addresses. Therefore, since the pound and ten pound counters 114, 116, which indicate the pound portion of the parcel weight, are decimal counters,
This decimal counter must be converted to a binary representation. To do this, K-binary converters 13
4 are connected to decimal counters 114 and 116 to convert the binary W-adic code counts obtained by these counters into binary signals from which the appropriate memory address is derived. The individual outputs of converters 134 are connected to address generators 136, which are described in detail in the embodiment of FIG. 2C.
connected in parallel to. Finally, one of the converter outputs is connected to a memory selection circuit 222. converter 134
is of the type that produces a 7-bit output signal, the most significant bit output is the signal when the J°CD input to converter 134 exceeds 64 pounds. This signal indicating that the parcel weight is greater than or equal to 64 pounds is provided to a predetermined sector encoded in memory as described below. The operation of the logic circuit that makes up the weight encoder is quite clear;
Detailed explanation will be omitted.

When the encoder 10 rotates counterclockwise, which means that the parcel is placed on the base plate and the base plate is lowered, the indicators detected by the phototransistors 104a and 104b are connected to the Schmitt trigger and the edge trigger. through the steering circuit, which applies weight incremental pulses to the steering circuit's sweat output. This pulse is counted by the ounce counter 112, which is 1
When it comes to pounds, 1 pound pulse is 1 pound counter 11
given to 4. This pulsing continues for the counter rows so that the ounce, pound, and ten pound counters are incremented according to the weight of the parcel. As the counts in these counters increase, the corresponding displays 122, 126 and 130 also increase. Encoder 10 may rotate beyond its final steady state position. When this occurs, the encoder rotates in the opposite direction, ie clockwise, toward this steady state position. During this clockwise rotation, the pulses from phototransistors 104a and 104b will cause a pulse to be generated at the DN output of steering circuit 110. This pulsing of the DN output causes the counts in each counter to decrease until the correct parcel weight is stored in the ounce and one pound counters. Each display will then display the correct parcel weight. The pound portion of the weight count is converted from BCD format to binary code in converter 134. Since ounce counter 112 is a binary counter, such conversion is not necessary. When the parcel is then removed from the scale baseplate, the baseplate returns to its reference point with clockwise rotation of the encoder 10.

This clockwise rotation means that the count in the counter column decreases to O. However, due to the mechanical structure of the device, the encoder crosses the reference point and overshoots the zero point. This causes the counter column to decrease below the O weight level and an overflow pulse is applied to the overflow output 117 to load the flip-flop circuit 1.
32 and drive stages 120, 124 and 128 are inhibited. When the encoder finally returns to its reference point, an overflow pulse is applied to terminal 119 to reset the flip-flop and stop generating the inhibit signal. As the contents of the 1 pound and 10 pound counters 114, 116 change, the binary signal from the BCD to binary converter 134 also changes.

When the indicia of tracks 10a, 10b are spaced at 0.05 pound intervals, ounce counter 112 is replaced, for example, by a 0.1 pound decimal counter. This decimal counter is a counter similar to counters 114 and 116. Therefore, decoder 118 is not required. Also, to form a binary code memory address,
Each stage of this 0.1 pound counter will be connected to a BCD-to-binary converter 134. Type and Region Encoders The transportation type encoder 32 and destination region encoder 42 of FIG. 1 are shown in detail in FIG. 2B.

Type selection switch 30 is push button switch 30a
~30f, these switches are interlocked so that only a single switch is effectively activated. This interlock can be implemented mechanically or electrically, but in the illustrated embodiment an electrical interlock is employed. In particular, each pushbutton switch consists of an upper pair of contacts and a lower pair of contacts, with each pair of contacts electrically connected to a spring-loaded contact. When all pushbutton switches are in the normal or inoperative position and each spring-loaded contact is in contact with the upper pair contact, the electrical circuit is connected in series from a suitable power supply at operating voltage +. Formed into an upper pair contact. One of the upper pair of contacts in each pushbutton switch is commonly connected to the lower pair of contacts, so that when one of the spring-loaded contacts is pressed, the operating voltage is applied to the lower pair of contacts. Added. For example, when button 30d is actuated, the series connection of the upper pair of contacts is broken and the actuation voltage + is applied to pushbutton 30d.
a, 30b, and 30c to the lower pair of contacts of the button 30d. A separate signal line connects the lower pair of contacts of each pushbutton switch 30a-30f to a corresponding input of type encoder 204.

Therefore, depending on which type selection switch is pressed,
The operating voltage +V is input to the type encoder 20 via the signal line.
given to 4. In the illustrated embodiment, six type selection pushbutton switches are provided. Accordingly, type encoder 204 generates a coded signal indicative of the particular pushbutton switch 30 that was pressed. 6
As any one of the three pushbutton switches is pressed, type encoder 204 produces a three-bit encoded signal identifying which switch was actuated.

This 3-bit encoded signal can be a binary code, Km code, etc. As an example, the type encoder 204 may be
It can be a 3-bit encoder of the model 14532 type from aSemiconductOrDivisiOn). This type of encoder has two output terminals, one for a control output and one for a pulse output terminal, and output signals such as a control signal and a pulse signal are generated when the encoder receives an input potential at one of its input terminals. It is configured to Alternatively, the type encoder 204 may be a conventionally known gate circuit configured as a 3-bit encoder, preferably provided with a gate output terminal. A temporary storage circuit 206 is connected to type encoder 204 and receives the 3-bit encoded signal of the particular type selection switch pressed.

This memory circuit 206 is manufactured by National Semiconductor Company (NatlOrlalSemiconductor).
COrp. ) model 74C173 can be used. Binary storage circuits typically have 4-bit storage. However, since the storage circuit 206 only stores 3-bit signals, the remaining storage capacity is limited to the type encoder 20.
4 is used to indicate whether a type code is stored. This indication is used to detect whether the type selection push button has been properly actuated.
The input to the fourth and final stage of storage circuit 206 is therefore connected to the other three stages and is driven when a binary signal enters any of these stages. Type storage circuit 206 further includes a clear or reset input, an enable input, and a trigger input.

The clear input terminal receives a clear signal and resets all of the memory circuits to their initial states. The enable input terminal of the type storage circuit 206 is connected to one of the additional outputs, such as the control output terminal of the type encoder 204. The enable input terminal receives the enable signal to condition the type storage circuit 206 to accept a 3-bit type encoded signal. To store this signal, a trigger signal must be applied to the trigger input of the type storage circuit. This trigger input terminal is connected to a one-shot or strobe circuit 204, which will be described below. It is connected to a display 210 via a decoder drive circuit 208.

As this decoder drive circuit, RCA Semiconductor Division (RCA Semicond.
uctOrDivisiOn) model 4028 is suitable. The display 210 preferably consists of an array of light emitting means, such as lamps, each lamp being associated with a type of transport. As is well known in the art, these lamps are incorporated into an integral structure with a type selection switch, which indicates which switch is pressed. It indicates whether the lamp has been stored on behalf of the memory circuit 206.Of course, it is not necessary to include the lamp in the same housing as the pushbutton switch.Many other configurations can be provided. Selection switch 3
A region selection switch 40 similar to 0 is shown.

Local, 1, 2, 3, 4, 5, 6, 7, and 8 regional push button switches 40a-401 are each connected to a signal line. In addition, BOOkrat
e) Push button switch 30e is diode 203
via a signal line that connects to the local regional switch 40a. This connection causes the local area line to be energized whenever the booklet switch 30e is pressed. All of the signal lines of the region selection switch are connected to corresponding inputs of the region encoder 304.

This encoder 304 is the type encoder 20 described above.
4 is a 3-bit encoder nearly identical to .

The encoder 304 also includes two additional terminals, a control output terminal and a pulse output terminal.
These terminals generate a control signal and a pulse signal, respectively, when the regional encoder is driven by an actuation voltage applied to any of the regional encoder's inputs. The 3-bit region code signal formed by region encoder 304 is provided to region storage circuit 306. This memory circuit 306 is almost the same as the type memory circuit 206 described above, and constitutes a four-stage memory device capable of storing a 4-bit signal. In the embodiment of the invention shown in FIG. 2B, nine region selection switches 40 are provided.

A 4-bit digital signal is required to represent the nine region selection switches.

However, since the regional encoder 304 forms a 3-bit signal, it becomes necessary to encode the fourth bit when the ninth selection switch 401 is operated. Encoding this fourth bit can be accomplished by connecting the lower pair of contacts of pushbutton 40i to the input of the fourth stage of local storage circuit 306. Therefore, whenever push button 401 is pressed, a corresponding signal is stored in region storage circuit 306. Regional storage circuit 306 further has a clear or reset input terminal for accepting a clear signal, the purpose of which will be explained below.

This clear signal serves to erase the contents of the local memory circuit. This regional storage circuit 306 also includes an OR circuit 314
It has an enable input terminal connected via a pushbutton switch 401 and an additional output terminal of the regional encoder 30. Similar to type storage circuit 206, region storage circuit 306 is configured to store the code signals that are applied to the four stages when the enable input signal enters the enable input terminal. Finally, the region storage circuit 306 includes a trigger input terminal that accepts a trigger signal, thereby allowing the region storage circuit 306 to store the encoded contents of the operated region selection switch 40. The trigger input terminal is connected to the one-shot circuit 214 via an inverter circuit 312. The output of the region storage circuit 306 is sent to the decoder drive circuit 3.
08 to an appropriate area indicating device 310. The decoder drive circuit 308 is substantially the same as the decoder drive circuit 208 described above. The instruction or display device 310 is also similar to the type display device 210. The display device 310 thus comprises suitable light emitting devices such as lamps, each of which displays the corresponding destination region selected by operation of the region selection switch 40. It will be appreciated that the decoder drive circuit 308 receives the stored 4-bit code signal and drives a particular one of the area indicator lamps in response to the 4-bit code. As the drive circuit 308, R.C.K. model 4028 can be used. Regional memory circuit 3
Regardless of the contents of 06, there are some predetermined conditions in which it may be desirable to disable the decoder drive circuit 308 so that none of the regional display devices 310 are driven.

These states include a state where the type is selected as bookcrate or blue label and none of the area selection switches 40 are activated. Therefore, a decoder disabling circuit is provided, which circuit is connected to the OR circuit 316.
, 320 and a flip-flop circuit 318.
OR circuit 316 has a pair of inputs each connected to pushbutton switch 401 and one of the additional regional encoder output terminals. This OR circuit 316
The output of is connected to the set input of flip-flop circuit 318. Another OR circuit 320 has three OR inputs. Its first input is connected to the O output of flip-flop circuit 318, its second input receives a signal when the book rate is selected, and its third input receives a signal when the blue label is selected, respectively. It is configured. The second and third inputs can be connected directly to pushbutton switches 30e and 30f or to the corresponding outputs of type encoder 204 or type storage circuit 206, but the OR circuit 32
Preferably, the zero input is connected to the appropriate output terminal of memory selection circuit 222. The output of OR circuit 320 is connected to the disabling input of decoder drive circuit 308. Flip-flop circuit 318 is preferably a set-reset type circuit whose reset input receives the clear or reset signal provided to type and region storage circuits 206 and 306.

This clear signal is generated by OR circuit 148.
As can be seen, the output of this OR circuit is commonly connected to the respective input terminals of region storage circuit 30 and type storage circuit 206 as well as to the reset input of flip-flop circuit 318. This OR circuit 148 receives at one of its input terminals a reset pulse from a reset pushbutton switch 150. The reset pushbutton switch 150 has a pair of normally open contacts which, when heard, provides a positive potential to the OR circuit 148. The same input terminal of this OR circuit is also connected to the + power supply via capacitor 152. The purpose of such coupling is to provide a reset signal to OR circuit 148 when power is turned on to the mailing scale.
The other input of the OR circuit 148 is connected to the overflow terminal 117 of the 10 pound counter 116 described above. The trigger signals provided to the respective trigger input terminals of type and region storage circuits 206'' and 306, as previously described, are provided by one shot circuit 214.

The reason for this one-shot circuit is to avoid storing erroneously generated type and area code signals. For more information, see Push Button Switches 30 and 4.
Errors caused by 0 to 1 bounces are avoided by the one-shot circuit 214 providing a trigger signal to each storage circuit. This switch contact bounce provides an incomplete and unreliable signal to the select switch line. This incomplete signal leads to coding errors and the selected type and region being stored incorrectly. This contact bounce problem can be avoided by using a one-shot circuit 214 whose input is connected to the OR circuit 21.
2 to one of the additional output terminals of the type encoder 204, one of the additional output terminals of the regional encoder 304, for example to a respective pulse output terminal. Furthermore, the third input of OR circuit 212 is connected to one of the normally open contacts of pushbutton switch 401. Before explaining the types and operation of regional encoder circuits, it is important to note that the OR circuit used here has a conventionally well-known configuration.
It is noted that the input signal is what forms the output signal when applied to one or more of the input terminals of the OR circuit. For convenience of explanation here, the OR circuit is configured to generate binary RlJ when binary RlJ is applied to any of its input terminals, and to generate binary ROJ when binary RlJ is applied to none of its input terminals. It is assumed that The inverter circuit used here is a conventionally well-known logic inverter, which receives binary ROJ and forms binary r1,
It receives binary r1 and forms binary ROJ. In operation, it is assumed that all of the lower pair of contacts of the type selection switch 30 are in an open state.

Similarly, it is assumed that all lower contacts of the region selection switch 40 are also in an open state. Initially, neither type encoder 204 nor region encoder 304 is driven and type and region storage circuits 206 and 30 are activated.
Assume that each of 6 is empty. At this time, it is assumed that the flip-flop 318'' is set and the binary RlJ is supplied from its O output to the disabling input of the decoder drive circuit 308 via the OR circuit 320. When a type selection switch such as a mail switch 30a is operated, the normally open contact is closed and a signal +V is applied via the priority mail signal line to the input of the corresponding type encoder 204.When the priority mail switch 30a is operated. It should be noted that when the normally closed upper pair contacts are opened, the potential to all of the other switches 30b-30f is removed. Even if you operate the type encoder 2
04 will have no effect. When this signal +V is applied to the priority mail input of the encoder, its 3-bit encoded content is formed and applied to type storage circuit 206.

Simultaneously, the type encoder 204 is activated, thereby providing an enable signal to the enable input of the type storage circuit. Additionally, a pulse signal indicating that type encoder 204 is being driven is provided from another output terminal of the encoder via OR circuit 212 to activate one shot circuit 214. After a suitable delay time, one-shot circuit 214 determines that its positive edge is stored in type storage circuit 206.
generates an output pulse that acts as a trigger signal. At this time, the 3-bit encoded content is stored in the type storage circuit. Once this encoded content is stored, the decoder drive circuit 208 drives the corresponding type display to indicate that the priority mail switch has been operated. The stored encoded contents of the transportation type are also supplied to the memory selection circuit 222 and the priority type detection circuit 220. This circuit is illustrated in the embodiment shown in FIG. 2C. In the embodiment described herein, type storage circuit 206 stores a 4-bit signal and type encoder 204 is simply a 3-bit encoder.

Accordingly, the fourth stage of storage circuitry, which is not used for storing coded type content, is activated when the type storage circuit is triggered and enabled to accept and store the coded signal. Ru. This fourth stage is connected to the OR circuit 142 via an inverter circuit 216. The fourth stage of type storage circuit 206 is activated only when the storage circuit is triggered to receive and store signals. At this time, the output of the inverter 216 is, for example, binary RL RO. Convert to J. The trigger signal of one shot circuit 214 has a finite width. When this trigger signal terminates, its terminal end is inverted by inverter circuit 312 to provide a positive transition to the trigger input terminal of regional storage circuit 306. However, at this time, the area selection switch 4
When none of the 0's are activated, the regional encoder 304 is not being driven and therefore no enabling signal is provided to the enabling input terminal of the regional storage circuit. Therefore, unless the trigger signal is in a normal state, the trigger signal is stored in the local memory circuit 30.
6 has no effect. Now region selection switch 40
For example, press button 40d corresponding to region 3.
When activated, this provides a signal to the corresponding input of regional encoder 304 via the signal line. When properly activated, region encoder 304 sends the 3-bit encoded content of the actuated region selection switch to region storage circuit 306 and, via OR circuit 314, to the enable input of the region storage circuit. A signal is sent to the one-shot circuit 214 via an OR circuit 212.
A drive signal such as a pulse signal is sent to the Since the region 8 selection switch 401 is not actuated (the region 3 switch was operated), the corresponding fourth bit signal of the binary ROJ is provided to the fourth input of the region storage circuit 306. After a predetermined delay time following activation of one-shot circuit 214, the trigger pulse thereby produced is inverted and applied to the trigger input terminal of local storage circuit 306.

This inversion provides a negative transition to this input terminal,
This memory circuit is prevented from storing the encoded contents of activated region selection switches. However, once the one-shot pulse is completed, inverter circuit 312 provides the necessary positive transition to the trigger input terminal of the region storage circuit, which causes the region storage circuit to store the 4-bit encoded contents of the activated region selection switch. do. When regional encoder 304 is activated, the enable signal provided to the enable input of regional storage circuit 306 via OR circuit 314 is also provided to the SET input of flip-flop 318 via OR circuit 316.

It is clear that flip-flop 318 is only set when the region selection switch is correctly activated. When in the set state, the signal applied to the zero output of the flip-flop is converted from binary RlJ to binary RO. This binary ROJ removes the disabling signal applied to the disabling input of the decoder drive circuit 308 and decodes the encoding stored in the region storage circuit 306 to drive one of the corresponding region display devices. It works effectively. A visual representation of the selected region is thus possible. The setting of flip-flop circuit 318 also removes the inhibit signal provided by the flip-flop to OR circuit 142, which is an inhibit circuit.
After the type selection switch and/or region selection switch is operated, if the operator wishes to change the type of transport or destination region, the type and region storage circuit 206
It becomes necessary to clear 306 and select the appropriate type and region.

Clearing of these memory circuits is accomplished by actuating a reset pushbutton 150 which sends a reset signal to the clear input terminal of the respective memory circuit via an OR circuit 148. Alternatively, each of the other types or region selection switches may be connected to the memory circuit 206 or 3.
It may be activated without clearing 06. For example, pressing the parcel post push button 30d as another type switch activates the type encoder 204 and sends the corresponding encoded content to the type storage circuit 206 along with an enable signal. Actuation of type encoder 204 produces a final trigger signal by one shot circuit 214 to the trigger input terminal of the type storage circuit. The coded content of the changed type is thereby stored and displayed on the type display device 210. However, since the region selection switch is not pressed, the stored contents and display of the selected region remain unchanged. This is done by the regional encoder 30 when there is no active region selection.
4 is because it is not driven. Therefore, the regional memory circuit 3
06 cannot store new region contents. Therefore, the previously stored region contents are retained. After the appropriate type and region have been selected and the parcel has been placed on the scale base plate. The appropriate postage is then read from memory and displayed.

The operator then removes the parcel from the base plate. As described with respect to the configuration of FIG. 2A, when a parcel is removed, the scale baseplate overshoots its reference point and the encoder 10 causes the counter column to decrease so that the counter indicates a negative weight. be rotated. That is, the overflow terminal 117 of the 10 pound counter forms the overflow signal. This overflow signal is sent through OR circuit 148 as a clear signal to type and region storage circuits 206 and 306. Therefore, upon completion of a postage determination operation, the type and region storage circuitry is automatically cleared in preparation for the next operation. Assume that the book button 30e is pressed instead of the priority mail push button 30a.

It is clear that in this case, in addition to driving the type encoder 204, the signal applied to the book rate signal line is also applied via the diode 203 to the local area signal line. Therefore, by simply pressing the booklet push button 30e, the contents of the appropriate type and region are stored in the type storage circuit 206 and the region storage circuit 306, respectively. The encoded contents of this local region are used in combination with the encoded contents of the parcel weight, as will be explained later, to address the appropriate address in the relevant sector of memory. Since book crates usually have no association with other regions, region storage circuit 306
It is preferable to disable the decoder drive circuit 308 from driving the lamps in the local area according to the local area encoding contents stored in the local area. To do this, a signal indicative of the selected booklet type is applied via OR circuit 320 to the disabling input terminal of decoder drive circuit 308. Region 8 when Priority Mail or Parcel Post is selected as the transport type.
It is assumed that the push button 401 is pressed.

Since none of the other region selection switches are pressed, region encoder 304 is not activated. Therefore, the regional encoder 304 sends the enable signal to the regional storage circuit 306.
and does not drive one-shot circuit 214. However, when the push button 401 of region 8 is operated, a corresponding signal potential is applied to the fourth stage of the region storage circuit 306, and an enable signal is applied to the enable input terminal of the region storage circuit via the OR circuit 314. . Furthermore, an appropriate potential can be set using this push button 401.
is applied to the OR circuit 212 from the one-shot circuit 21
4 is activated, thereby providing a trigger signal to the trigger input terminal of the regional storage circuit 306. For this purpose, the coded contents of region 8 are stored in the region storage circuit. This potential applied to the region 8 signal line also sets a flip-flop 318 via an OR circuit 316 to remove the disable signal from the decoder drive circuit 308 and is normally supplied from the flip-flop circuit to an OR circuit 142. Remove the inhibit signal that is present. It is clear that regardless of the order of actuation of the type selection switch and the region selection switch, the appropriate type and region contents will be stored in the respective storage circuits.

For example, when the type selection switch is operated first, the one-shot circuit 214 is driven and a trigger signal is applied to the type storage circuit 206, whereby the coded contents of the selected type are stored. If the region selection switch is actuated before the termination of this trigger signal, the encoded region content will be stored in region storage circuit 306 after the end of this one-shot pulse. This is because the negative transition of the one-shot pulse is inverted and provided to the local memory circuit as a trigger signal. Of course, when the region selection switch is actuated at the end of a one-shot pulse, the one-shot circuit is re-driven by region encoder 304 to send the appropriate trigger signal to the region storage circuit. If the area selection switch is actuated first, the encoding content of the subsequently actuated type selection switch will be stored in the type storage circuit if the type selection switch was activated prior to the generation of the trigger signal of the one shot circuit 214. 206
is memorized. However, when the type selection switch is actuated after the trigger pulse of the one-shot pulse is formed, type encoder 204 again drives the one-shot circuit to provide another trigger signal to the type storage circuit.
The delay time and pulse spacing associated with one-shot circuit 214 is very small for erroneous operation due to manual operation of the type and region selection switches. Therefore, the possibility of such an erroneous operation is hardly a problem. Address Circuit FIG. 2C shows an address circuit for a memory used in a postal scale according to the present invention.

As previously mentioned, the memory is a programmable ROM consisting of multiple sectors, each sector being constructed on a removable printed circuit or board. Each sector stores postage data for each weight increment and each destination area. The coded content of the type stored in the type storage circuit 206 is thus used for the selection of the appropriate memory sector and the binary (binary) content of the parcel weight formed by the K-to-bin converter 134. ) signal is used in combination with the selected destination region's encoding contents stored in the region storage circuit 306 to address the appropriate address of the selected sector. consists of a memory selection circuit 222, a 1/2 pound detector 146, an address coater 322, and an address generator 136.The memory selection circuit 222 consists of a decoder circuit having individually drivable output terminals; selectively drives one of the output circuits in response to a binary signal applied to its input terminal.

As explained below, the memory consists of five independently accessible sectors, each sector having an enable input connected to one of the memory selection outputs 1, .

An example of such a memory selection circuit is Model 14556 manufactured by Motorola, which is constructed by combining it with a conventionally known gate circuit. An input to memory selection circuit 222 is connected to type storage circuit 206 to receive the stored encoding contents of actuated type switch 30. Depending on the selected type of encoded content, one of the output terminals 1-V is driven.
As previously mentioned, some types of transportation have limited destination areas.

Therefore, the amount of postage data to be stored for these types is relatively small. It is therefore economical to divide a single memory sector for two or more transport types. Additionally, for types requiring postage storage capacity that exceeds the storage capacity of one memory sector, excess postage data is stored in other sectors. Memory selection circuit 222 has the ability to take these conditions into account by providing a drive signal to the appropriate one of its drive output terminals. For example, both Parcel Post and Priority Mail include parcels up to 70 pounds. However, Parcel Post has a much larger number of segmented destination areas than Priority Mail. So for example Parcel Post as one example? Postage data for parcels over pounds is stored in the appended sector. Memory selection circuit 222 performs other sector selections to enable this storage configuration when a parcel post is selected. For example, the memory selection circuitry has the ability to select a parcel post memory sector when a parcel post switch is operated and the parcel weight is less than 64 pounds, and another when the parcel weight exceeds 64 pounds. It has equal power to select additional memory sectors. This capability is obtained by providing an additional input to the memory selection circuit from the aforementioned most significant bits of binary converter 134. Thus, when the parcel weighs more than 100 pounds, the appropriate signal is sent to the memory selection circuit 22.
This additional input of 2 is given. As another example of the need for flexibility in selecting or accessing specific memory sectors, in addition to providing a flat rate classification for pound weight increments of parcel weight, priority mail In that case, 1/2
Postage classification will be enabled for parcels up to 5 pounds in pound increments. This added 1/2 pound of postage data would exceed the storage capacity of the priority mail sector of memory. In this case, priority mail 1/2 pound postage data is stored in another sector. Therefore, when priority mail is selected and postage must be determined based on the 1/2 pound increase in parcel weight, this other sector must be accessed. This is implemented by providing yet another input connected to the 1/2 bond detection circuit 146. As discussed below, the 1/2 pound detection circuit determines whether the parcel weight exceeds or falls below the 1/2 pound weight increment. Detects the input signal and sends the appropriate input signal to the memory selection circuit 2.
22 to enable the memory selection circuit to access the appropriate memory sector in which the 1/2 pound postage is stored. 1/2 pound detection circuit 146
is configured to form, for example, a binary r1J when the parcel weight exceeds a 1/2 pound increment and a binary roJ when the parcel weight falls below a 1/2 pound increment.

In addition to being connected to the input of the memory selection circuit 222, 1/
The output of the 2 pound detection circuit is connected to a specific memory sector described below. Since 1/2 pound weight data is significant in determining postage only when Priority Mail is selected as the type of transport, the 1/2 pound detection circuit 146 detects whether Priority Mail is selected. enabled only when

Accordingly, the 1/2 pound detection circuit has an enable input terminal that accepts the enable signal generated by the priority detection circuit 220. As is clear from the figure, the priority detection circuit 220 is connected to the type storage circuit 2.
It has multiple inputs connected to opposite stages of 06.
The priority detection circuit includes a gate circuit configured to detect when the encoded content stored in the type storage circuit 206 corresponds to a priority mail. The 1/2 pound detection circuit also includes an input terminal for accepting data indicative of parcel weight.

This input terminal is connected to an ounce counter circuit 112 to accept data indicating the parcel weight in ounces. Of course, if this ounce data indicates a parcel weight between 9 and 15 ounces, the 1/2 pound detection circuit 146 will indicate that the parcel weight is greater than 1/2 pound. Also, when the ounce data indicates that the parcel weight is between 0 and 7 ounces, the 1/2 pound detection circuit indicates that the parcel weight is less than or equal to 1/2 pound. If the ounce data is a mediocre value of 8 ounces for the parcel weight, an ambiguous factor will exist. This ambiguity is based on the fact that the parcel weight could be between 7 ounces and 8 ounces or between 8 ounces and 9 ounces when ounce counter 112 makes a count corresponding to 8 ounces. It is. Of course, the parcel weight is 7
When the parcel weight is between 8 and 8 ounces, the weight is less than or equal to a 1/2 pound increment, and when the parcel weight is between 8 and 9 ounces, it is more than or equal to a 1/2 pound increment. To avoid this ambiguity, the position of the encoder disc is detected. More specifically, the Schmitt trigger 106a,1
A pulse with 06b is used to indicate whether the parcel weight is between 7 and 8 ounces or between 8 and 9 ounces. If track 10a has a phase difference with respect to track 10b by 900 degrees during the cycle of the light-dark pattern, then the pulse
6a and 106b for 2700 of this distance. Since each of these pulses corresponds to a 1/2 ounce increment, the only time that either Schmitt trigger 106a or 106b produces an output pulse is when the parcel weight is slightly less than a 1/2 ounce increment. The OR circuit 149 therefore detects when none of these shot triggers produce an output signal, and this information is provided to the 1/2 pound detection circuit to avoid the ambiguity described above. By detecting the relative position of the encoder 10 in this way, 1
The /2 pound detection circuit can distinguish between 8-ounce and 8+ ounce weight increments. Inputs to OR circuit 149 are provided from respective Schmitt triggers 106a and 106b. Another input to the 1/2 pound detection circuit 146 is provided by the BCD-to-binary converter 134;
Indicates the weight of the parcel in pounds.

Since the 1/2 pound postage data does not apply to parcel weights of, for example, 5 pounds or more, it is useful to detect when the weight exceeds this limit and the 1/2 pound detection circuit is no longer used.

Thus, when the binary signal in pounds of parcel weight provided by transducer 134 exceeds the aforementioned weight limit, for example 5 lbs., 6 lbs., 7 lbs. or 8 lbs. or any other required weight, 1/2 lb. Detection circuit 146
no longer gives the 1/2 pound information described above. 1
The /2 pound detection circuit 146 was configured as a gated circuit to utilize all of the weight information provided, but preferably uses read only memory (ROMQ).

A ROM that can be used as a 1/2 pound detection circuit is manufactured by Harris Intertype (Harr'IsSemi).
cOrKluctOrDivisiOnOfHarri
sIntelypeCOrp. ) model HDlO24
There is.

When such a ROM is used, the ounce counter 1
The ounce signal from 12, the encoder disk position signal from OR circuit 148, and the pound signal from binary converter 134 can all be used to address various memory locations. According to each addressed memory location, the stored data indicates whether the parcel is over or under 1/2 pound increments.

This is the 1/2 pound weight information provided by the 1/2 pound detection circuit 146 to the memory selection circuit 222 and to the particular sector of memory. Once the appropriate sector of memory has been selected, it is necessary to address the specific storage address of the sector in order to read the postage stored in this sector. Since the postage rate for a given type of transport is determined by the weight of the parcel and the particular destination area, the postage information is stored in the memory sector as a function of the parcel weight and the destination area. The addressing for each memory location is therefore a combination of the parcel weight determined by the counter column and the destination region selected by actuation of a particular region selection switch 40. For this purpose, an address generator 136 and an address coater 322 are provided. Address generator 136 forms a multi-bit address according to binary information of the parcel weight.
Therefore, one embodiment of address generator 136 is B
It is configured as a code converter with a plurality of inputs connected to the output of the CD-to-binary converter 134 and a plurality of outputs connected to corresponding address lines of each of the memory sectors. The purpose of the address generator is to convert the binary information of the parcel weight into a code that fits into the memory sector. As such a code converter, Motorola Model 14008 can be used. Of course, if the memory device is addressable by the binary code produced by converter 134, address generator 136 is not needed. Alternatively, the address generator may be constructed from conventionally known gated circuits suitably interconnected to provide code conversion capabilities. Address coater 322 is configured to function similarly to address generator 136 and has multiple inputs connected to corresponding stages of regional storage circuit 306 and multiple outputs.

Address coater 322 converts the storage information of the selected region into a form suitable for addresses in memory sectors. As an example of such an address coater, model 4008 manufactured by R.C.I.Koichi can be used. As described here, if the code information stored in the area storage circuit 306 is compatible with the memory device, this address coater 3
22 is unnecessary. The combination of the address code from address generator 136 and the address code from address coater 322 forms the address of the storage address of the accessed memory sector.

Therefore, depending on the particular sector accessed by memory selection circuit 222, address generator 136 and .
The memory address addressed by the combination of address coaters is read. To facilitate understanding of memory sector operation and memory device description, the memory has five sectors, sector 1 contains parcel post rate information, sector priority rate information, and sector interface. State UPS charges are
It is assumed that the intrastate UPS charges are stored in the sector and other charges are stored in the sector.

Other charges in the sector include Priority Mail half pound charges, Priority Mail charges, book crate charges and Parcel Post charges for parcels between £64 and £70. Additionally, book crate fees are stored in the sector with priority mail fees, and blue label fees are stored in the sector along with intrastate fees. Of course, the postage rates included in these particular sectors are merely illustrative and are not intended to limit this invention. This particular separation of memories is stated for the purpose of facilitating understanding of the postal scale according to the present invention. Now, by pressing any of the type selection switches, the memory selection circuit 222 selects the corresponding one of the output terminals determined by the coded content and stored in the type storage circuit 206. drive one.

Furthermore, when the book rate is selected, not only is the output terminal driven, but the auxiliary output is also activated to provide a disabling signal to OR circuit 320. Similarly, when the blue label selection switch is operated, the output terminal of memory selection circuit 222 is energized and the other auxiliary output terminal is energized to provide a disable signal to OR circuit 320.
No matter which type selection switch is operated, the 1/2 pound detection circuit 146 supplies ounce data from the ounce counter 112, encoder disk position data from the OR circuit 149, and pound data from the BCD-to-binary converter 134. be done.

However, this data provided to the 1/2 pound detection circuit 146 is not used until the detection circuit is enabled. That is, the encoded information stored in the type storage circuit 206 is stored in the priority mail selection switch 3.
This is limited to when the priority mail detection circuit 220 detects that the 0a operation is indicated. At this time, the 1/2 pound detection circuit 146 is enabled to use the provided information to determine whether the parcel weight is greater than or equal to 1/2 pound increments (the parcel weight is less than or equal to 1/2 pound increments). (assuming the weight is less than that determined by the pound unit data provided to the detection circuit). This decision is provided to the memory selection circuit 222, which in turn is provided to the memory sector V. According to the signal provided to the memory selection circuit 222 by the 1/2 pound detection circuit 146, the memory selection circuit drives either its output terminal or the output terminal V.

The latter terminal is of course driven to select the memory sector V in which the 1/2 pound postage data is stored. The most significant bit produced by BCD-to-binary converter 134 indicates that the parcel weight is 64 pounds, and this indication is communicated to memory selection circuit 222 to assign the selected type of code content as priority. When it is timer, parcel post or book rate, the memory selection circuit drives its output terminal.

1 Inhibition Circuit According to the present invention, data stored at an address in a memory is prevented from being displayed when a predetermined condition occurs.

These states are (a) when the counter row indicates that the weight on the base plate is ROJ weight 2, (b) when the counter row indicates negative weight, {c) when the type selection switch 30
(d) Region selection switch 40 is not operated.
(e) including when an inappropriate region selection switch is activated. The details are explained below. (a) When the weight is RO.

First of all, when the scale base plate and therefore the encoder disc 10 are in their respective reference positions, even if the transport type selection switch and the destination area selection switch are operated correctly,
It is desirable that the postage charges not be displayed even if the This can prevent confusion for postal scale operators.
A zero weight detector is therefore provided to detect when the base plate is in the reference position. This zero weight detector is composed of OR circuits 137 and 138 and a NOR circuit 140. OR circuit 137 has multiple inputs connected to the output of BCD-to-binary converter 134. OR circuit 13
8 has a plurality of inputs connected to respective counting stages of the ounce counter 112. It will be clear that these OR circuits 137 and 138 can be constructed by a single circuit if desired. NOR circuit 140 is a circuit well known in the art that generates binary RlJ when binary RO enters each input. As shown, NOR circuit 1
The inputs of 40 are connected to respective outputs of OR circuits 137 and 138. Thus, when the count in the counter column is not being incremented, each stage of ons counter 112 stores the binary RO and the OR circuit 138 sends the binary RO to the NOR circuit 140. Also binary ROJ
occurs at each stage of pound counter 114 and ten pound counter 116, which produces a binary ROJ at each output terminal of K-width to binary converter 134. This state is the OR circuit 1 that sends the binary RO to the other input of the NOR circuit 140.
Detected by 37. By sending binary ROJ to each input terminal of the NOR circuit 140, the NOR circuit 140
teeth,. A binary RlJ indicating the state of zero weight is generated.

This zero weight instruction is the OR circuit 142, the other OR circuit 1
44 and a pair of OR circuits 416 and 418 as an inhibit signal to prevent postage from being displayed when this condition occurs. b) When under negative weight.

As detailed above, when a parcel is removed from the scale baseplate, the baseplate and thus the encoder disk 10 return and overshoot past the reference point. This means that the count in the counter column decreases below O and counts a negative weight. This decrease in count causes an overflow of the signal at overflow terminal 117 which sets flip-flop circuit 1132. Therefore, when this flip-flop circuit 132 is set, it will indicate the J weight. This condition is detected by OR circuit 144 which has an additional input connected to one output terminal of flip-flop circuit 132. Therefore, when this flip-flop circuit 132 is set to indicate a negative weight condition, the binary RlJ
is sent to the OR circuit 144, in other words, this binary R
lJ is sent as an inhibit signal through OR circuits 416 and 418 to prevent the display of postage being read at this time. (c) When the type selection switch is not operated.

As previously mentioned, when the type selection switch is operated to close its normally open contacts, a corresponding signal is provided via the signal line to the type encoder 204, thereby driving the type encoder. When the type encoder is activated in this manner, the encoded information for this selected switch is formed and stored in type storage circuit 206. As previously mentioned, this type storage circuit 206 has extra stages that are not required to store the above information. This is due to the fact that, in the embodiment of the invention, the coded information is a 3-bit word and the type storage circuit has a storage capacity of 4 bits. This fourth storage stage receives a predetermined signal, such as binary r1, when any of the other three stages receives a binary r1, signal. This means that when the type encoder 204 is driven, the fourth stage of the type storage circuit 206 is also driven. Therefore, an indication that the type selection switch is not operated is given by the binary RO. This binary Rl. Sent as J. This signal is transmitted to OR circuit 144 and passes through OR circuits 416 and 418 as a prohibition signal, thereby inhibiting the display of the data stored in the addressed memory address in this state. Of course, type encoder 20
4 is activated normally, the type memory circuit 20
The binary ROJ stored in the fourth stage of 6 is the binary R
lJ, and the previously occurring inhibit signal is removed. (d) When the region selection switch is not operated.
As previously mentioned, when any of the region selection switches is operated and its normally open contacts are closed, the region encoder 304 is activated.
A signal is applied to the signal line connected to 01. Driving this regional encoder or providing a signal to the region 8 signal line sets a flip-flop circuit 318. Therefore, when none of the region selection switches 40 are operated, the flip-flop circuit 318 remains set and a binary RL is sent to the OR circuit 142 from its 0 output terminal. This signal applied to OR circuit 142 is transmitted to OR circuit 144, and is further applied as an inhibit signal to OR circuits 416 and 418 to inhibit the display of data read from memory in this state. Of course, if the region select switch is properly actuated, the setting of flip-flop circuit 318 will remove binary RlJ from OR circuit 142 and stop the inhibit signal. :e} When the area is inappropriate.

There are several types of transportation with limited destination areas to choose from. For example, UPS Intrastate (UPS
If IntrastateShipment is selected, the local region and several other regions can be selected due to the special pricing structure of the United States.

Another example is Blue Label.
) is selected, only four regions can be selected at most. It therefore makes sense to detect whether the selected destination region is applicable to [JPS Intrastate and Blue Label]. This determination is made by regional comparator 324. This regional comparator 324 has an input terminal connected to the output terminal of address coater 322 . Still other input terminals are connected to memory selection circuit 222, each of which accepts a signal indicating that JPS Intrastate or Blue Label has been selected. Upon receiving a signal indicating that UPS Intrastate has been selected, region comparator 324 compares the address by address coater 322 with the selected region to determine whether an inappropriate region was selected and change the region. Preset. A similar comparison is made by regional comparator 324 when Blue Label is selected. When an inappropriate region is selected, e.g., when the selected region is not compatible with a particular transport type, the region comparator 324 provides an output signal to the OR circuit 142 which is routed through the OR circuit 144 to the OR circuit. 416 and 418 to form a prohibition signal;
Display of data read from memory is prohibited while this condition occurs. This comparator is a Motorola 3-bit comparator model 1458.
5 can be used. Of course, it is possible to configure this comparator with a gate circuit,
The coded region information is then compared to a reference preset region when a particular type is selected. If necessary, individual OR circuits 137, 138, 142, 1
It is clear that 44, 416 and 418 can be combined into a single composite input OR gate.
The reason for using OR circuits 416 and 418 individually will become clear later. Furthermore, the OR circuits 137, 138 and the NOR circuit 140 can be combined into a single composite input NOR gate circuit. Alternatively, a single OR circuit connected in series with an inverter circuit can be used if desired. Memory and Postage Display As mentioned above, the memory device is a programmable ROM.
It is preferably divided into five sectors, for example consisting of removable printed circuit boards or cards.

This allows individual memory sectors to be easily replaced or removed when postage revisions occur. Therefore, sectors 1 and 1 are preferably used for Parcel Post, Priority Mail and Booklet, UPS Intrastate and UPS Interstate, and Blue Label, respectively. The memory sector is configured to store postage for priority mail half pound increments and postage for priority mail, parcel post and book crates between 64 and 70 pounds. Each of these memory sectors is designated 402,4 in FIG. 2D.
04, 406, 408, and 410, generally designated as memory 400. Each of the memory sectors is of a type having multiple storage addresses;
Each memory address is divided into two parts. The two portions of each memory location are addressed by the same address code applied to the memory sector by a combination of address generator 136 and address coater 322. The first and second portions of the addressed storage location are read sequentially by time sharing when the memory sector is enabled. Each of the memory sectors is connected to output terminal 1 of the memory selection circuit 222.
, , , and have enable inputs connected to , , , and.

Depending on which output terminal is driven, the corresponding memory sector is thus enabled. When a memory sector is enabled, the postage data stored in the corresponding portion of the addressed storage location is read therefrom in response to a timing signal provided to the memory sector. More specifically, each memory sector has a timing signal input terminal that is commonly connected and configured to accept a periodic timing signal generated by a suitable lock generator 44. One cycle of clock generator 414 consists of a positive pulse followed by a negative pulse, which pulses are applied to the timing pulse input terminal of each of the memory sectors. As an example, a first portion of an addressed storage location is read during a timing interval of positive pulses, and a second portion is read during a timing interval of negative pulses. Therefore, during each clock cycle all of the data stored in the addresses addressed, ie, the first and second portions, is read out. The time required for a complete read of both portions of the addressed storage location is considered to be a multi-flex cycle of memory 400. If desired, each addressed address can be made up of four or more parts, each part being read in part of a multiflex cycle.

This multiflex cycle can be defined by the clock generator 414, and can be, for example, two or more clock cycles, and techniques for using such multiflex cycles are already well known. There is. The postage data stored in the addressable addresses of the memory sectors is in dollars and cents.

Of course, this data is stored in coded form, such as the K1 code. As an example, data showing dollars is
Data representing cents is stored as a two-digit number in the first part of the address, and data representing cents is stored as a two-digit number in the second part of the address. Thus, during the first part of the multiflex cycle, dollar data is read from the addressed address, and during the second part of the multiflex cycle, data representing cents is read. The programmable ROM used in each memory sector has a storage capacity of 8 data bits for each portion of the addressed address. Since the BCD code represents the numbers 0 to 9 as 4-bit codes, each memory sector has a first read output terminal for reading out the 4-bit coded contents of one decimal digit and a 4-bit coded content of the other decimal digit. Preferably, it has a second read output terminal for reading out the contents. For example, the first decimal digit can be a tens digit and the second decimal digit can be a ones digit. Thus, in the first part of the multiflex cycle, the data representing the dollar portion of postage is read out as a number of 2 digits, and in the second part of the multiflex cycle, the data representing the cent portion of postage is also read as a number of 2 digits. Read out as a number of digits. In a preferred embodiment of the postage scale according to the invention, the postage is displayed in the form of a visual display such as an LED array, a suitable numeric display lamp JZ array, or the like.

In FIG. 2D, these displays 430 and 432 are each configured as two seven segment arrays. Display 430 displays dollars in two digits and display 432 displays cents in two digits. Display 1-430
The 0tfI portion is driven by a suitable 7 segment driver 420 and the 1 row portion by driver 434. A portion of the display 432 is driven by the driver 426. and the single digit portion are respectively driven by a driver 428. Drivers 420 and 426 drive memory sectors 402, 404, 406, 408 and 4
A common connection is made to the first readout output terminal of each of the 10 terminals. Drivers 424 and 428 are commonly connected to the second read output terminals of all memory sectors. Therefore, as is clear from the figure, the first read terminal 402a of the memory sector 1 is commonly connected to the drivers 420 and 426. The second read output terminal 402b of memory sector 1 is commonly connected to drivers 424 and 428. Similarly, memory sector read terminal 404a is commonly connected to drivers 420 and 426, and memory sector second read terminal 404b is commonly connected to drivers 424 and 428, respectively.
The read terminals of other memory sectors are similarly connected.

Each of drivers 420, 424, 426 and 428 has an inhibit input terminal for accepting an inhibit signal. An inhibit signal such as binary RlJ inhibits the driver from driving the corresponding display, causing the display to
Planking out. As is clear from FIG. 2D, the inhibit input terminals of drivers 420 and 424 are commonly connected, and the inhibit input terminals of drivers 426 and 428 are commonly connected. The inhibit signal provided to drivers 420 and 424 is formed by OR circuit 416;
The inhibit signal provided to drivers 426 and 428 is formed by OR circuit 418. These OR circuits are connected to an OR circuit 144, and the OR circuit 144 further receives an inhibit signal from the OR circuit 142. Furthermore, OR circuit 41
6 has another input terminal connected to one of the outputs of the clock generator 414 and receives one of the timing pulses from the clock generator during each multiflex cycle. OR circuit 418 has another input terminal connected to the output of clock generator 414 as well as receives another timing pulse during each multiflex cycle. Thus, during each multiflex cycle, OR circuits 416 and 418 alternately provide inhibit signals to drivers 420, 424 and drivers 426, 428, regardless of which inhibit signals are provided by OR circuits 142 and 144. It is carried out without any delay. Of course, when the inhibit signal is provided by OR circuits 142 and 144, the inhibit signal provided to all of the drivers will be maintained for the entire multiflex cycle. As detailed above, there are various prohibited conditions. In another state, the drivers 420, 424
, 426 and 428 are all prohibited. This state will be explained below. Some addressable storage locations in a memory sector are not filled with postage. Normally, this address is not addressed. However, when considering the possibility of an address error,
When such an address is specified, it is preferable that its contents not be displayed. Such an address therefore has a predetermined data word, which data are read out from the first and second read terminals when an address error occurs. A gate circuit, such as AND gate 412, is provided with a composite input connected to the memory read output terminal of each memory sector, and the gate detects when a given data word has been read. For example, if this predetermined data word is a binary RL at each bit address,
, the AND gate 412 detects this and generates an inhibit signal accordingly. This prohibition signal is
OR circuits 416 and 4 via OR circuit 144 (Fig.
18 to inhibit all drivers 420, 424, 426, and 428. In operation, it is assumed that parcel post is selected as the transport type.

Parcel Post postage rates are shown in Table 1 below.
It is assumed that the parcel postage charges, some of which are shown in Table 1, are stored in memory sector 1.

Memory selection circuit 222 sends an enable signal to the sector 1 enable input terminal. The parcel is placed on the platform of the scale,
When the necessary region selection switch 40 is operated, the address generator 136 and address coater 322 address a particular storage address in memory sector 1. This address is sent commonly to all memory sectors, but
Since only memory sector 1 is enabled, only the address of this sector 1 is addressed. Parcel weight is 5
lbs., and the selection switch 40f for region 5 is operated. This causes the address generator 136
The address formed by the combination of and address decoder 322 will select the address where the postage of $1.28 is stored. During the first part of the multiflex cycle, the first part of the addressed address is read from memory 1 and the content representing one dollar (0 in this case) is transferred from read terminal 402a to driver 4.
Enter 20 and 426.

At the same time, content indicating a single digit dollar (I in this case) is read out from the readout terminal 402b, and the drivers 424 and 42
8. However, during the first portion of this multiflex cycle, the timing pulse provided by the clock generator to OR circuit 418 acts as an inhibit signal to inhibit drivers 426 and 428. As a result, the display 432 becomes blank,
Display 430 is driven by drivers 420 and 424 to display the dollar information stored in the first portion of the memory address and read from memory selector I. Therefore, the display on the display 430 becomes ROl. In the second part of the multiflex cycle, a negative timing pulse is applied to memory sector 1 and the second part of the addressed address is read.

During this portion of the multiflex cycle, the ten cent digit encoding information is read from terminal 402a (in this case a 2) and provided to drivers 420 and 426. At the same time, encoded information for the one digit of cents is read out from terminal 402b (8 in this case) and supplied to drivers 424 and 428. However, during this second portion of the cycle, the clock pulses provided by clock pulse generator 414 to OR circuit 416 serve as an inhibit signal and drive
The display 430 is prevented from being driven. Therefore, during the second portion of this multiflex cycle, display 432 will display R28J cents.
In the display described above, displays 430 and 432 are driven alternately during each part of the multiflex cycle, so that the frequencies at which these displays are driven are such that an observer of the displays does not experience any flickering. It is preferable that the value is set sufficiently high.

Therefore, in each multiflex cycle,
The data for the dollar portion of the postage is read out and displayed on display 430, and then the read data for the cent portion is displayed on display 432. By using this multiflex or time sharing, low cost commercially available memory devices can be used as memory sectors. Postage charges must be expressed as a 4-digit decimal number, so
Each memory sector requires 16 bits of BCD information, even though it is comprised of memory devices that can only store 8 bits of BCD. By alternately reading the first and second portions of each addressed memory location, all 16 bits are read in each multiflex cycle. of course,
Drivers 420, 424, 426 and 428 inhibit driving of their respective associated displays 430 and 432 when one or more of the inhibit conditions described above occur.

- Therefore, even if the selected memory sector is addressed, the data stored at that address will not be displayed. Therefore, also when no parcel is placed on the scale base plate, the counter column shows zero weight and the inhibit signal is generated by the NOR circuit 140. OR circuits 142, 144,
416 and 418 to all drivers. Similarly, when a parcel is removed from the scale baseplate, the baseplate overshoots from the reference point and an inhibit signal is generated by the flip-flop circuit 132 indicating one negative weight! The signal is generated and supplied to all drivers via the OR circuit 144 and the OR circuits 416 and 418. Additionally, when type selection switch 30 is not actively operated, an inhibit signal is generated by type storage circuit 206 and transmitted to inverter circuit 216 and OR circuits 142, 144, 416, and 418 to inhibit all drivers. . Similarly, when the region selection switch is not properly operated, an inhibit signal is generated by flip-flop circuit 318 and output from OR circuit 142.
, 144, 416 and 418. Also, in inappropriate areas such as U.
When selected for PS Intrastate or Blue Label, regional comparator 324 forms an inhibit signal provided via the OR circuit described above to inhibit the display driver. Finally, if an inappropriate memory address, such as an address that is not supposed to be used, is accidentally addressed, its contents are detected by AND gate 412 and an inhibit signal is formed by OR circuits 144, 416 and 412.
8 to all display drivers.
In this manner, inappropriate or confusing information is not displayed. . It is clear that memory sectors other than memory sector 1 are selected and addressed in exactly the same manner.

For example, when a memory sector is selected, if Priority Mail is selected as the type and 1/2 pound information is used, or when the parcel weight exceeds 1/2 pound, such information is stored in the address of the memory sector. Available as part of. That is, the 1/2 pound information generated by the 1/2 pound detection circuit 146 is transmitted to the address generator 136 and the address coater 322.
Select the appropriate address in Sector V that stores the postage for priority mail in 1/2 pound increments. This rate information is read out using the multi-flex cycle technique as described above and displayed as appropriate on the displays 430, 432. Similarly, if the parcel weight exceeds 64 pounds,
This information is combined with the encoded addresses by address generator 136 and address coater 322 to select the appropriate address in the memory sector where the postage for parcel weights greater than 64 pounds is stored.
This rate information stored at the addressed address is read out by the multiflex and displayed on displays 430 and 432 as detailed above. Although this invention has been described with respect to a particular embodiment of a postal scale, it will be obvious that various modifications and changes may be made thereto.

Further, the present invention can be considered for various types of applications to data processing devices, and need not be limited to the periphery of postal scales. Additionally, the particular postal scales described herein may be subject to various modifications in construction and detail.

For example, encoders, code converters,
Address generators etc. can be changed or omitted. The type selection switch and region selection switch may be any suitable keyboard input device commonly used in data processing equipment. Similarly, other display devices known in the art may be used for the indicator lights, weight display, and postage display. For example, a single display panel may display the particular shipping type and destination region selected, the weight of the parcel, and the determined postage rate. As another example, a display for displaying postage charges may also be used as a display for displaying the weight of a parcel by providing a suitable switching device. In addition to or in lieu of displaying prices,
Various mechanisms may be provided to automatically record and affix the read postage of a weighed parcel to the parcel.

Furthermore, since the read postage charges can be encoded in the necessary digitized form, such data may be used in other devices, such as digital computers, to automatically tally the charges. Furthermore, although the units of weight have been described in terms of pounds and ounces and in 1/2 bond increments, the weights in pounds and ounces may also be expressed in units of pounds in w-adic numbers. It is clear that other weight units such as kilograms and grams may be used if necessary. It is clear that if the weight of the parcel is not measured in ounces, the ounce counter must be replaced by a decimal counter circuit capable of counting tenths of a pound, for example. In other embodiments of the present invention, in certain conditions where displays 430 and 432 are inhibited from displaying information, each inhibit signal may be used to drive an associated inhibit indicating device so that an operator can It is possible to notice the occurrence of such a situation.

For example, the ROJ weight prohibition signal generated by the NOR circuit 140 is applied to the zero weight display, the 1 negative weight prohibition signal generated by the flip-flop 132 is applied to the negative weight display, and the ROJ weight prohibition signal generated by the NOR circuit 140 is applied to the negative weight display. , by an appropriate display device driven by an appropriate stage of type storage circuit 206. Other prohibited states are displayed in the same way. In yet other embodiments, each multiflex cycle may be defined by more than just two clock pulses. That is, multiflex can be used to select various portions of each of the storage addresses of a memory sector,
The corresponding display driver is selectively activated and enabled. For example, one dollar and one digit indicating the postage as an 8-bit word in the first part of the addressable address, and a cent for the postage as an 8-bit word in the second part of the addressable address. Instead of memorizing 1 digit and 1 digit, you can write 1 digit of dollar in 4 bits in the first part, 1 digit of dollar in 4 bits in 2nd part, 1 digit in cents in 4 bits in the second part,
It is possible to store each digit and one digit using 4 bits. Each of these portions is read from the memory sector by time sharing during one multiflex cycle.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of an electronic postal scale according to the present invention, and FIGS. 2A to 2D are block diagrams of logic circuits of various parts of the postal scale according to the present invention. 10... Encoder disk, 10a, 10b... Track, 12a, 12b... Photoelectric detector, 14... Weight encoder, 16... Zero weight detector, 18... Base plate lowering detection Device, 20...Address generator, 30
...Type selection switch, 32...Type encoder,
34...Address generator, 36...Memory selector, 40...Region selection switch, 42...Region encoder, 44...Address generator, 46.
...Error area detector, 50...Memory, 60...
Prohibition circuit, 70... Drive circuit (driver), 80...
・Day spray.

Claims (1)

[Claims] 1. In a postage scale adapted to display the postage of a parcel sent to a destination, a first means operable for selecting the type of transportation of the parcel, selecting the destination region of the parcel. weight data forming means for forming digital data according to the weight of the parcel placed on the base plate of the scale; and a postage rate according to the type, the destination and the weight increment of the parcel. memory means comprising a plurality of memory portions corresponding to at least one of the said types, storing the parcel weight data at an addressable address; means for addressing a street address; means for reading stored postage data from said address addressed; means connected to said reading means for displaying postage data; and removing a parcel from the scale when there is no parcel on the scale. means for inhibiting said display when at least one of a plurality of conditions occurs, including at least improper selection of a destination region, incomplete selection of a type, and improper addressing of a memory address. 2. said weight data forming means includes means for generating a number of pulses proportional to the weight of the parcel, further comprising multi-stage pulse counting means connected to said pulse generating means for counting said pulses; and The means are
and detecting means connected to said counting means, said detecting means being responsive to the contents of at least a selected column of said counting means to detect when said column is empty and to provide an inhibit signal indicating zero weight to said memory reading means. 2. The postal scale according to claim 1, wherein the postal scale is configured to inhibit the display of the display means when the postal scale is sent. 3. The counting means comprises an up/down counter, and when the counter counts below a predetermined value due to pulses from the pulse generating means when the parcel is removed from the base plate, an overflow signal is generated. , and the inhibiting means further includes overflow detecting means for detecting the overflow signal and transmitting an inhibiting signal to the memory reading means to inhibit display by the display means. Postal scales described in Section 2. 4. said first means comprises a plurality of individually manually operable type selection switches, each of said selection switches generating a corresponding signal when actuated according to a respective type of transport; The prohibition means includes means for detecting that the type selection switch is operated, and upon detecting this, sends a prohibition signal to the memory reading means to prohibit display by the display means. Postal scales listed in section. 5. The first means further comprises a type encoder connected to all of the type selection switches for forming encoded information of the operated type selection switch, the encoded information being at least as part of the address of the memory portion. said type encoder generates an output signal which changes state when said coded information is formed, and said detection means included in said inhibiting means typically generates an inhibiting signal and said 5. A postal scale according to claim 4, further comprising means for terminating the inhibition signal in response to a change in the state of the output signal. 6. said second means comprises a plurality of individually manually operable region selection switches, each of said region selection switches generating a corresponding signal when operated, and said inhibiting means comprises a plurality of individually manually operable region selection switches; Claim 1 includes means for detecting that the display means is not operated, and upon detecting this, sends a prohibition signal to the memory reading means to prohibit display by the display means.
Postal scales listed in section. 7. said second means further comprising a region encoder connected to all said region selection switches for forming coded information of the operated region selection switch, said coded information being at least as part of the address of the memory portion; said regional encoder generates an output signal which changes state when said coded information is formed, and said detection means included in said inhibiting means typically generates an inhibiting signal to detect said 7. A postal scale according to claim 6, further comprising means for terminating the inhibition signal in response to a change in the state of the output signal. 8. The prohibition signal further comprises comparator means which accepts a signal indicative of an operated region selection switch and a signal indicative of the selected transport type and produces an output when these do not correspond, and this comparator output signal indicates that an inappropriate selection has been made. 7. The postal scale according to claim 6, wherein the postal scale is supplied to the memory reading means as a prohibition signal indicating the area where the area has been designated, thereby inhibiting the display by the display means. 9. Each memory address in the memory means that does not contain postage data is provided with a predetermined storage signal, and the inhibiting means detect this predetermined storage signal when it is read from the memory means. 2. A postal scale according to claim 1, wherein a prohibition signal indicating an inappropriate address is sent to the memory reading means to inhibit display by the display means. 10. A method for determining and displaying postage charges for sending a parcel to a destination area according to the selected type of transport, comprising:
The postage charges for a given weight increment are then stored in addressable addresses in the memory, each of which addresses being provided in the memory portion corresponding to said type and being addressed as a function of the weight of the parcel and the region of destination. The method comprises performing a digital count as a function of the weight of the parcel, selecting said type and making it a digitally coded signal, selecting said destination area and making it a digitally coded signal, and selecting said destination area and making it a digitally coded signal; select a memory portion as a function of said coded signal of said destination area, address an address of said memory portion by combining said digital count and said coded signal of said destination area, and address a postal address from said address addressed by time sharing. reading rate data and providing said data to a display means by time sharing to display an appropriate postage rate depending on the type of transport, destination area and weight of the parcel, and (a) said digital count is (b) when the digital count indicates a negative weight; (c) when the type is not selected;
d) when said destination region is not selected; (e) when said destination region and said type selection are not compatible; and (
f) the provision of data to said display means is inhibited when at least one or more of the following conditions exists: f) no postage is stored at said address; 11 said digital counting process generates a first set of consecutive pulses when the parcel is placed on the scale and a second set of consecutive pulses when the parcel is removed from the scale; incrementing a count of a counter from a reference count in response to a group of pulses and decreasing a count of a counter in response to a second group of pulses, generating an output signal when the count falls below a reference count, and , wherein the inhibiting process uses the output signal as the inhibiting signal.
The method described in section.