JPS6049333B2 - Clock control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a clock control system for a microprogram-controlled electronic computer.

The clocks used in electronic computers are semi-fixed once the design is completed. On the other hand, the speed of logic elements used in electronic computers is increasing day by day due to advances in semiconductor technology. Therefore, there is a need to improve performance by replacing the logic elements of the originally designed electronic computer. In this case, the major problem is the processing of the clock system that controls the logic of the electronic computer. Normally, the operation of an electronic computer is defined by a machine cycle, and one machine cycle consists of a plurality of clock pulses. Replacing logic elements reduces the delay in the data system, but this does not mean that the machine cycle can simply be shortened, since there are variations in the delay time of each element, and it is not possible to uniformly shorten the clock pulse intervals. In reality, this is not possible. The conventional technique was to shorten the machine cycle by moving and resetting the clock pulses used for data latches.

This has the disadvantage of causing extensive logic changes. This will be explained in detail based on FIGS. 1 and 2.

FIG. 1 shows a generally implemented arithmetic device, and FIG. 2 is a time chart explaining the operation of FIG. 1.
One machine cycle consists of As, B3, A as shown in Figure 2.
It consists of six basic pulses: 1, B1, A2, and B2.

When the type of operation is specified using the EO word, the control code is latched into the register D4 using the clock As. Here, a case will be considered in which the contents of register B2 and register Al are subjected to arithmetic processing and the results are latched in register Al.
It is assumed that the contents of the register Al are determined by clock B1 before the execution of this EO. Further, it is assumed that the contents of register B2 are determined by clock B3 of this EO. 1
If the machine cycle is m hours, immediately m during calculation time 6
/ Arithmetic processing is performed for 6 hours, but if one machine cycle is changed to n hours (m>n), a case may arise where the processing cannot be performed for n/6 hours.

For example, it is latched by clock M, and its output is clock B3.
If the delay 1 of the data system between clocks A3 and B3 is n/6<TD<m/6, time compression in this section is impossible. Regarding the line with sufficient margin when the machine cycle is m hours, that is, if TD < n/6 × m/6, even if the machine cycle is shortened by n/m times (basic pulses A3, B3, etc. /m
It is clear that no problem will arise. SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned conventional problems and to provide a lock control system that can shorten machine cycle time without moving clock pulses.

A feature of the present invention is that it has a memory that stores clock control data, addresses the clock control data in the memory using the EO word, and controls the basic clock generation circuit based on this clock control data. .

3 and 4 show examples of generally known clock system logic, and FIG. 5 shows its time chart.

In FIG. 3, the signal PU generated from the pulse generator 7
The waveforms of LSEA-Pl2 and PULSEB-Pl3 are the fifth
Suppose we have a tool like the one shown in the figure.

Trigger type latch circuits 8, 9 and NOT circuit 10 in FIG.
,0R circuit 11 constitutes a clock ring! The output signals from the clock ring, PTO-P, PTl-P,
The waveforms of PT2-P, TO-P, Tl-P, T2-P are:
The same is shown in FIG.

FIG. 4 shows the output signal from the clock ring and the PU? Basic clocks A3-P, Al-P, A2-P, B3-P, Bl from EA-P, PULSEB-P signals, etc.
-P, B2-P, and its signal waveform is also shown in FIG.

FIG. 6 shows a block diagram of an electronic computer controlled by a microprogram using a clock control method, which is an embodiment of the present invention.

Since it is a microprogram-controlled electronic computer, a control storage device (CS) 20, CS address generation circuit 21, and E
Zero word register 22 is a basic component.

The contents of the EO word set in the Eq register 22 are used by the decoder 32 to perform various controls inside the computer. Now, as shown in Figure 7 (b), EO words are basically E
It consists of a function section that specifies the function of the O word, a control data section, and a branch address section.

Note that the EO word for memory writing in FIG. 7(a) is used when the memory 25 in FIG. 6 is a UAM.

The clock control data generation circuit 30 in FIG. 6 uses the function part of the EO word register 22 as an address, sets read data from the memory 25 in the read data register 26, and outputs the read data to the clock control circuit 31. The contents of the memory 25 have been previously written as shown in FIG. If the memory 25 is a RAM, use the memory write EO word (FIG. 7(a)), set the function section = 000, and write memory addresses 000 to 000.
Initial settings up to 111 must be performed. In this case, the control data I field is used as a memory address, and the control data ■ field is used as write data. The clock control circuit 31 includes a pulse generator 27, a clock ring 28, and a basic clock generation circuit 29.

The pulse generator 27 and clock ring 28 are identical to those shown in FIG. Basic clock generation circuit 2
9 is an example in which the present invention is applied to the above-mentioned FIG. 4, and detailed circuit diagrams are shown in FIGS. 10, 11, and 12. The operation of the basic clock generation circuit 29 will be explained below based on a specific example. It is assumed that the contents of the memory 25 are as shown in FIG. Now, when the EO word of function section = 001 is read, its Eq is set in the EO word register 22 at the timing of clock Bl-P, and furthermore, the memory address is set in the memory address register 23 at the timing of clock A2-P. Set. The output data of the memory 25 is DO=0, d1=1, d2=1, d3=0,
d4=0, d5=0, set in the read data register 26 at the timing of clock B2-P, and output to the clock control circuit 31. Note that the clock control data DO to D5 must be determined before the EO word is executed.

(The execution cycle of the EO word is from clock A3-P to clock A3-P, and overlaps with the access cycle of the EO word. See Figure 9.) If the clock control data is DO=0, d1=1, d2,=1,d
3=D4=D5=. In the case of 0, according to the logic in FIGS. 10, 11, and 12, clock B3-P, clock Al-P, and clock A
Between 1-P and clock B1-P, each dummy time W
)1, D2 can be inserted.

Below, with reference to Figure 13, Figures 10, 11, and 12 will be explained.
The operation of the figure will be explained in detail. Output data d of memory 25
Since 1-P is the true value, the flip-flop 41 is set by the AND circuit 40 at clock A3-P, and 0
The signal is inputted to the D input terminal of the trigger type latch circuit 45 via the R circuit 44 .

The input signal 1NHB-1P of the NOT circuit 48 is the output of the trigger type latch circuit 55 shown in FIG. 11, and its initial value is -false.

Therefore, the AND circuit 4 is activated at the timing of PULSEB-P.
7 acts, becomes the clock signal of the trigger type latch circuit 45, the output signal of the 0R circuit 44 is latched, and the I
NHA-1P becomes true. Then timing PULS
At EA-P, the output signal 1NH of the trigger type latch circuit 46
The B-1P signal becomes true. INHA-1P, iN1IB
The -1P signal is input to the 0R circuits 58 and 59 in FIG. 11, respectively, and the INHA-P and INHB-P signals become true. In the AND circuit 61 of FIG. 12, since the INHA-P signal is true, the AND condition does not hold, and therefore the basic clock A1-P is blocked. Also, similarly INHB-
Since the P signal is true, the basic clock B1-P signal is also blocked. To release the blocking of the basic clock A1, the O side output signal of the trigger type latch circuit 46, that is, I
PU when NIB-0P becomes false? The timing AND circuit 43 of EA-P operates and the flip-flop 41 is reset, and then INHA is activated at PULSEB-P.
This is when the -1P signal becomes false. Also, the blocking of the basic clock B1-P is canceled at PULSEA-P immediately after the JNHA-1P signal becomes false, but due to the clock control data D2=1, the IN of FIG.
The HB-1P signal is simultaneously set in the same PULSEA-P, the JNHB-1P signal immediately becomes true, and the basic clock B1-P is blocked again. As can be seen from the time chart in Fig. 13, the basic clock B1-P is
Occurs at PULSEB-P after the HB-P signal becomes false. With the above clock control data d1=1, d2=1, the basic clock B3-P-A1-P and A1-P
This means that dummy times Dl and D2 can be inserted between -B1 and P, respectively.

With the configuration as described above, the following effects can be obtained in the present invention.

Depending on the type of EO word, a dummy time can be inserted between arbitrary clocks within one machine cycle, which can save the operation of elements with long delay times, so logic elements can be replaced without moving clock pulses. It is possible to easily and economically reduce machine cycles by increasing performance.

Furthermore, since clock control data can be written in EO words, timing margin tests using microprograms can be easily performed.

Furthermore, when the processing device detects a malfunction, the EO word can be re-executed by adding a dummy time to the clock interval, resulting in an effect that the probability of re-execution is increased.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the logic that is the object of the present invention;
Figure 2 is a time chart diagram of Figure 1, Figure 3 is a circuit diagram of a general pulse generator and clock link, Figure 4 is a general basic clock generation circuit diagram, and Figure 5. is the third
FIG. 6 is a block diagram showing an embodiment of the present invention, and FIG. 7 is a time chart showing the operation of FIG.
8 is a diagram showing an example of the memo 5 data in FIG. 6, and FIG. 9 is a supplementary time chart diagram of FIG. 6. 10, 11, and 12 are detailed diagrams of the basic clock generation circuit of FIG. 6, and FIG. 13 is a time chart representing one embodiment of FIG. 6. θ Code explanation 23...Memory address register, 24...
...Write data register, 25...Memory, 26...Read data register, 27.
... Pulse generator, 28 ... Clock ring, 29 ... Basic clock generation circuit.

Claims (1)

[Claims] 1. In a microprogram-controlled electronic computer in which a machine cycle consists of multiple phase clock pulses, an EO word register for latching an EO word read from a control storage device, a memory for storing clock control data, and an E.
A memory address register for latching a field indicating the type of EO word in the O word and using it as a memory address of the memory, a read data register for latching clock control data from the memory, and the clock control data. The clock control data stored in the memory is data corresponding to each of the multiple phase clock pulses constituting the machine cycle. , wherein the basic clock generation circuit changes the interval between clock pulses of a corresponding phase depending on the value taken by the clock control data.