JPS6047847B2 - EEG diagnostic device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electroencephalogram diagnostic apparatus useful for comprehensively analyzing and diagnosing electroencephalograms.

Conventional electroencephalogram diagnosis has long been based on visual observation of electroencephalogram recordings, and even today, most doctors still rely on this method.

However, attempts have been made to automatically analyze brain waves obtained from electrical signals for a long time. In other words, the amplitude spectrum can be obtained by passing the electrical signal of the brain wave through multiple bandpass filters, and in recent years, with the development of electronic computers, it has become easy to obtain the autocorrelation and cross-correlation of the power spectrum of various waveforms. Many people are analyzing this. All of these methods statistically average brain waves and can easily calculate various parameters, but it is unclear what characteristics of brain waves the parameters being calculated are intended to represent, and many It has many drawbacks, such as difficulty in drawing comprehensive conclusions due to the flood of parameter values, and has not been put into practical use. In the field of electroencephalogram diagnosis, in addition to the above-mentioned correlation and power spectrum analysis, it has also been proposed to extract the amplitude probability density distribution of electrical signals. Obtaining the peak-to-peak distribution of amplitudes is also carried out by some analysts. This is a very good method, but since it focuses only on the amplitude of the waveform, it is necessary to separately find the power spectrum distribution. As already explained, this power spectrum information is like discarding the raw electroencephalogram waveform information, and therefore becomes a cause of not being able to obtain good results. Therefore, in order to obtain information as close to the raw brain wave information as possible, other analysts use the zero-crossing interval method, level-crossing interval method, or Ξ-angle approximation method to perform diagnostic calculations by hand or using a general-purpose computer. is suggesting.

Although this trigonometric approximation method takes amplitude into account, it cannot express the subscript as it is. Furthermore, the military crossover interval method discards amplitude information, and the level crossover method also discards values other than a certain level. Furthermore, they are provided as general-purpose computer programs that use the zero-cross interval method, which relatively does not damage the raw information of the brain waves very much, and all of these are batch processing methods that allow the raw information of the brain waves to be processed and measured online. There was no. An object of the present invention is to provide an electroencephalogram diagnostic device that statistically processes electroencephalograms faithfully to the electroencephalogram waveforms, accurately performs various analyzes with a small amount of input information, and can also be performed online.

According to this invention, each distribution of the time interval, the peak value of the signal during each interval, and the area value of the signal during the interval is extracted using the interval of zero crossing or level crossing of the electroencephalogram signal as a base point, and the standard deviation of each of these distributions is calculated. Detect.

It is possible to comprehensively evaluate brain waves from these standard deviations. Next, embodiments of the present invention will be described in detail with reference to the drawings.

Electrodes 2 are respectively attached to a plurality of induction points on the head 1, and these electrodes 2 are connected to a switching device 5 for switching the induction points via connection lines 3 and electrode terminal plates 4, respectively. An electrical brain wave signal (hereinafter simply referred to as "brain wave") from one guidance point selected by the switch 5 is amplified by an amplifier 6. The configuration so far is the same as that of a conventional electroencephalograph, and a conventional electroencephalograph generally extracts 8 to 12 induction points. The electrode 2 and amplifier 6 constitute means for extracting brain waves as electrical signals. Amplifier 6 in Fig. 1
A plurality of the following configurations may be prepared, and brain waves may be supplied from different guidance points to each and simultaneously processed, and these brain waves may be compared. Three unnecessary components of the output of the amplifier 6 are removed by a filter 7 as necessary.

As the filter 7, a combination of a low-pass filter and a high-pass filter, or a combination thereof, is used depending on the measurement state at the time. The output signal Vi of the filter 7 is input to a sampling point detection circuit 8 and a mask signal detection circuit 9 for removing unnecessary signals, and a sampling command signal and a mask command signal are generated. The brain wave signal Vi is input to each signal processing section of a peak value detection circuit 11, a waveform duration detection circuit 12, a waveform area detection circuit 13, and a preamplifier 14 for detecting amplitude probability density, and is subjected to signal processing according to each circuit. is done.

At this time, sampling commands are simultaneously issued to the gate circuits 15 to 17 provided at the next stage of the signal processing circuits 11 to 13, and furthermore to the cumulative storage units 21 to 23, which have been continued thereto. Gate circuit 18 next to preamplifier 14
Although the sampling command to the data accumulation storage unit 24 connected in cascade thereto is not shown, by performing the sampling command at O constant period from the pulse oscillator,
As will become clear later, an amplitude probability density distribution is measured in the cumulative storage section 24. The data accumulation storage sections 21 to 24 have a function of adding and accumulating analog input voltages to memories provided for each input voltage magnitude for each sampling command. The data stored in the data accumulation storage units 21 to 24 is further converted into analog values and recorded as a hard copy by the recorder 25, or displayed on the cathode ray tube display device of the display device 26, and the contents of the data are monitored. Further, the data from these cumulative storage units 21 to 24 are input as digital values to a data processor 27, and data calculation processing described later is performed. Data cumulative storage unit 21
~24, recorder 25, display device 26, data processor 27
Control for the above is performed by the control circuit 28. Next, the details of each part in FIG. 1 will be explained, but since this device can be constructed using a linear ICl digital IC, which is a semiconductor integrated circuit currently available on the market, the explanation will be made using logical formula designations without any particular emphasis. .

FIG. 2 shows part of the sampling detection circuit 8 and the processing section, in which the signal Vi input to the input terminal 29 is compared with the reference voltage from the variable voltage setter 31 by a comparator 32. The variable voltage setter 31 is set so that this comparator 32 compares at a level close to the zero crossing of the signal Vi(7) due to the nature of the signal. This setting is changed depending on the level of the brain waves, and the zero crossing point of the signal is desirable, but the level is determined depending on the situation. Therefore, the output of the comparator 32 is a rectangular wave output (2) that changes from positive to negative and from negative to positive almost at each zero crossing point for the input signal (voltage) Vi shown in FIG. 7, for example. b is supplied to the level converter 33. At this time, the square wave output■
. If a DC component is added to , then naturally this DC component must be cut off. The comparator 32 constitutes level crossing detection means. Square wave output■. b is level-converted to TTL level by the converter 33 and supplied to the delay circuit 34 and exclusive OR circuit 35. Here, the TTL level rectangular wave corresponding to the input signal Vi is delayed by 1 to 2 μSec in the delay circuit 34, and the exclusive OR of this delayed waveform and the waveform before the delay is taken in the circuit 35, and a rectangular wave output (2) is obtained. b
At each rise and fall of , a pulse having the same time width as the delay time of the delay circuit 34 is output. The output signal of the exclusive OR 35 is differentiated by a differentiating circuit 36, and each rising differential pulse thereof is supplied as a sampling command signal to the gate circuits 15 to 18 in FIG. 1. The output of the waveform delay circuit 34 is output to the waveform shaping circuit 37 of the waveform duration detection circuit 12.
Square wave with polarity of ± from L level■.

, is converted to . This converted rectangular wave signal is transmitted to an integrating circuit 44 configured by resistors 39 and 41 in a signal zero short circuit 38 that cuts off when the input signal Vi is zero, an integrating capacitor 42, and an operational amplifier 43. It is integrated by On the other hand, the rising and falling points of the rectangular wave output from the waveform delay circuit 34 are detected by waveform differentiating circuits 45 and 46,
These waveform signals drive a monostable multivibrator 48 through an OR circuit 47. A reset signal is applied to the FET switch 51 through the input terminal 49 during the operation time of the monostable multivibrator 48, which is turned on to discharge the charge in the integrating capacitor 42 and reset the integrating circuit 44. With this configuration, as shown in FIG. 7, the time from one zero-crossing point of the input voltage Vi to the next zero-crossing point, that is, the interval between level crossings, is equal to the output voltage of the integrating circuit 44 immediately before reset. o and is obtained at the terminal 52. In other words, the voltage VOt3 corresponds to the level crossing interval of the input voltage Vi, and the waveform duration detection circuit 12 constitutes a level crossing interval detecting means. The input signal i from the terminal 29 is supplied to the amplifier 54 through the input terminal 53 of the waveform area detection circuit 13, and its amplified output is sent to the resistors 56 and 57 in the signal zero short circuit 55, the integrating capacitor 58, and the operational amplifier. 59 and an integrating circuit 61 constituted by the voltage .
. (See also FIG. 7) is output to the terminal 62. The monostable multivibrator 63 is triggered by the output of the OR circuit 47, and a reset pulse is input from the reset input terminal 64 for the operating time to turn on the FET switch 65.
The integration circuit 61 is reset by this FET switch 65. With this configuration, the area value of the waveform from the zero-crossing point to the next zero-crossing point of the electroencephalogram waveform, that is, the signal indicating the waveform area within the adjacent level crossover is obtained at the terminal 62 as the integral output VOc of the integrating circuit 61 immediately before reset. . In FIG. 2, a short command to the signal zero short circuits 38 and 55 is given from a mask signal detection circuit 9, which will be described later, and the FET switches 66 and 67 are turned on by the short command.
The connection point between the resistors 39 and 41 and the connection point between the resistors 56 and 57 are each set to approximately zero potential. Next, the peak point detection circuit 11 will be explained with reference to FIG.

The input signal Vi is sent from a terminal 68 to a buffer operational amplifier 69,
The positive side of the input voltage Vi is supplied to each non-inverting input terminal of 71, and the positive side of the input voltage Vi is charged to a capacitor 73 through a diode 72. The voltage of this capacitor 73 is supplied to the non-inverting input terminal of the summing operational amplifier 75 through the buffer operational amplifier 74, and is also fed back to the inverting input side of the operational amplifier 69. On the other hand, the negative side of the signal ■i at the terminal 68 is connected to the buffer operational amplifier 7.
1 and is supplied to a capacitor 77 through a diode 76. The voltage charged in the capacitor 77 is transferred to the buffer FET.
The signal is supplied to the non-inverting input terminal of the addition operational amplifier 75 in the next stage through 78, and is also fed back to the inverting input terminal of the operational amplifier 71. In this way, the peaks of the respective polarities are charged and held in the capacitors 73 and 77 at each polarity switching point, that is, each zero crossing point, of the input signal Vi, and this is alternately applied to the output VO.
A (FIG. 7) appears at terminal 79. The FET switches 81 and 82 are turned on by the output of the monostable multivibrator (not shown) triggered by the output of the OR circuit 47 shown in FIG. (2) The peak point detection circuit 11 is reset for each zero crossing of i. With the above configuration, the seventh
As shown in the figure, the peak voltage of the voltage from the zero crossing point of the input signal Vi to the next zero crossing point, that is, the peak value within the adjacent level crossing is the output (2) immediately before resetting the capacitors 73 and 77. It is detected at terminal 79 as ``9''. The preamplifier 14 for amplitude probability density detection is composed of an operational amplifier 83, for example, as shown in FIG.

The mask signal detection circuit 9 outputs a signal for inhibiting signal processing when the input signal i is extremely small or too large, and is configured as shown in FIG. 5, for example. terminal 8
The input signal ■i from 4 is compared with the reference voltage from the variable voltage setter 86 by a comparator 85, and if Vi is larger, the comparator 85 outputs a constant positive voltage. This comparator output is level-converted by a level converter (not shown), and then its rising edge is extracted by a differentiating circuit 86.
The output triggers the monostable multivibrator 87 in the next stage. This monostable multivibrator 87 is a retrigger type, and if the time from the positive side of the input signal i waveform to the next positive side is longer than the operation stabilization time of the monostable multivibrator 87, the monostable multivibrator 87 The output remains at a high level for the set time. This high level output turns on transistor switch 88 and capacitor 89 is shorted. Comparator 91 is capacitor 89
The voltage of the capacitor 89 is compared with the voltage divided by the variable resistor 90, and when the voltage of the capacitor 89 becomes higher, the output of the comparator 91 becomes zero level. The connection point between the collector of the transistor 88 and the capacitor 89 is a variable resistor 92.
If the input signal Vi is zero for more than the charging time constant determined by the capacitor 89, the monostable multivibrator 87 is not retriggered, and the output of the comparator 91 becomes -low. level, the output of the gate circuit 93 becomes a low level, and this low level is used as a short command to output the signal zero short circuit 3 in FIG.
8 and 55, and is configured so that the sampling command signal does not go to the next stage, as will be explained later. The input signal V1 from the terminal 84 is compared with the reference voltage from the variable voltage setter 94 by a comparator 95, and when the signal i is greater than the voltage of the variable voltage setter 94, the output of the comparator 95 becomes a constant positive potential.

The voltage level of the output of the comparator 95 is lowered by a level converter 956 and applied to a transistor switch 97, which is turned on and the transistor 97 converts the capacitor 9
8 is shorted. The comparator 99 compares the divided voltage of the variable resistor 101 to which a constant voltage is applied and the voltage of the capacitor 984, and when the voltage of the capacitor 98 becomes higher than the former voltage, the comparator 99 outputs a high level output. The voltage of variable resistor 101
If the voltage is lower than the divided voltage, it outputs a zero level. The capacitor 98 is charged from the power supply through the variable resistor 102, and if the input signal Vi continues to be extremely large for a longer time than the charging time constant of the variable resistor 102 and the capacitor 98, the transistor 97 is turned on during that time. , the output of the comparator 99 goes to zero level, and the output of the gate circuit 93 goes to low level to prevent the sampling command signal from being applied to the next stage. By turning on the switch 103, the output of the gate circuit 93 is forced to a high level of 9, thereby inhibiting these signal mask operations. The already mentioned peak point detection circuit 11 and waveform duration detection circuit 12
, the wave area detection circuit 13, and the output V processed by the preamplifier 14, respectively.

A to 7V0D are classified and cumulatively stored in the data cumulative storage units 21 to 24 shown in FIG. 1, respectively, according to a sampling command.
These cumulative storage units 21 to 24 can have the same configuration, for example, as shown in FIG.
For example, VOA is input to analog input terminal JlO5. When a sampling command signal is input to the sampling command terminal 106, if the output of the gate circuit 93 in FIG. The pulse shift circuit 109 in the control circuit 28 is driven. A signal is sent from terminal B of shift circuit 109 to sample hold circuit 111, and analog input V at terminal 105. Al, that is, the peak value within the level crossing of the signal i is sampled and held. Immediately after this, the pulse shift circuit 109 outputs a signal from its terminal C, and the A/D converter 112 converts the output analog voltage of the sample hold circuit 111 at the previous stage into a digital voltage. This A/D converter 1
12, a 7- to 12-bit precision one is used for economic reasons, and in this embodiment, an 8-bit precision one is used. A
When the conversion of the analog value into a digital value is completed by the A/D converter 112, a signal is output to the terminal ST of the A/D converter 112, and the converted digital value is latched by the latch circuit 113.

Using this digital value Xi as an address, the next-stage memories 114a to 114c are accessed via the bus 124, and the stored contents of the accessed address Xi in these memories are first transferred to the latch circuits 115a to 115a by a command from the terminal E of the pulse shift circuit 109. 115c, and the outputs of the latch circuits 115a to 115c are sent to adders 116a to 116c.
is input. Each word 4 of memories 114a-114c
In the case of bits, the adders 116a to 116c are full adders (one full adder), such as 7483 made by Texas Instruments, and the input terminals 8, BJ, B, of the adder 116a, adders 116b, 1116c, etc. are used. Each input terminal? ~B4 are respectively grounded, and by setting only the terminal B1 of the adder 116a to a high level, only one bit is added to one addition input A1~in, and the adder 116
Each carry output of a, 116b is sent to an adder 116b, 116.
The configuration is such that the data is sequentially supplied to c. Next, adder 116a~
The parallel 4-bit addition output of 116c is sent to the memory 11 through reset gates 117a to 117c, respectively.
4a to 114c, and are addressed and written by the digital value Xi of the latch circuit 113.

The memories 114a to 114c are, for example, Intel-2
An example is shown here in which three 101 4-bit x 256 memories are used, and the storage capacity for one address, that is, one digital value Xi, is 12 bits. A write command to memories 114a to 114c is given from terminal D of pulse shift circuit 109. With the above configuration, an analog value ■ is input from the input terminal 105 for each sampling command signal of the saw cycle.

An operation is performed in which A is converted into a digital value, the digital value is used as an address to read out the memories 114a to 114b, 1 is added to the read content, and the result is written into the memories 114a to 114c again. For example, as shown in FIG. 9, the stored contents of the memories 114a to 114c for a plurality of sampling commands within a certain period are Fl, f2, .
...Fn, that is, a memory indicating that the digital value X1 has occurred f1 times is obtained. For example, as shown in Fig. 9, if each number of Fl, f2...Fn is expressed as a vertical line and expressed for each Xl, X2...Xn on the horizontal axis, a histogram is obtained. You will get it.
Therefore, the output VOA of the peak point detection circuit 11 is connected to the terminal 105.
, the input signal V is supplied to the memories 114a to 114c.
The distribution of peak values within j adjacent level crossovers is obtained.

In this case, the gate 108 in FIG. 6 constitutes the gate circuit 15 in FIG. The sampling point detection circuit 8, the peak value detection circuit 11, and the gate circuit 15 constitute a means for detecting the peak value within the adjacent level crossover of the electroencephalogram electrical signal, and the cumulative storage section 21 constitutes a means for obtaining the distribution of the detected peak value. It consists of The output ■ of the waveform duration detection circuit 12 is input to the input terminal 105 in FIG.

As is clear from the above description, if B is supplied, the distribution of level crossing intervals of the input signal Vi can be obtained in the memories 114a to 114c. In this case, gate 108 in FIG.
corresponds to gate 16 in FIG. Sampling point detection circuit 8, waveform duration detection circuit 12, gate circuit 16
constitutes means for detecting the length of the level crossing interval of the electroencephalogram electric signal, and the cumulative storage section 22 constitutes means for obtaining the distribution of the detected length. Similarly, sampling point detection circuit 8
, the waveform area detection circuit 13, and the gate circuit 17 constitute means for detecting the waveform area within adjacent level intersections of the electroencephalogram electric signal, and the cumulative storage section 23 constitutes means for obtaining the distribution of the detected area. The contents written in the memory I rivers 14a to 114c are based on the timing of the addition mentioned above and the data processor 2.
7 (Fig. 1) except when reading the memory.
Addresses that change sequentially by an address generator 118 in 8 are given to memories 114a to 114c, and the memory contents read at this time are latched to latch circuits 119a to 119c and supplied to the next stage multiplier 1) 21. Its output is D/
The signal is output as an analog output to a terminal 123 through an A converter 122, and is supplied to the recorder 25 and display device 26 in FIG. 1 for display and monitoring.

The multiplier 121 multiplies the outputs of the latch circuits 119a to 119c by the address values of the memo 5s 114a to 114c at the time of reading them as a multiplier, and a bit slice method using a combination of channel selector ICs can be used. If the address switching speed of the address generator 118 is set, for example, every 0.5 seconds or 1'' seconds, the analog O output of the terminal 123 is used for the recorder 25, and the switching speed is set, for example, every 1 to 100 microseconds. Terminal 12
3 analog outputs are used for display 26. Address bus 124 for memories 114a-114c is
Through the tristate type 1C gate 125, an address is given from the latch circuit 113 during addition, an address is given to read out the memories 114a to 114c from the data processor 27, and an address is given to be displayed on the display device 26. It is used by switching when giving

This switching priority order is configured by a combination of an AND circuit 126, NAND circuits 127 and 128, and an inverter 129, and in this example, when adding by the latch circuit 113, when reading by the data processor 27, and displaying on the display device 26. Priority priority is given when reading. The outputs of the latch circuits 119a to 119c are supplied to the data bus 131 through a tri-state buffer circuit 132,
It is used for reading from the data processor 27.

This data bus 131 may be directly connected to the memories 114a to 114c through a tristate buffer circuit 132. In FIG. 6, if a low level is supplied to the mask signal input terminal 107 from the gate circuit 93 in FIG.
Sample command signals are prohibited from entering this data accumulation store. Next, to obtain the amplitude probability density distribution of the signal, the input signal Vl is inputted to the analog input terminal 105 in FIG. 6 through the preamplifier 14 in FIGS. 1 and 4.

A pulse with a fixed period, for example, every 100 psec or every 1 msec, is input from a separately provided pulse oscillator (not shown) to the input terminal 106 of the sample command signal shown in FIG. The above operation is performed, and the amplitude probability density 5 degree distribution is stored in the memories 114a to 1.
14c. The preamplifier 14, a pulse oscillator (not shown), and a gate circuit 18 constitute a means for detecting the amplitude of the electroencephalogram electrical signal at each fixed period, and the cumulative storage section 2
4 constitutes means for obtaining an amplitude probability density distribution of the detected amplitude. The series of processing results explained above are
An example is shown in the figure.

Figure 8 ■. D is a distribution curve showing the amplitude probability density distribution obtained in the data cumulative storage section 24, and 0A in the same figure is a curve showing the distribution of peak 4r peak values between zero crossing points obtained in the cumulative storage section 21. , 20c and 20B in the figure are curves showing the area distribution between zero crossing points obtained in the cumulative storage units 23 and 22, respectively, and the time interval (interval length) between adjacent zero crossing points. The data processor 27 in FIG.
The data indicating each distribution obtained in each of 24 to 24 is taken in, and the standard deviation σ is determined for each distribution.

The data processor 27 constitutes a means for obtaining the standard deviation.
These distributions can be obtained over a relatively short period of time, over a relatively long period of time such as several hours, and over multiple induction points.
In other words, from the information obtained for each measurement point and the deviation of the brain waves when stimulating the subject, we can determine the pattern of the distribution curve, that is, the pattern of the shape or a certain singular point. Evaluations can be made based on the number of times and frequency, etc.

Furthermore, evaluations are made using the mean value X and standard deviation σ of each of these distributions, evaluations are made using X and σ for each singular point group within each distribution curve, that is, each population, extraction comparison of singular points, and from these results. By comparing with similar patterns and data obtained for various previously known symptoms, it is possible to determine whether the disease is normal, abnormal, or abnormal.

These operations can also be performed online by the data processor 27. In this invention, in particular, the standard deviation σ of the above-mentioned various distributions can be calculated and comprehensively evaluated.

The standard deviation σ is calculated by the data processor 27. That is, numbers f1 to Fn for each of the digital values X1 to Xn are read out from each of the data cumulative storage units 21 to 24, and the following calculation is performed from these numbers. 10th
Figures A to C show examples of various standard deviations σ obtained as described above.

In these figures, the horizontal axis represents time, the curve σ9 represents the standard deviation of the peak distribution between zero crossing points, the curve σB represents the standard deviation of the interval distribution between zero crossing points, and the curve σ represents the standard deviation of the interval distribution between zero crossing points. is the standard deviation of the area distribution between zero crossing points, and the curve σ. 10A shows the standard deviation of the amplitude probability density distribution, respectively.
Figure 0 B shows the data of a patient with uremia, and Figure 10 C shows the data of a patient with cirrhosis, where ■, ■, and ■ indicate the severity of the symptoms, where ■ is in a coma, ■ is in a slightly comatose state, and ■ is in a slightly comatose state. is a state of consciousness. In Fig. 10A, in the coma state ■, σB increases, and σA, σ. decrease together, but σ. There is not much change. In FIG. 10B, σA, σC, and σD change depending on the symptoms, but σ8 does not change. In FIG. 10C, σ8 does not change, σo changes little, and σA and σc change relatively greatly. From these, standard deviation σ9
It is not possible to make a correct judgment by looking at only one of ~σo. Combining all of these standard deviations σ~σD,
It is understood that various evaluations and diagnoses become possible. In this way, current brain wave information such as symmetry of the left and right front and back of the head, hypnotic waves, sound stimulation waves, optical stimulation waves, epileptic waves, brain waves in various medical conditions, and waves in unconsciousness can be statistically compared to normal people. Because comparative studies can be performed faithfully, this method is extremely effective, including in determining the course of disease progression.

Furthermore, it can be effectively used not only for electroencephalogram diagnosis but also for evaluation of various biological information. In the above, the zero crossing point of the brain wave is used as the starting point, but the crossing point with a certain level other than the zero level may be used as the starting point.In short, the processing may be performed using the level crossing point including zero as the starting point.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an example of an electroencephalogram diagnostic apparatus according to the present invention, FIG. 2 is a block diagram illustrating a sampling detection circuit 8, a time interval detection circuit 12, and an area detection circuit 13; 3
The figure shows a block diagram showing an example of a peak detection circuit, FIG. 4 is a connection diagram showing an example of the preamplifier 14, FIG. 5 is a circuit diagram showing an example of a mask signal detection circuit, and FIG. 6 shows a data accumulation storage unit. A block diagram showing an example, FIG. 7 is a waveform diagram showing an example of signal processing, FIG. 8 is a graph showing various distribution curves obtained, and FIG. 9 is a waveform diagram showing an example of signal processing.
The figure shows an example of storage in the memories 114a to 114c.
Figure 0 is a graph showing various standard deviations. 1: Head, 2: Electrode, 5: Pattern switch, 8: Sampling detection circuit, 9: Mask signal detection circuit, 11: Peak value detection circuit, 12: Time interval detection circuit, 13: Area detection circuit, 21- 24: data accumulation storage unit, 25: recorder, 26: display device, 27: data processor, 28: control circuit.

Claims (1)

[Claims] 1 means for extracting brain waves as electrical signals, means for detecting the level intersection of the extracted electrical signal with a predetermined level, means for detecting the length of the interval between the detected level intersections, and means for obtaining a distribution of detected interval lengths, means for detecting peak values within adjacent level crossings of said electrical signal, means for obtaining a distribution of said detected peak values, and means for obtaining a distribution of said detected peak values within adjacent level crossings of said electrical signal. means for detecting a waveform area within the area, means for obtaining a distribution of the detected waveform area, means for detecting the amplitude of the electrical signal at each fixed period, and obtaining an amplitude probability density distribution of the detected amplitude. An electroencephalogram diagnostic device for comprehensively evaluating electroencephalograms, comprising means and means for obtaining standard deviations of each of the above-mentioned distributions.