JPS6046586B2 - Communication control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a communication control device, and particularly to improvements in the control of start bits and stop bits in the control of character assembly and disassembly.

In a serial start-stop line, a start bit is added before the data, and a stop bit is added after it, and the data is sent out onto the line.

This bit is necessary to synchronize transmission and reception. FIG. 1 shows an embodiment of the prior art.

In FIG. 1, transmission data transferred from the processing device qPU1 is received by the processing device connection circuit CA2 and sent to the line control circuit CS4 via the central control circuit CC3. The line control circuit CS4 puts the transmission data into the parallel data field PDF5, performs transmission start processing, moves the transmission data including a start bit and stop bit into the serial data field SDF6, and starts transmission. The transmission data including the start bit and stop bit entered into the serial data field SDF6 is subjected to character decomposition processing, and sent bit by bit to the transmission data bus SBUS7. Line connection circuit LS8, which has received one bit from transmission data bus S and BUS7, transmits it to modem interface 9 according to the transmission timing. The received data (including start bit and stop bit) input from the modem interface 9 is sampled by the line connection circuit LS8 and sent as 1-bit data to the received data bus R,
It is sent to BUS10. Receive data bus R, BUSI
The serial data field SDF6, which receives one bit from O, includes a start bit and a stop bit, and performs character assembly processing. The serial data field SDF6 transfers the received data to the parallel data field PDF5 when one character is assembled. The data in the parallel data field PDF5 is sent to the processing device connection circuit CA2 via the central control circuit CC3. The processing device connection circuit CA2 transfers the data to the processing device CPUl. As described above, in the conventional technology, start bits and stop bits are transmitted and received using the same processing as data bits, which causes the following problems. (a) Since the start bit and stop bit are processed in the same way as data bits and character assembly/disassembly processing is performed, the line control circuit must take in and send out the start bit and stop bit and perform character assembly/disassembly processing.

Therefore, since processing time for start bits and stop bits is required, there is a problem that the number of accommodated lines is reduced.
(b) Since character assembly and disassembly is performed including a start bit and a stop bit, the character assembly and disassembly register (SDF6 in FIG. 1) requires a start bit and stop bit register.

Therefore, there is a problem in that each line must be provided with a start bit and stop bit register. The purpose of the present invention is to solve the above-mentioned problems by processing the start bit and stop bit without controlling them in the line control circuit that performs character assembly and disassembly, thereby increasing the number of lines that can be accommodated. The purpose of the present invention is to provide a wide variety of communication control devices.

The feature of this invention is that a primary bit stop pit instruction signal (a signal indicating that the next bit of transferred data is a stop bit) is inserted into the interface between the buffer circuit, the circuit, and the control circuit. A next bit stop pit instruction signal is sent from the control circuit to the buffer circuit based on the contents of the character assembly register of the control circuit.

The buffer circuit that receives the next bit stop pit instruction signal suppresses data transfer and request signals to the control circuit when transmitting and receiving start bits and stop bits. This eliminates the need for the control circuit to control the start bit and stop bit. Next, embodiments of the present invention will be described in detail using the drawings.

FIG. 2 shows a circuit functional logic diagram of a communication control device according to an embodiment of the present invention.

The line control circuit is composed of PDFlOl, SDFlO2 and a control circuit 105.

The buffer circuit also includes a received bit transfer request latch 108.
, a transmission bit transfer request latch 109, a next bit stop pit (NXTSP) latch 110, and a transmission/reception control circuit 111. PDFlOl holds data in character units. SDFlo2 is data bus AB
It is connected to PDFlOlno via USlO3,
Performs serial/parallel conversion. That is, in the case of transmission, serial-to-parallel conversion involves sending character data bit by bit to a buffer circuit. In the case of reception, data sent in 1-bit units from the buffer circuit is assembled into characters. 1-bit transmission bus S. BIT,
BUSlO4 is connected to the control circuit 105 from the bit sending port of SDFlO2.

1-bit reception bus R. BIT. BUS1O7 is connected from the control circuit 105 to the bit receiving area of SDF1O2.

The control circuit 105 is serial. Parallel conversion, PDFlO
1, SDFlO2, and the buffer circuit control circuit interface 106. A buffer circuit control circuit interface 106 that connects the control circuit 105 and the buffer circuit includes a transmission control circuit 111 between the control circuit 105 and the buffer circuit, and a transmission bit request latch S. RDY latch 10
9. Receive bit transfer request latch R.9. RDY latch 108
, N indicating that the next bit is a stop bit
The XBP latch 110 is connected to the XBP latch 110. Further, the control circuit buffer circuit interface 106 is connected to the control circuit control interface 119, R. RDY signal 112, S. R
DY signal 113, NXTSP signal 114, ST. R. R
It is composed of a DY signal 121. The transmission/reception control circuit 111 is connected to the R. RDY latch 108, S. It is connected to the RDY latch 109 and the NXTSP latch 110, and to the modem interface 120. Note that the input signal to the line control circuit is a series of character data transferred in parallel character by character. Furthermore, the input signal that the buffer circuit receives via the modem interface 120 is a series of character data that is serially transmitted bit by bit, and a start bit and a stop bit are added to the beginning and end of each character data, respectively. has been done. (a) Operation during transmission The character data prepared in SDFlO2 is shifted one bit at a time and sent to S. BIT. Send to BUSIO4.

The 1-bit shift of SDFIO2 is performed by the control circuit 105 using the S. A 1-bit request signal S.D., which is a transmission data request, is sent from the RDY latch 109. This is performed when the RDY signal 113 is received and the sending of the transmission data to the transmission/reception control circuit 111 is completed. Data transmission is performed by the method described above, and the control circuit 105 sends out the bit before the stop bit as the bit stop pit signal NXTSP signal 11.
Send 4. NXTS receives NXTSP signal 114
The P latch 110 holds this state, and the transmission/reception control circuit 1
The modem interface 120 receives a 1-bit transmission completion signal (transmission complete of the bit before the stop bit) from the control circuit control line 115 from the NXTSP latch control line 118 and puts the transmission/reception control circuit 111 in the stop bit transmission state. sent to. Start bit transmission ready signal 1 when stop bit is transmitted
21 to the control circuit 105. When the control circuit 105 receives this signal, it sends a start bit to the transmission/reception control circuit 111 at the timing when the transmission data is passed from PDFlOl to SDFlO2. When the start bit has been sent, all NXTSP latches 110 are set. That is, when the transmission/reception control circuit 111 transmits a start bit and a stop bit, the transmission/reception control circuit 111 sends an S. RDY latch 109 sends a transmission request signal S. The transmission of the RDY signal 113 is suppressed. Next, in order to transmit the data, the buffer circuit is connected to the S. The RDY latch 109 allows the S. The modem interface 120 sends the RDY signal 113 and receives data from the control circuit 105.
Send to. Repeat the above operations in sequence. (b) Operation during reception The transmission/reception control circuit 111 uses the modem interface 120
The data is received by sampling the received data coming from the .

After the control circuit 105 shifts the data in the SDFIO2 by 1 bit, the control circuit 105 shifts the data in the R. RDY latch 10
8 to receive data request signal R.8. When RDYll2 is received, the reception data is received from the transmission/reception control circuit 111. Data transmission is performed in this manner, but when the control circuit 105 receives the bit before the stop bit, it sends out the next bit stop pit signal (NXTSP signal) 114.

This causes the NXTSP latch 110 to receive this signal.
is set and maintains this state. Next, if the data received by the transmission/reception control circuit 111 is a stop bit, the transmission/reception control circuit 111 transmits the NXTSP signal via the control line 118.
The latch 110 is held and a start bit reception state is created. The start bit to be received next is in the start bit reception state due to the control signal of the NXTSP latch 110 obtained from the control line 118, so the transmission/reception control circuit 111
performs start bit determination, but R. R.D. sent from RDY latch 108. The RDY signal 112 is suppressed. Therefore, no start bit is sent to control circuit 105. After completion of start bit reception, NX'ISP latch 1
10 are all reset, the transmission/reception control circuit 111
When R. receives the next data bit, R. RDY latch 1
By 08 R. An RDY signal 112 is sent, and 1-bit data is sent to the control circuit 105. That is, when the transmission/reception control circuit 111 receives a start bit and a stop bit, it sends an R. A reception request signal R. The transmission of the RDY signal 112 is suppressed. Data reception is performed by sequentially repeating the above operations. With the configuration as described above, the following effects can be obtained in the present invention. (a) By providing a next bit stop pit instruction signal, start bits and stop bits can be transmitted and received without transmitting or requesting them from the buffer circuit to the character assembly/disassembly control circuit. Since the control circuit does not need to control and hold the transmission/reception of start bits and stop bits, the number of character assembly/disassembly registers can be reduced, and the number of lines accommodated can be increased.

[Brief explanation of drawings]

FIG. 1 is a functional block diagram of a conventional communication control device, and FIG. 2 is a functional logic diagram of a communication control device showing an embodiment of the present invention. Explanation of symbols 101...Character holding circuit, 10
2...Character disassembly and assembly circuit, 103...Transfer interface from character holding circuit to character disassembly and assembly circuit, 104...Character disassembly,
Transmission 1-bit data line from assembly circuit, 105...
. . . Control circuit for controlling transmission and data transmission and reception, 106 . . . Interface between buffer device and control circuit, 107 . . . Reception 1-bit data line,
108...Receive data transfer request control latch, 1
09... Transmission data request control latch, 110...
...Next bit stop bit latch, 111...
...Transmission/reception control circuit, 112...Reception data transfer request line, 113...Transmission data request line, 1
14...Next bit stop pit instruction line, 115...
... Control circuit control line, 116 ... Reception data transfer request latch control line, 117 ... Transmission data request latch control line, 118 ... Next bit stop pit Indication latch control line, 119...Control circuit control interface, 120...Modem interface, 121...Start bit transmission preparation completion instruction line.

Claims (1)

[Claims] 1 In a communication control device that connects a serial start-stop line and assembles characters of bit serial data input from the line and transfers it to a processing device, or disassembles character data from the processing device and sends it to the line as bit serial data, A buffer circuit that buffers the bit data received from the formula circuit or transmit bit data and transmits and receives it to the serial asynchronous circuit, and a buffer circuit that assembles characters of the received bit data or decomposes the transmitted characters into bit data and transfers the transmitted and received bit data from the buffer circuit. It consists of a control circuit that transfers bit data when a request is made, a buffer circuit, an interface between the control circuits, and a next bit stop bit instruction signal. The buffer circuit that receives the instruction signal holds the instruction signal until it is reset after completion of transmission and reception of the start bit, thereby suppressing requests for transmission and reception of the stop bit and the subsequent start bit to the control circuit. communication control device.