JPS6045390B2 - digital clock - Google Patents

Description

[Detailed Description of the Invention] <Technical Field> The present invention relates to a digital clock, and in particular, to prevent setting times from being set to 00:00 minutes when a memory for storing set times is cleared to 0○00. This is related to digital clocks.

<Prior art> Conventionally, in digital clocks that store multiple times, after a match with a certain memory has been detected,
The time may be specified again.

In preparation for such a case, the memory may be cleared, but even if the memory is cleared to 0000, the time still includes 0○:00, so the time in this memory will match that time. <Object of the invention> In order to prevent the above-mentioned situation, the present invention provides a flip-flop in each of the plurality of memories, and the flip-flop has the following functions:
The purpose is to store the state of the corresponding memory, that is, the state in which the time is stored or the state in which it has been cleared, and in the latter case, the designation of the memory can be removed by a jump.

<Example> An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a block diagram of a digital clock according to the present embodiment, in which a time reference circuit 1 sets the current time and changes the time according to a reference clock signal A with an accurate frequency. is supplied to the display device 2 to display hours, minutes, and seconds.

For time correction, an input device 3 such as a 10 key is provided, and the signal thereof is stored in a time correction memory 4.

When the time correction start signal is generated by the switch 5 attached to the input device 3, the circuit 1 generates a pulse signal that is much faster than normal, such as a speed that allows a shift between 1 to 2 seconds to be performed. It is driven by the clock pulse B, and this is continued by the signal of the coincidence detection circuit 6 until the contents of the time reference circuit 1 and the time correction memory 4 match, and when they match, the output signal from the circuit 6 is Therefore, it is switched to operate with the normal clock signal A. The above time correction circuit will be explained in detail with reference to the circuit diagram shown in FIG. In Figure 2, 11, 19 are JK flip-flops, 14, 15, 16
, 18 are D flip-flops, and 4 is a time correction memory consisting of a shift register.

1 is a time reference circuit consisting of a shift register.

22 is an exclusive OR circuit.

In order to correct the time, time correction data is input in advance to the NAND gate 23 and the ORCATE 3 using the input device 3 such as the 10 key.
1 to the memory 4, and its contents are stored in a circular circuit driven by a clock C and passing through a NAND gate 20 and an OR gate 31. Next, when the standard time coincides with the time input into the correction memory, when the time correction start switch 5 is operated, a start signal is input and the JK flip-flop 11 is set.

Therefore, the AND gate 34 outputs the reference pulse signal A to the circuit 1.
Prevent it from being entered. A very fast pulse B is input to the terminal 13 of the 3-AND gate 12, and the D flip-flops 14, 15, and 16 are all in the reset state, so the output terminal of the AND gate 12 becomes a high level.

The output of gate 12 is applied to time base circuit 1 via OR gate 32 to change the time of circuit 1. Clock pulse B sets flip-flops 14, 15, and 16 in sequence.

When flip-flop 14 is set and flip-flop 15 is reset, AND gate 1
7 is satisfied, and the flip-flop 19 is set at its output.

Flipf. When the mouth knob 15 is set, its output is applied to one of the AND gates 25, so the gate output of the exclusive OR 22 passes through the gates 25 and 24.
It is added as a reset input to the flip-flop amplifier 19. If the contents of the time reference circuit 1 and the time correction memory 4 do not match, the output of the exclusive O 22 is at a high level.

When the flip-flop 15 is set and the flip-flop 16 is reset, an output is obtained from the AND gate 33 and the flip-flop 18 is set.

This output is applied to the JK flip-flop 11 via the AND gate 35. Flip-flop 14, 15,
16 are all set, the conditions of the gate 36 are met and a signal is supplied to the 3-AND gate 13 via the inverter 37.

In this way, the operation returns to the initial state and the above operations are repeated until the time reference circuit 1 and the correction memory 4 match.

A time changing pulse is applied to the circuit 1 from the AND gate 12 via the gate 32 and counted up, and when the content matches the memory 4, the flip-flop 15
Once set, a low level output is obtained from the exclusive OR 22 and is applied to the flip-flop 19 via gates 25 and 24, but the flip-flop 19 cannot be reset and the set state cannot be maintained. I will.

Therefore, when the flip-flop 16 is set, the AND gate 26 becomes valid and outputs a high level, resetting the flip-flop 11. Gate 12 is therefore disabled and prevents clock pulse B from being input to time reference circuit 1. On the other hand, by resetting the flip-flop 11, a signal is supplied to the AND gate 34, and a clock signal A having an accurate frequency is input to the circuit 1 through this gate 34. The signal from the circuit 1 is input to the time display conversion circuit 8, where it is converted into a 6-digit time display signal, and supplied to the display to display hours, minutes, and seconds.

Note that a clock B is input to the flip-flop 19 so that the flip-flop 11 is always reset even when the circuit 1 and the memory 4 match and there is no reset pulse.

The time is corrected as described above, and the digital clock operates normally thereafter. The input device 3 of this embodiment,
By using the coincidence detection part 6 and the time reference circuit 1 and preparing a plurality of memories 9a and 9b, it can be used as a timer for controlling the on/off of external electrical equipment.

If this circuit has multiple memories, the time may be specified again after a match with a certain memory is detected, so even if you clear the memory to 0000 in preparation for this case, the time will be set to 00:00. Since there is 00 minutes, this memory will match at this time.

In order to prevent this, the state is memorized by a flip-flop for memory specification, and when this is invalid, a signal that is specified is generated and jumped, and the memory specification is removed. There is. Therefore, the fourth
The figure shows a circuit that operates sequentially from the earliest time set in multiple memories when specifying a memory, and automatically jumps if there is no time data in that memory.

In FIG. 4, numerals 48 to 51 are flip-flops used to determine the validity or invalidity of the memory. This is set when time data is input into the memory from the outside, and reset when the match detection for that memory is completed. 52 and 53 are T-type flip-flops for determining the order of memories, and 66 is a time-set memory selection circuit.

The memory flip-flop 48 does not have a jump function, and the flip-flops 49 to 51 have a jump function.

Now, flip-flop 48 is set, flip-flops 49 and 50 are reset, and flip-flop 51 is set.
Suppose that is a set.

That is, the time is set in the memory corresponding to the flip-flop 51. In the initial state, the flip-flops 52 and 53 are in a reset state, so the AND gate 5
5 is a low level output, and the AND gate 59 is a high level output and becomes invalid. When the time set in the memory corresponding to the flip-flop 48 and the time reference circuit match, signal 1 is output, and this is added to the AND gate 60, so that the gate becomes valid and the time reference circuit matches the time set in the memory corresponding to the flip-flop 48.
is reversed. At the same time, flip-flop 48 is reset. The flip-flop 52 is set and the AND gate 56 goes high, but the set output of the flip-flop 49 is applied to the other side of the gate 51, and since the flip-flop 49 is reset in the initial assumption, the gate 61 is a high level output, and the gate 54 is enabled.

Since the output of gate 55 is high, gate 59 is controlled by the signal applied to terminal 64. terminal 64
This gate 5 contains the signal that is always output.
9 becomes valid, flip-flop 52 is inverted again,
At the same time, the flip-flop 53 is also inverted. Therefore, the output of the gate 57 becomes high level, but the output of the flip-flop 50
Since the output of the gate 62 is also reset, the output of the gate 62 becomes high level and operates in the same manner as described above, the flip-flop 52 is inverted and the gate 58 is enabled.

In this way, flip-flops 49 and 50 are jumped.

Next, since flip-flop 51 is set, gate 63 has a low level output and gate 59 is disabled.

Therefore, the memory corresponding to flip-flop 21 is selected. Since gate 59 is disabled, flip-flops 52 and 53 are stopped. In this way, flip-flop 51 is selected. After the above selection, the above-described time matching circuit detects matching with the time reference circuit.

When the times match, a match signal 1 (for example, the output of the AND gate 26 in FIG. 2) is obtained, which turns the external electrical equipment on or off. When the match detection is finished, the flip-flop 51 is reset for the match signal 1.

<Effects> As described above, the digital clock of the present invention has a plurality of memories in a valid state or a cleared invalid state storing a plurality of times, and a memory provided in each of the plurality of memories and a corresponding memory. a flip-flop that stores the state of the flip-flop; a selection device that jumps over the flip-flops that are in an invalid state and selects a flip-flop that has a valid state; and a memory that stores a memory corresponding to the flip-flop selected by the selection device. Since it has a detection means for detecting a coincidence between the current time and the current time, the memory can be zeroed out.
Even if 000 is cleared, it does not mean that the time has been set to ○0:00, and no inconvenience will occur.

[Brief explanation of the drawing]

FIG. 1 shows a block diagram of the digital clock of the present invention, FIG. 2 shows a time matching circuit diagram, FIG. 3 shows a time chart, and FIG. 4 shows a circuit diagram for specifying a memory. 1... Time reference circuit, 6... Coincidence detection circuit, 9a, 9b... Memory, 48, 49, 5
0, 51, 52, 53... flip-flop, 54
,55,56,57,58,59,60,61,62,
63...gate, 66...selection circuit.

Claims (1)

[Claims] 1 A plurality of memories that are in a valid state that stores time or a cleared invalid state, a flip-flop that is provided in the plurality of memories and stores the state of the corresponding memory, and a flip-flop that is in an invalid state. selection means for jumping through the flip-flops to select a flip-flop whose state is valid; and detection means for detecting coincidence between the current time and the time stored in the memory corresponding to the flip-flop selected by the selection means. A digital clock characterized by having and.