JPS6040726B2 - Ultra high frequency oscillation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an ultra-high frequency oscillation circuit using an active three-terminal element as an oscillation element and a dielectric resonator having a high Q value. The purpose is to

As a local oscillator for a mixer in the 1-common HZ band, we use an oscillator that uses a Gunn diode, which is a two-terminal negative resistance element, whose frequency is stabilized by a dielectric resonator, and a GaAs field-effect transistor (hereinafter abbreviated as GaAsFET), which is an active three-terminal element. do)
An oscillator whose frequency is stabilized using a dielectric resonator is known.

Compared to an oscillator using Gandhi auto, Ga trillion FET
Oscillators using GaAsFETs have features such as high efficiency, low bias, and small current, and GaAsFET oscillators can also be used as local oscillators used in down converters for primary day 2-band SHF broadcasting, which has recently become a hot topic. It has an attractive feature. active 3
Oscillation circuits using Ga carrier FETs as terminal elements are often used because the integrated circuit configuration using microstrip lines or the like is relatively easy to manufacture.

FIG. 1 shows a conventional example of an oscillation circuit using a GaAsFET and a dielectric resonator for frequency stabilization. Figure 1 shows a GaAsFET oscillator circuit with a grounded drain.
A microstrip line 3 having a length of 1 (21/4 skin length) and having an open end is connected to the drain terminal 2 of the GaAsFETI.

Similarly, a microstrip line 6 whose other end is terminated with a load resistor 5 is connected to the source terminal 4 of the GaASFETI. 7 is a capacitor for blocking direct current.

The gate terminal 8 of the Gabon FETI is a microstrip line whose other end is terminated with a dummy resistor 11 formed from a resistive element 9 and a ground conductor 101! 2 are connected.

Reference numerals 13 and 14 are chokes for high frequency blocking, and reference numeral 15 is a bias resistor for applying a bias voltage between the gate and the source. 16 is a dielectric resonator, which is located at a distance of 12 from the gate terminal 8.
In this respect, if the GaAs FETI is coupled to the microstrip line 12 and the distance 12 is selected to be an appropriate length, the GaAs FETI will oscillate at the resonant frequency of the dielectric resonator 16.

In the conventional example shown in FIG. 1, a gap capacitance of a microstrip line is used as the capacitor 7, or a beam lead capacitor for ultra-high frequencies with low loss is used.

Although the method using the gap capacitance of the microstrip line is easy to manufacture, it has the drawback that a large capacitance cannot be obtained and the characteristic impedance of the microstrip line 6 is greatly disturbed. Further, although the method using a beam lead capacitor does not disturb the characteristic impedance of the microstrip line 6, it has the disadvantage that it is difficult to handle and expensive. Furthermore, dummy resistor 1
The resistance element 9 and the ground conductor 10 forming the microstrip line 12 are patterned on the same plane as the microstrip line 12 for ease of manufacturing.
The impedance when looking at the ground conductor 10 side from the surface is that even if it is grounded in terms of direct current, it is not necessarily grounded in terms of ultra-high frequencies, and it is grounded over a wide range from low frequencies to ultra-high frequencies where GaAsFETs can oscillate. It is very difficult to do so. Therefore, the impedance of the dummy resistor 11 is not necessarily equal to the impedance of the resistive element 9.
The drawback was that the shape of 0 had to be modified in various ways. An object of the present invention is to use an interdigital DC blocking circuit instead of the capacitor 7, and to connect the ground conductor 1
By using a microstrip line with a carpel length of 1' open at both ends instead of 0, when forming the entire pattern of the oscillation circuit including the pattern of each microstrip line, the above-mentioned interdigital DC blocking circuit and the above-mentioned By making it possible to simultaneously form a microstrip line with both ends open as a pattern with a skin length of 1'4, the drawbacks of the above-mentioned conventional example are eliminated, and the low-pass filter connected to the microstrip line eliminates parasitic oscillation at low frequencies. It is an object of the present invention to provide a Ga carrier FET oscillation circuit which is an integrated circuit and has the effect of preventing the above, has a simple configuration, and is easy to manufacture.

FIG. 2 shows an embodiment of the present invention, and in the embodiments shown in FIG. 2 and the subsequent embodiments, the same parts as in FIG. 1 are given the same numbers and will be explained.

The oscillation circuit in Fig. 2 is a drain-grounded oscillation circuit like the oscillation circuit in Fig. 1, and in Fig. 2, 1 is oaA
In the sFET, the length of the drain terminal 2 with the open end is 1. A microstrip line 3 having a length of (d1/distance length) is connected.

The other end of the source terminal 4 of the GaAsFETI is a load resistor 5.
A microstrip line 6 terminated at is connected.

17 is an interdigital DC blocking circuit made of conductive foil formed in a predetermined pattern.

The resistive element 9 is connected to the gate terminal 8 of the GaAsFETI.
and a dummy resistor 19 formed by sequentially connecting in series a microstrip line 18 with both ends open and having a length of one strip length.
A microstrip line 12 terminated at is connected. 13', 14', and 20 are low-pass filters made of conductive foil formed in a predetermined pattern; 15 is a gate filter;
a bias resistor for applying a bias voltage between the sources,
21 is a resistor for preventing parasitic oscillation.

16 is a dielectric resonator, which is coupled to the microstrip line 12 at a distance 12 from the gate terminal 8, and if the distance 12 is selected to be an appropriate length, the GaAsFETI becomes the dielectric resonator 1.
6, and if the dielectric resonator 16 is removed, the oscillation will stop.

In the configuration of this embodiment, the interdigital DC blocking circuit 17 for preventing bias pressure from being applied to the load resistor 5 can be formed of conductor foil with a predetermined pattern, and can be formed using a microstrip line over a wide band around the operating frequency. The impedance of the open-ended microstrip line 18, which has a length of 1'4 and can be formed with conductive foil and is less likely to disturb the characteristic impedance of 6 and is short in size, when viewed from the right side from plane B-8, is the impedance at the operating frequency. Since the front and rear parts are short-circuited, the impedance of the dummy resistor 19 becomes equal to the impedance of the resistive element 9 in the frequency range used.

The low-pass filters 13', 14', and 20 act as chokes at the operating frequency, but the G is sufficiently lower than the operating frequency.
In the frequency range where aAsFETI can oscillate, and the impedance of the dummy resistor or interdigital DC blocking circuit deviates significantly from the impedance at the operating frequency, the dummy resistor or interdigital DC blocking circuit can sufficiently perform its original function. In the frequency range where the low-pass filters 14' and 20 disappear, the low-pass filters 14' and 20 function as a pass-through region, and the resistors 15 and 21 function as terminating resistors in the pass-through region, and the low-pass filters 14' and 20 function as terminating resistors in the pass region. Looking at the pass filter 4', 20 side, we see resistances 15, 2.
1 acts as a damping resistor, so GaAsFETI
This serves to prevent parasitic oscillations at frequencies other than the resonant frequency of the dielectric resonator 16. Therefore, the present invention has the effect of providing a low-cost integrated circuit Ga pine FET oscillator that can be simplified in configuration, easy to manufacture, and excellent in mass production without any adverse effect on the characteristics. have

FIG. 3 shows another embodiment of the present invention, in which a common source Ga
This is a melon FET oscillation circuit. 1 is a GaAs FET, and a microstrip line 3' having an open end and having a length of 13 (1'4 long, 13<1/2 wavelength) is connected to the source terminal 4.

The other end of the drain terminal 2 of the Ga melon FETI is a load resistor 5.
A microstrip line 6' terminated at ' is connected. 17' is an interdigital DC blocking circuit.

The gate terminal 8 of Ca$FETI has a resistor element 9 at the end and a microstrip line 1 with both ends open and the length of which is 1/4 skin length.
A microstrip line 12 terminated with a dummy resistor 19 formed by sequentially connecting 8 and 8 in series is connected. 13', 14', 2 low-pass filters made of conductive foil formed in a predetermined pattern; 15 a bias resistor for applying a bias voltage between the gate and the source;
1 is a resistor for preventing parasitic oscillation.

16 is a dielectric resonator which is coupled to the microstrip line 12 at a distance of 12' from the gate terminal 8;
If you choose the appropriate length, the Ga ship FETI will become a dielectric resonator 1.
6, and if the dielectric resonator 16 is removed, the oscillation will stop.

The low-pass filters 14', 20 and the resistors 15, 21 connected to them are used when the dummy resistor 19 and the interdigital DC blocking circuit 17' do not perform their functions sufficiently, and
In the frequency range where the GaAsFETI can oscillate, the low-pass filters 14' and 20 act as pass regions, and the resistor 1
5 and 21 now function as terminating resistors, and GaA
Low-pass filter 14' from terminals 4 and 8 of sFETI,
Looking at the 20 side, since the resistors 15 and 21 act as damping resistors, they serve to prevent the Ga carrier FETI from parasitic oscillation at a frequency other than the resonant frequency of the dielectric resonator 16.

In the configuration of the embodiment shown in FIG. 3, as in the embodiment shown in FIG.
The interdigital DC blocking circuit 17' can be constructed by forming the conductor into a predetermined pattern along with the microstrip line 18 with 1/4 skin length open at both ends, so the construction is simple and easy to manufacture, making it suitable for mass production. This has the effect of providing an excellent low-cost integrated GaAsFET oscillation circuit.

Furthermore, low-pass filters 14', 20 and resistors 15, 21
has the effect of preventing parasitic oscillation at low frequencies as well as the bias circuit function and choke effect. In the above embodiment, a GaFET was used as the active 3-terminal element, but any active 3-terminal element capable of oscillating at ultra-high frequencies, such as a silicon transistor, is not limited to a GaAsFET and can operate as an oscillation circuit. Needless to say.

Furthermore, in the above embodiment, the dielectric resonator 16 is coupled to the gate terminal 8 side, but the dielectric resonator 16 is coupled to the drain terminal side, and the structure is not limited to the above embodiment. A configuration in which a load is connected to the circuit, or a configuration in which a dielectric resonator is coupled to the source terminal side and a load is connected to the gate terminal side can also operate as a GaAsFET oscillation circuit, and the effect is no different from the above embodiment. There is no place.

Furthermore, in the embodiments shown in FIGS. 2 and 3, a case is shown in which the end of the low-pass filter 20 is terminated with a resistor. A GaAsFET oscillator circuit using a low-pass filter as shown in another embodiment of the figure is also conceivable. In FIG. 4, only the low-pass filter portion will be extracted and explained for simplicity, but the other portions are the same as the embodiments shown in FIGS. 2 and 3. In FIG. 4, a microstrip line is connected at one end to the gate terminal 8 of the 12GaAsFETI, one end is connected to the microstrip line 12, and the other end is connected to a resistor 21 and an inductance 22 formed by a microstrip line with high impedance. A low pass filter 20 is provided which is terminated to a ground conductor 23 in a parallel connected circuit. This low-pass filter 24 is made of GaAsF.
The gate terminal 8 of the ETI is grounded in terms of direct current, and at the same time works as a choke at the frequency used. GaAsFE
TI can oscillate sufficiently even at a frequency lower than the operating frequency, which causes parasitic oscillation, but the parallel connection circuit of the resistor 21 and inductance 22 acts as a damping circuit in the pass region of the low-pass filter 20. Parasitic oscillation can be prevented by appropriately selecting the impedance of the resistor 21 and inductance 22. Low-pass filter 2 according to the above embodiment
0 is a GaAsFET oscillation circuit which has a gain up to a frequency range sufficiently lower than the operating frequency and is susceptible to parasitic oscillation, and has the effect of preventing parasitic oscillation. As explained above, according to the present invention, by employing an interdigital type DC blocking circuit which can be formed of conductive foil with a predetermined pattern and has good characteristics as a DC blocking circuit, expensive components such as beam lead capacitors can be eliminated. By adopting a 1/4 wavelength open-ended microstrip line, which has a simple configuration and can be formed with a small-sized pattern, in place of the ground conductor, there is no adverse effect on the characteristics of the present invention. A low-cost integrated circuit that is easy to configure, easy to manufacture, and has excellent mass production.
This has the effect of providing an AsFET oscillation circuit.

In addition, GaAsF
This has the effect of preventing parasitic oscillations at low frequencies of the ET.
Furthermore, each microstop IJ top line, one end of which is connected to each terminal of the Ga carrier FET, is DC-open at the other end, or by an interdigital DC blocking circuit.
The DC bias potential of each terminal of the GaAsFET is all given through a low-pass filter, so the GaAsFET
The power supply for the sFET oscillation circuit has the advantage that any power supply can be used as a positive power supply, a negative power supply, or both positive and negative power sources.

[Brief explanation of drawings]

FIG. 1 is a wiring diagram showing a conventional common drain GaAsFET oscillation circuit, FIG. 2 is a wiring diagram showing a common drain GaAsFET oscillation circuit in an embodiment of the present invention, and FIG. 3 is a connection diagram showing a common drain GaAsFET oscillation circuit in an embodiment of the present invention. A wiring diagram showing a GaAsFET oscillation circuit, FIG. 4 is a diagram showing only a low-pass filter portion of another embodiment of the present invention. 1...GaAsFET, 6...Microstrip line, 17...Interdigital DC blocking circuit, 12, 18...Microstrip line, 13', 14', 20...Low pass filter, 16...Dielectric resonator. Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] 1. An active three-terminal element having first, second, and third terminals, and a first microstrip having one end connected to the first terminal and the other end open. a second microstrip line having one end connected to the second terminal and the other end terminated with a load; one end connected to the third terminal and the other end connected to a resistive element; A third microstrip line terminated with a dummy resistor formed by connecting a 1/4 wavelength open-ended microstrip line in series, and a third microstrip line connected to the third microstrip line. An ultra-high frequency oscillation circuit comprising: a dielectric resonator formed in the same manner as described above; and an interdigital DC blocking circuit formed within the second microstrip line. 2 The active three-terminal element is a field effect transistor, and the first
2. The super high frequency oscillation circuit according to claim 1, wherein the terminal is a drain terminal, the second terminal is a source terminal, and the third terminal is a gate terminal. 3 The active three-terminal element is a field effect transistor, and the first
2. The super high frequency oscillation circuit according to claim 1, wherein the terminal is a source terminal, the second terminal is a drain terminal, and the third terminal is a gate terminal. 4 The active three-terminal element is a field effect transistor, and the first
2. The super high frequency oscillation circuit according to claim 1, wherein the terminal is a source terminal, the second terminal is a gate terminal, and the third terminal is a drain terminal. 5 The active three-terminal element is a field effect transistor, and the first
2. The super high frequency oscillation circuit according to claim 1, wherein the terminal is a drain terminal, the second terminal is a gate terminal, and the third terminal is a source terminal. 6. The ultrasonic filter according to claim 1, further comprising a low-pass filter connected to one end of the third microstrip line and terminated with a DC or high frequency resistor at the other end. High frequency oscillation circuit. 7. The ultrasonic filter according to claim 1, comprising a low-pass filter having one end connected to the third microstrip line and the other end terminated with a parallel connection circuit of a resistor and an inductance. High frequency oscillation circuit.