JPS6037938U - A/D conversion circuit - Google Patents
A/D conversion circuitInfo
- Publication number
- JPS6037938U JPS6037938U JP1983130034U JP13003483U JPS6037938U JP S6037938 U JPS6037938 U JP S6037938U JP 1983130034 U JP1983130034 U JP 1983130034U JP 13003483 U JP13003483 U JP 13003483U JP S6037938 U JPS6037938 U JP S6037938U
- Authority
- JP
- Japan
- Prior art keywords
- reference signal
- input signal
- signal
- comparator
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 title claims description 5
- 238000010586 diagram Methods 0.000 description 6
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図はＡ／Ｄ変換回路の基本構成を示す回路図、第２
図は同回路の動作を説明するグラフ、第３図は同グラフ
の一部を拡大したグラフ、第４図はＡ／Ｄ変換の一問題
点を説明するグラフ、第５図は本考案−実施例回路の基
本的構成を示す回路図、第６図は同回路の動作を説明す
るグラフ、第７図は実施例の回路図、第８図及び第９図
は上記回路の動作を示すタイムチャート、第１０、第１
１図は夫々異る本考案の実施例を示す回路図、第１２図
は本考案をカメラの露出制御回路を応用した実施例の回
路図、第１３図は同回路の動作を説明するタイムチャー
ト、第１４図及び第１５図はそれぞれ本考案の更に他の
実施例の回路図である。
Ｋ・・・・・・コンパレータ、ＩＮ・・・・・・入力端
子、ＣＬ・・・・・・クロックパルス発生器、Ｃ・・・
・・・カウンタ、Ｄ・・・・・・Ｄ／Ａ変換器、Ｓ・・
・・・・電圧発生器、Ａｄ・・・・・・加算回路。Figure 1 is a circuit diagram showing the basic configuration of the A/D conversion circuit;
The figure is a graph explaining the operation of the same circuit, Figure 3 is a graph that enlarges a part of the same graph, Figure 4 is a graph explaining one problem of A/D conversion, and Figure 5 is the present invention-implementation. A circuit diagram showing the basic configuration of the example circuit, Fig. 6 is a graph explaining the operation of the circuit, Fig. 7 is a circuit diagram of the embodiment, and Figs. 8 and 9 are time charts showing the operation of the above circuit. , 10th, 1st
Fig. 1 is a circuit diagram showing different embodiments of the present invention, Fig. 12 is a circuit diagram of an embodiment in which the invention is applied to an exposure control circuit of a camera, and Fig. 13 is a time chart explaining the operation of the same circuit. , FIG. 14, and FIG. 15 are circuit diagrams of still other embodiments of the present invention. K...Comparator, IN...Input terminal, CL...Clock pulse generator, C...
...Counter, D...D/A converter, S...
...Voltage generator, Ad...Addition circuit.
Claims (1)
た信号を基準信号としてコンパレータに印加し、同コン
パレータにＡ／Ｄ変換すべき入力信号を印加して基準信
号と比較し、基準信号が入力信号を超過した時点を検出
して、そのときの上記クロックパルス計数出力を入力信
号のＡ／Ｄ変換データとする構成において、基準信号が
入力信号を超過したとき上記コンパレータから発せられ
る信号によって基準信号と入力信号との差が所定値以上
になるように制御する制御手段を設けたＡ／Ｄ変換回路
。The clock pulses are counted, and the counted output is D/A converted and applied to the comparator as a reference signal.The input signal to be A/D converted is applied to the comparator and compared with the reference signal, and the reference signal is input. In a configuration in which a point in time when the reference signal exceeds the input signal is detected and the clock pulse count output at that time is used as A/D conversion data of the input signal, the reference signal is determined by the signal generated from the comparator when the reference signal exceeds the input signal. An A/D conversion circuit provided with a control means for controlling the difference between the input signal and the input signal to be equal to or greater than a predetermined value.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1983130034U JPS6037938U (en) | 1983-08-22 | 1983-08-22 | A/D conversion circuit |
| KR1019840004625A KR900000488B1 (en) | 1983-08-22 | 1984-08-03 | Analog / Digital Conversion Circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1983130034U JPS6037938U (en) | 1983-08-22 | 1983-08-22 | A/D conversion circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6037938U true JPS6037938U (en) | 1985-03-15 |
Family
ID=15024503
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1983130034U Pending JPS6037938U (en) | 1983-08-22 | 1983-08-22 | A/D conversion circuit |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPS6037938U (en) |
| KR (1) | KR900000488B1 (en) |
-
1983
- 1983-08-22 JP JP1983130034U patent/JPS6037938U/en active Pending
-
1984
- 1984-08-03 KR KR1019840004625A patent/KR900000488B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR900000488B1 (en) | 1990-01-30 |
| KR850002183A (en) | 1985-05-06 |
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