JPS6037739A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6037739A JPS6037739A JP14690383A JP14690383A JPS6037739A JP S6037739 A JPS6037739 A JP S6037739A JP 14690383 A JP14690383 A JP 14690383A JP 14690383 A JP14690383 A JP 14690383A JP S6037739 A JPS6037739 A JP S6037739A
- Authority
- JP
- Japan
- Prior art keywords
- package
- center
- ceramic package
- ceramic
- unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 13
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000000919 ceramic Substances 0.000 claims abstract description 25
- 238000000034 method Methods 0.000 claims description 10
- 238000003909 pattern recognition Methods 0.000 description 5
- 235000009852 Cucurbita pepo Nutrition 0.000 description 1
- 241000219104 Cucurbitaceae Species 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、半導体及び半導体集積回路の組立方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor and a method for assembling a semiconductor integrated circuit.
半導体及び半導体集積回路を搭載するセラミックパッケ
ージの組立に関して自動化された、組立設備が盛んに稼
動している。本発明は、この自動化された組立設備の中
で半導体集積回路の内部電極とセラミックパッケージの
外部導出電極とを細線によシ結線する自動ボンディング
組立の方法に係る。Automated assembly equipment for assembling semiconductors and ceramic packages containing semiconductor integrated circuits is in active use. The present invention relates to an automatic bonding assembly method for connecting internal electrodes of a semiconductor integrated circuit and external lead-out electrodes of a ceramic package using thin wires in this automated assembly equipment.
自動ボンディングはその装置の性能上、単能機と全自動
が有る。単能機は、与えられた、命令プログラムによシ
半導体集積回路の内部電極とセラミックパッケージの外
部電極と＝ｉＴＶモニター又は、投光機を用い、人間が
その位置全確認してから。Depending on the performance of the equipment, automatic bonding can be divided into single-function machines and fully automatic machines. The single-function device uses an iTV monitor or a projector to check the entire location of the internal electrodes of the semiconductor integrated circuit and the external electrodes of the ceramic package according to the given command program.
結線するものである。全自動は、パターン認識機能金持
たせたもので、人間全必要としない。この双方とも、半
導体集積回路を搭載したセラミックパッケージは、フＶ
−ム状に大全形成した搬送キャリヤ上に乗せてボンディ
ングステーションまで送られる。一方この方式以外に、
ステンレス鋼又は、アルミニウム材等の金属ブロックに
穴を形成したユニットキャリヤ方式が有る。製造ライン
には、パターン認識機能を持つ、全自動が設置され稼動
している。パターン認識機能は、与えられたプログラム
の認識部分をモニターにて走査し基準バ４−ンとのマツ
チングが行なわれるもので、セラミックパッケージ側に
、認識される目合せ用のパターンが必要となる。又、こ
の目合せ用パターンの位置は、プログラムによシ与えら
れ、その位置精度が要求される。セラミックパッケージ
の目＆セパターンは、タングステンメタライズ層に金め
っ＠を施こした、特殊形状である。このパターンは、セ
ラミックパッケージの製造段階に於て７００℃以上の焼
成が繰返されるため、パッケージの外形と同様に、位置
がずれる。この精度は、基準値に対し±０．１５〜０．
２５ｗｍである。It is for connecting wires. Fully automatic means that it has a pattern recognition function and does not require a human being. In both of these cases, ceramic packages equipped with semiconductor integrated circuits are
- It is placed on a transport carrier formed entirely in the shape of a bar and sent to a bonding station. On the other hand, in addition to this method,
There is a unit carrier method in which holes are formed in a metal block such as stainless steel or aluminum. The production line is fully automated and has a pattern recognition function. The pattern recognition function scans the recognition portion of a given program on a monitor and matches it with a reference bar, and requires a recognized alignment pattern on the ceramic package side. Further, the position of this alignment pattern is given by the program, and its position accuracy is required. The eyes and sepata of the ceramic package have a special shape made by gold-plating the tungsten metallized layer. Since this pattern is repeatedly fired at temperatures of 700° C. or higher during the manufacturing stage of the ceramic package, the position of this pattern is shifted in the same way as the outer shape of the package. This accuracy is ±0.15 to 0.0% with respect to the reference value.
It is 25wm.
従来この位置ずれに対応する必要性から、パターン認識
は、この基準値に対し±０．２〜０．３１の領域をパタ
ーンマツチング出来る機能？持たせである。この領域を
広げることは可能だが認識時間の遅れが生じ、生産上無
駄な時間を費すため極カシを乗せるフレームキャリヤ及
びユニットキャリヤ方式、ともに、セラミックパッケー
ジ全米せる穴の内寸法は、セラミックパッケージの外形
寸法公差を考慮した値となってｂる。即ち、七ラミック
パッケージの最大値が穴の内寸法である。これは、セラ
ミックパッケージの外形寸法公差範囲内に穴の内寸法が
ないとセラミックパッケージのロフト間の差により、フ
レーム及びユニットの穴に入らないパッケージが生じる
恐れがあるためである。この外形寸法公差は、前記同様
０．１５〜０．２！ｌｕ１ｍである。フレーム及びユニ
ットで搬送する方式では、前記穴にセラミックパッケー
ジ全入れ、その穴壁又は、位置決め治具によシ外形を利
用して位Ｒｋ決める。従ってセラミックパッケージの目
合せパターンの位置は、基準値に対して、最悪０．３〜
９．５１１１のずれを生じるため、認識エラーが発生し
ていた。Conventionally, due to the need to deal with this positional shift, pattern recognition has a function that can pattern match an area of ±0.2 to 0.31 with respect to this reference value. It's a chore. Although it is possible to expand this area, there will be a delay in recognition time, and wasted time in production.For both frame carrier and unit carrier methods, the internal dimensions of the holes that are placed in the ceramic package are The value takes into consideration the external dimension tolerance. That is, the maximum value of the seven ramic packages is the inner dimension of the hole. This is because if the internal dimensions of the hole are not within the tolerance range of the external dimensions of the ceramic package, there is a risk that some packages will not fit into the holes of the frame and unit due to the difference between the lofts of the ceramic packages. This external dimension tolerance is 0.15 to 0.2 as above! It is lu1m. In the method of transporting using a frame and a unit, the entire ceramic package is inserted into the hole, and the position Rk is determined using the hole wall or the outer shape of the positioning jig. Therefore, the position of the alignment pattern of the ceramic package is at worst 0.3~
A recognition error occurred due to a deviation of 9.5111.
本発明は、これら従来の認識エラーによる、設備稼動率
の低下を無くし安定した作業条件を作りだす方法全提供
するものである。The present invention provides a complete method for eliminating the drop in equipment operating rate due to these conventional recognition errors and creating stable working conditions.
本発明は、セラミックパッケージの位置決め精度を向上
させるため、ユニットキャリヤとの位置決め方法を改善
したものである。即ち、本発明の特徴は、セラミックパ
ッケージの寸法公差に於て変動の少ない中央部に穴又は
溝を設ける又、ユニットキャリヤ方式を採用しユニット
上面に、パッケージの穴又は溝に対応する突起を設けた
事によシ、セラミックパッケージの位置を決めるための
製造方法である。The present invention improves the method of positioning the ceramic package with the unit carrier in order to improve the positioning accuracy of the ceramic package. That is, the features of the present invention are that a hole or groove is provided in the center of the ceramic package where there is little variation in dimensional tolerance, and that a unit carrier system is adopted and a protrusion that corresponds to the hole or groove of the package is provided on the top surface of the unit. This is a manufacturing method for determining the position of the ceramic package.
以下に図面を用いて本発明の具体的な実施例を説明する
。第１図に本発明を用いるためのセラミックパッケージ
の断面図を示す。第２図に、ユニットキャリヤの斜視図
を示す。Specific embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a cross-sectional view of a ceramic package for use in the present invention. FIG. 2 shows a perspective view of the unit carrier.
セラミックパッケージ１に設けられた穴４は、パッケー
ジの回転を防ぐために長方形の溝構造とする、長辺５ｍ
、短辺２瓢、深さ０．２ ｎａ＆である。The hole 4 provided in the ceramic package 1 has a rectangular groove structure with a long side of 5 m to prevent rotation of the package.
, the short side is 2 gourds, and the depth is 0.2 na&.
この溝は、セラミックパッケージ形成時、グリーンシー
ト状で、ポンチ押しによるものである。更にパッケージ
中心部の収縮量の少ない部分に設けている。パッケージ
に対しユニットキャリヤ６上面には、凸状にパッケージ
側の溝に、差し込める寸法で、突起７を設けている。前
記バスケージ及びユニットキャリヤの組合せにょシ基準
値の百合セパターンがパッケージの寸法公差のみで位置
決めが可能となるため、パターン認識エラーが生じ得な
い。パッケージ及びユニットキャリヤの組合せ公差は、
十０．０５鑓である。This groove is shaped like a green sheet and is formed by punching when forming the ceramic package. Furthermore, it is provided in the center of the package where the amount of shrinkage is small. A protrusion 7 is provided on the upper surface of the unit carrier 6 with respect to the package and has a convex shape and has a size that can be inserted into a groove on the package side. Since the standard pattern of the combination of the bus cage and unit carrier can be positioned only by the dimensional tolerance of the package, no pattern recognition error can occur. The combination tolerance of package and unit carrier is
It is 10.05 yen.
以上の説明で判る通シパッケージの外形を位置決めの基
準としていた従来の方法では、パッケージ形状が大型化
することにより、その公差は大きくなシ認識エラーは防
げないため、パッケージの収縮変動量の小さい中心部を
位置決め基準とすることが必要である。又本実施例には
説明しなかったが、パッケージ裏面中央部に、２個以上
の穴を設けることによっても同様な効果全得ることは言
うまでもない。In the conventional method, which uses the outer shape of the package as a reference for positioning, as shown in the above explanation, as the package shape becomes larger, the tolerance becomes larger and recognition errors cannot be prevented. It is necessary to use the center as a positioning reference. Although not explained in this embodiment, it goes without saying that the same effect can be obtained by providing two or more holes in the center of the back surface of the package.
第１図は本発明実施例に用いるセラミックバッケージの
断面図、第２図はユニットキャリヤの斜視図、である。
なお図において、Ｊ・・・・・・セラミック、２・・・
・・・半導体集積回路グイ、３・・・・・・外部リード
、４・・・・・・溝穴、５・・・・・・ボンディング細
線、６・・・・・・ユニット、７・・・・・・突起、で
ある。FIG. 1 is a sectional view of a ceramic package used in an embodiment of the present invention, and FIG. 2 is a perspective view of a unit carrier. In the figure, J...ceramic, 2...
... Semiconductor integrated circuit guide, 3 ... External lead, 4 ... Slot hole, 5 ... Bonding thin wire, 6 ... Unit, 7 ... ...It is a protrusion.
Claims (2)
、セラミックパッケージの主面と対向する面の中央部に
溝又は、複数の穴を設け、前記溝又は、穴に対する。突
起を設けた搬送ユニットに前記パッケージを乗せワイヤ
ーボンドをすることを特徴とする、半導体装置の製造方
法。(1) In a method for assembling semiconductors and semiconductor integrated circuit devices, a groove or a plurality of holes are provided in the center of a surface facing the main surface of a ceramic package, and the grooves or holes are connected to the grooves or holes. A method of manufacturing a semiconductor device, comprising placing the package on a transport unit provided with a protrusion and performing wire bonding.
が矩形又は円形で、対向する搬送ユニットの突起もそれ
に対応した形状のものを用いること全特徴とする特許請
求の範囲第（１）項記載の半導体装置の製造方法。(2) The hole provided in the center of the ceramic package has a rectangular or circular shape, and the protrusion of the opposing conveyance unit has a corresponding shape. A method for manufacturing a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14690383A JPS6037739A (en) | 1983-08-11 | 1983-08-11 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14690383A JPS6037739A (en) | 1983-08-11 | 1983-08-11 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6037739A true JPS6037739A (en) | 1985-02-27 |
Family
ID=15418174
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14690383A Pending JPS6037739A (en) | 1983-08-11 | 1983-08-11 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6037739A (en) |
-
1983
- 1983-08-11 JP JP14690383A patent/JPS6037739A/en active Pending
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