JPS6035273A - Logic analyzer - Google Patents

Abstract

PURPOSE:To convert input data into a corresponding sign set to indicate by providing an input signal memory means, a means of setting a sign corresponding to the value of the input signal and a means of recognizing the correspondence of the memory contents to the input signal and replacing the signal value recognized with a corresponding signal. CONSTITUTION:The main program 2 and the related subprogram 3 operate in cooperation with a data structure 4 named ''DATA-BLOCK''. The name of the main program is ''MAIN'' and the name of the subprogram ''FACTOR''. In conjunction with these two PASCAL programs and the data structure thereof, three utility programs are made available from a library in execution to be called with a compiler of PASCAL while the programs MAIN and FACTOR are being compiled. They are a parameter passage routine 5, a multiplication routine 6 and a check routine 7.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a logic analyzer having a disassembly function, and more particularly to a logic analyzer having a function of converting and displaying input data into set corresponding symbols.

Compilers and assemblers that generate relocatable object code are very often used to develop executable code for systems that are primarily comprised of processing units. If you load such a program one after the other in succession, the list of traces obtained from the logic state analyzer will take a long time to recognize.
At worst, it's unrecognizable. Even a disassembler cannot replace arbitrary address signals with the corresponding symbols used in the original source program. Replacement requires knowing how the various software tools interact with each other and how to modify the relocatable object code to produce the final absolute value. Relating the traced events to the aggregated source program tabulation requires a significant amount of non-decimal operations.

The problem is further complicated when the hardware of the unmeasured system is known to be good, and what is being debugged is simply software. However, in many cases there may be bugs in the hardware and software. Therefore, regarding what actually happened,
It is particularly important to be able to analyze information based on traces.

This is because there are many cases where the program does not work as planned.
In this case, it is unwise to think of the trace as a hardware variant of the program list, but rather to think of the program list as a guide to understanding the trace.

Therefore, if the traces are not relocated, they can become extremely bothersome. It would be particularly desirable to replace the absolute values corresponding to traced addresses and operands with the symbols used in the original source program. Such symbols may refer to individual cases or to ranges of cases. It would be useful if it were possible to define symbols similar to those contained in the source program. It is also helpful to have source program line number references in traces or actual source program lines.

This is a great help in following the flow of the entire program.

The logic analyzer of the present invention also includes other improvements and troubleshooting related to the operation of the state machine. The state machine trace is 001001.010001,010
011, etc.), [-8IT-MEMCJ (wait for storage to complete), or STM (start storage cycle). There are many cases where it is possible. It would be desirable for a log, analyzer to be able to tabulate traces with such labels.

Each state in this list is either a label or a value associated with a label. In the latter case, there may be several states in the process, such as a storage read cycle.

The label RMCY indicates the initial state of the process. RMCY+
3 indicates the fourth state in the group labeled RMCY.

The logic analyzer's ability to incorporate source program symbols and lines into the trace list described here allows the logic analyzer to access the symbol table created by the compiler or assembler that generated the code (absolute or relocatable). This results from having the logic analyzer invoke the decisions made by the linker or relocation loader. Using this information, the logic analyzer can determine which symbols to use in the trace list through various testing processes.

Still other benefits arise from the ability to do this. A logic analyzer can extend or simplify the process of defining trace conditions.

The trace conditions determine the conditions for starting tracing, the information to be captured, and so on. According to the present invention, symbols of the source program can be used in trace conditions without knowing which absolute values are being captured. This is extremely useful since their absolute values are likely to change as bugs are found and fixed or as different variants of the software are developed and tested. However, a logic analyzer configured to make use of various symbol tables and loadmaps may be unable to do so simply because one or more programs are of a different length than before, or because the programs are loaded in a different order. No need to change trace conditions. The symbolic nature of relocatable trace conditions makes it unnecessary.

These principles can be extended to apply to logic analyzers performed on systems under test that incorporate storage management devices. In such a system under test, the relocatable address generated by the processing unit is a de facto address that is further modified in real time by the storage management unit as the processing unit operates. The modified address is the actual physical address sent to the storage device. Its value depends on the operating time conditions, which represent which parts of the storage device are assigned to which programs or tasks. This assignment is dynamic and generally cannot be predetermined as a fixed absolute offset that applies to relocation addresses that exist during operation. This relocated address is itself an offset from the relocated address generated by the assembler or compiler based on the relocation. Addresses managed by such storage devices have absolute values that result from dynamically off-centing a relocated value that is already offset by a fixed amount from the relocatable value appearing in the source list. Contains some.

The dynamic offsets described above are not discrete for processing within the system under test and therefore need not be opaque to the logic analyzer. Symbols representing various dynamic offsets can be defined to the logic analyzer. Then, given certain metrics (determined by the system under test) regarding maintaining a known knowledge of the offset flow, a logic analyzer constructed in accordance with an embodiment of the present invention will maintain a "true" state during operation. The absolute trace specifications of the trace can be continuously adjusted to cause traces to be traced according to user-defined symbols. Also, even traces related to programs whose locations in storage are dynamically determined during operation.
It is also possible to insert primitive symbols into the trace list.

The present invention will be explained below using examples.

FIG. 1 is a diagram showing the usage relationship in the logic analyzer of the present invention. The operation and effectiveness of the present invention will also be explained using FIG. 1 with reference to Appendix U.

Thereafter, the internal operation of the present invention will be described in conjunction with FIGS. 2-6.

Referring now to FIG. 1, a main program 2 and an associated subprogram 3 cooperate with a data structure 4 named r_DATA-BLOCKJ. In the case of this embodiment, both program 2 and subprogram 3 are Pascal (PASC)
AL) written in language. The name of the main program is rM
AINJ and the name of the subprogram is r FACT
It is ORJ. In relation to these two Pascal programs and their data structures, IN and FACT are sent to program M.
During compilation of the OR, there are three utility programs from the runtime library that are called by PASCAL's 21 compiler. The parameter passing routine 5 named PARAMETER is nυ1.71F'LY
A multiplication routine named 6 and a BOO that checks whether the specified bit is set in the specified word.
and routine 7 named LEANIN. For example, BOOLEANIN is used to evaluate the r IFJ statement of pAscAt. Below, we will briefly consider each of these program elements.

PAGE i OF APPI
ENDIX 8), PASCA of program MAIN
A source list in L language is shown. The program MAIN changes the data structure DATA BLOCK from O to 2.
Fill with factorials of consecutive integers up to 0. To do this, MAIN references an external integer array, conveniently named DATABLOC:. The input to the array is named INDEX, and the external FACTO
RAIAL (factorial) for a given integer n! will send it back. A simple FOR loop assigns the factorial of the value of an index to the value specified by that index. This is done for pointer values from 0 to 20.

Create the source list using the PASCAL language of the function subprogram FACTOR on page i of Dimension B (PAGE
i OF APPENOIX B) Subprogram failure C
The logical arrangement of TOR3 is detailed below. Programs MAIN2 and FACTOH3 are merely presented as part of the example situation workpiece. This includes FACTO
Contains confirmation of H operation or troubleshooting. More specifically, this example involves tracing the operation of FACTORI^L for three supply values.

For this, set the parameter NIJMBER to function 1'ACTO
Pass it to the old AL and use BOOLEANIN to write statement number 1
It includes items such as executing the IP instruction statement above 0 and summing it up using statement number 12. We mention these items because by examining the relevant portions of the trace with a logic state analyzer, we can observe what is actually happening during these important portions of the FACTORIAL. In short, the idea is to look at the inputs, the outputs, and some important points in between.

PAGE i OF APPEN
Annotated assembly language program DATE-BLO that satisfies external programs referenced in DIX C)
CK and gives the storage requirements for the integer array. DATE-
BLO (The active part of J is line number 21. Here, l
'-BSS21 The J command has 21 words, the first of which is related to the symbol ↑EBLOCK. The program DATE-BLOCK is a text file that can be assembled without generating executable code. The important thing it does in the current example is create a symbol table of all the assembly language labels in the program. One of them is DATE BLOCK. This will become important later. Important incidental matters are r.
B5521'' command still increases the program size value. This was later explained by D.
The simple expedient of making an ATE BLOCK appear to be 21 words long has the effect of having 21 words, even though those words do not contain code generated by the assembler.

To run the workpiece program, program M
Compile AIN2 and IIACTOR3 with a suitable PASCAL compiler, and DATE BLOCK4 with a suitable assembler (i.e. one of the machine languages of the processing unit in the system under test that executes the workpiece program).
must be assembled. Then all work must be rearranged and loaded.

The workpiece program can then be executed. During this execution, the logic analyzer can selectively trace all events or only selected events in response to the occurrence of certain predefined conditions (defined by trace conditions). (Here, we will select all events). The formant format tailors the logical organization of "address,""data," and "state" to the particular grouping of electrical signals that the logic state analyzer monitors. The obtained trace records the operation of the system near the conditions defined by the 1-race condition.

In the traces in each appendix, the triggering event is
The first trace is traced, and the large number of traces shows what happened following the 1-Riga event. But first, programs MAIN2 and FACTOR3 must be compiled and loaded. Appendix C is DAT^-
The result of assembling 4 into BLOC; has already been shown.

With this in mind, programs MAIN2 and FACT
Let us consider the tabulation of the extended compiler of Appendix RI and E obtained by compiling OR3. The ultimate goal of the example is to obtain a trace that follows the trace conditions. Here, I
Indicates when NDEX is assigned an integer value of 3, prepares to start tracing, and triggers when address equals FACTORIAL and state equals obcode (i.e., object code's first directive to FACTORIAL has been retrieved for execution). For such l-race conditions to be effective, the desired meaning must be translated into the appropriate combination of switch settings and key movements according to the syntactical characteristics of the respective logic state analyzer at hand. Not only must special (ie, absolute) addresses and numbers be provided for things like FACTORIAL and INDEX. Also FACTOR
If calls other routines, the user must be prepared to translate the addresses in those parts of the trace into meaningful locations in those called routines. To do this, the user uses the load map provided by the linker or relocation loader to find out which routine such an address is in, examines the compiler tabulation for that routine, and uses the trace to determine what behavior is occurring. We will follow what is expressed.

It is worth noting that several important items appear in the list in Appendix E in connection with these operations. The relocatable address for each word of the code generated by the compiler is written in the column marked LOCATION at the leftmost end of each list. SOURCE LIN
The column labeled IE) contains the line number of the PASCAL source list from which the associated machine command was issued. This source line is filled in with the resulting machine code shown below. Appendix page i (PAGE
i OF APPI! INDEX in row 26 of NDIX D) (This is MAIN(7) PASCAL
7 - Symbols defined by the user in their source program, such as (related to line 1 of the list) are the symbols INDε
The code uses χ. However, to use this INDEX, an execution definition is now required in the context of an executable machine language program. This is row 42 of page i in the appendix, r[1 with a relocatable hex address of 001On.
This is done using ssIJ. To run the example using the logic state analyzer, use INDI! X to M
0010 assigned to AIN compiled code
Must be replaced with the final relocatable value for 11. Something similar needs to be done to actually specify in a conventional trace specification what the absolute address of the first command executed in FACTOR is.

Utility program PARAMETER5, M
IJLTIPLY 6. and BOOLEANIN 7
call again.

The compiler generates code that uses these routines. PAGE OF APPENDIX E
NDIM E) (7) 14.22. See the JSM Directive on lines 38 and 38. The trace in this example includes such JSM and its related operations. This is not unreasonable; if something bad happens, the behavior of these or other utility routines should be examined to understand the nature of the failure.

Now, there are some devices in which the only utility of a runtime library is a relocatable machine code program whose meaning remains shrouded in mystery. A more advanced approach is to have the runtime library contain not only the relocatable code for each application, but also text files containing the source itself or extended edits. If this latter method is available, complete tracing makes each of the steps below at least less complicated than it would be without the practicality of such a library being executed by the compiler.

Appendices F, G, and 11 each contain three practical routines PARAMETER5, MIJLTIPLY6.
and an assembler list for BOOLEANIN7.

PAGE OF APPENDI
X I) is the program MAIN to DATA BLO
Until CK and library program-i, Mu BOOLEAN
This is a road map showing where each item from IN to MULTIPLY is loaded for execution. rP
The column labeled ROGRAM J contains the hexadecimal number at which each block of code begins.

The road map as listed in Appendix I is in Appendix J.

As the following example regarding K and L shows, this is essentially what is needed when tracing the flow of a program written with a relocatable list.

APPENDIX J tells the logic analyzer which probe has the address (Address).
Which one is the data line?
It is a style specification that tells which is the status line, etc. Each track name has a data label (
data label). 5ta
Data labels such as tus relate to multiple numerical values.

That is, two or more states exist. These various numerical values can also be represented symbolically and arranged in a symbol map. The format designation identifies the electrical logic polarity and threshold level that the signal is to follow.

APPENDIX K is a trace condition that defines the nature of the information that the logic state analyzer is to record while monitoring the execution of the workpiece program. RPC (
Although it is not particularly necessary to investigate the properties of the Binary Processor Chip, its command sequence,
Bus structure and internal configuration is US Special Fraud 4,180.854
checking ...

Now, the trace specifications in the appendix are lNl1[! The conditions are to start tracing when x is assigned an integer value of 3 and trigger when address equals FACTORIAL and state equals opcode.

To create a trace with this kind of meaning, do you need a certain clear number like "Enable after address =???"? It must be given in full. That is,
The user must navigate to r801211 J in the second line of the appendix. In this particular example r801
2+1 J can be found by noting that MAIN is initially loaded at 8002+1 and INDEX is at 1011 (relocatable) of MAIN. 800211 plus 1
011 equals 801211, and although this is not a formidable task in itself, such arithmetic
Stopping a race is necessary in so many places. Furthermore, it is extremely troublesome for the user to memorize 800211 and add/subtract it in hexadecimal notation. This is because as soon as the program changes (which can occur many times in the middle of a large program) new relocatable addresses appear that may be associated with completely different relocation criteria.

By the way, this is the general situation regarding APPENDIX L, which is the general situation regarding APPENDIX L, and this situation is APPENDIX
and is an abbreviated representation of the tracking obtained according to K.

r in the TRIGGER line of page i in the appendix
Note that there is 08013 LDA 8030J. Address 8013+ according to the road map in Appendix ■
1 is the starting point of the program FACTOR. line +00
4 has rJSM 806DJ, 806 in row +006
The address change to 011 continues. The meaning of 806011 is unclear just by looking at the trace in the appendix. 80
To find out the meaning of 60+1, first look at the road map (
By examining Appendix I), 806DI+ can be changed to 808F.
II, so the absolute address 806011
Is it PARAME? The hexadecimal value for I[ETER is 80
691! It is. Subtracting the hex value of load from the referenced location is 000411, which is PARAMETE
It is a relocatable location in R.

Now, look at line 49 in the assembly list of PARAMIETIER (page ii of inventory F), and find the location 00041.
1 to label PAR? Note that it is assigned to IETERENTRY.

Therefore, rJSM 806DJ is actually rJSM
PARA liver TERENTRY J.

Similar analysis applies to other address changes (JMP, JSM, etc.) and associated RETs.

Additional "map specifications" that the user supplies to the logic analyzer, generally done at the same time as the specifier provides the style and trace specifications, allow the logic analyzer to perform the necessary 1-race specifications by symbol. Relocations can be made, as well as non-relocations needed to create a trace list by symbol. APPIDIX M describes such a map specification with two symbol maps, each of which relates various symbols to a single value or a range of numbers. A single value can be uniquely defined in any base, and it doesn't care.
can be set. These numbers are absolute values and can be obtained from the roadmap or from the absolute list.

In the general case, a map specification may contain a collection of one or more such symbol maps. The reason why two or more symbol maps are necessary is that symbols generally represent logically incoherent phenomena such as addresses or states. For example, in the case of the RPC microprocessor described above, an address of zero represents the A register;
A zero state (constant control line paper length for a given selection of methods) represents a memory write cycle.

It is because the same value can have such different and independent meanings that it is necessary to divide the various types of symbols into separate collections. These collections generally represent functional divisions of the work represented by the various symbols entering and leaving the processing equipment. However, it is not absolutely necessary that the actual electrical signal itself be incoherent. What is needed is logical independence. For example, in BPC, the address and data lines are one and the same, but different types of information occur when they are different. The property of clock qualification (U.S. Patent 4,33
8.677) allows logic state analyzers to demultiplex logically separate but electrically common components in such situations.

Now referring specifically to APPENDIX M, in line 6 the symbol FACTORIAL is defined as a single unique absolute value 801311. Symbol 2 in the 7th line
is defined as a range from absolute value 22H to 0C211.

Any value that falls within this range will appear in the trace list relative to a reference location that may or may not fall within that range. It is convenient to select the start of the range, the end of the range, or 0 as the reference location. However, other values are acceptable and may be implemented. For example, the value in Z appears in the trace list as the symbol 2 plus or minus offset. However, here the offset relates to 4211. This feature is useful when the index is zero and the symbol is a compiler group or an array.

In line 8 of Appendix H, the symbol MAIN is defined as the absolute range 8002+1 to 801211 relative to the beginning of the range. In line 14, the symbol 5TACK is defined as the absolute range 0F9FO11 to 0FA1711, which relates to the end of the range.

And finally, on the 31st line, the symbol Error is 1×××B
(X means unrelated). binary 10
Any value in the range 00 to binary 1111 will simply appear as the symbol Error in the trace list.

In this embodiment, map specifications are set in one of two ways. In the first method, the user uses various software tools (assemblers, compilers, linkers, etc.) to generate information corresponding to the desired map specifications that can be operated on disparate equipment in various locations other than the system under test. The user then enters this information into the logic analyzer using a keyboard, etc. A second method of inputting map usage is for the user to prepare a properly formatted information table in a file on a mass storage medium. The map specification is then read into the logic analyzer by loading a disk or tape into the drive in the logic analyzer and instructing the logic analyzer to read the file at the appropriate moment to obtain the map specification. You will be able to communicate. Save the file to R3232 or I.
It can be transmitted over any suitable data link such as EEE488.

In conjunction with the addition of map specifications, it is desirable to make changes to related format specifications. The revised format specifications are attached in Appendix N (8 pages).
PBNI) IX N), which is somewhat different from the previous format specification shown in Appendix J. The difference is line 14,
It appears on lines 26 and 37. The meaning of the 17th line is that the default symbol map for the data label address is A.
It is a symbol map named ddress-. Other suitable symbol maps with other names are also possible, one of which can be used in place of Address- if desired.

The same general situation exists for state maps.

In line 37, the corresponding default map is identified as a map named 5tat-map. Other state maps with different names may exist as well.

Also, in line 26, the existence of the default data map is denied. The absence of such a map means that numerical values of data are simply represented by their absolute values in the trace list. In this example, the base of such an absolute value is abbreviated to hexadecimal when no specification exists to the contrary. Finally, specifying such an abbreviation map in a format specification merely selects which symbol map to use if the abbreviation condition is actually achieved.

Some special symbol maps can be specified (somewhere else), in which case no default state is obtained. This "somewhere else" is in the trace list, which is also now somewhat different from what appeared in Appendix K, for example. Now Appendix 0 (APPE
A modified trace specification is shown in NDIX O). It uses the same symbols for making measurements as specified in the Appendix. However, although the symbol map is not shown, the omission selection function in Appendix N is executed. Appendix 0 also shows another trace specification, which results in a completely different measurement. The sauce is included because it describes a symbol map that ignores the omissions and selections specified for a given data label in the Forman I specification. The important point is that the actual implementation of the symbolic map specification occurs in the modified I-Race specification.

Now compare the trace list shown on pages i and 11 of Appendix P (8PPBNDEX P) with the l-race list shown in the appendix. In particular, compare row →-004 of appendix P with row +004 of appendix P. In the former, the command is expressed as rJSM 806DJ, which is disassembled, while in the latter, r JSM PARAMETER→-000
4j, rPARAMETER+0004J
is the symbol r that appears in the source program for the parameter passed through routine 5.
Represents a relocatable location in the file named PARAI'1ETE11 corresponding to J. In this case, the map specification of the appendix stand has the symbol r PARAMETER-
Since ENTRY J is not entered, all references to numbers within the range 806911 to 808E are mapped to values related to the beginning of the range. Absolute value 806011
and the symbol PARAMETER-ENTRY are both in the fourth location of the range.

Refer again to the map specifications in Appendix H. Symbol failure CTOR
IAL is defined as an absolute value of 801311, and the symbol FACTOR is defined as 801311 to 803811.
The range is specified. FACTORIAL is thus a value within FACTOR. Now, let's look at the Trtgger line on page i of Appendix P. FACTORIA
The special value defined as L is expressed as FACTORIAL rather than as a value relating to the beginning of the range FACTOR, as is written, for example, in lines +001 to 005.

On page i of Appendix P, range 2 on the opposite side of the reference position is referenced by demapping in lines +066 and →-077. row +
075 has a definition range from 0F90Fll to 0FA171
Represents a reference to 5TACK demapped with respect to the end of 1.

This time, +005, +06 from the Trigger line in Appendix P.
6, →-075, and up to +077, and compare with the same line in the appendix. It is clear that the trace list in Appendix P is quite easy to use. Furthermore, in the trace list in the appendix, although the commands themselves have been disassembled, there are many operands and addresses whose connections to the symbols used to create the source program remain unclear. The 1-race list in Appendix P traces from line +065 to +074, and the trace is related to the program execution in the practical program BOOLEANIN7, and then the program execution is F
Move to the range labeled ACTOR and select FACT
The limitations of OR are in sharp contrast in that it is clear that FACTOR3 is known to correspond to user-written subprograms to the extent of executable code.

A trace list that is an improved version of Appendix P is possible in part through the map specifications included in the appendix. However, although the special map specifications are clearly improved, it is still necessary to add appropriate actions on the part of the user. That is, the user must key in the names of various symbols and their numerical values. This is in contrast to the environment surrounding Appendix Q.

Returning briefly to Appendix I again, one of the pieces of information regarding the tabulated output from the linker (i.e., the "roadmap") is on line 18: rabsolute &1ink-c.

m file name -WORKPIECE: E
Note that it is published as XAMPLE J. The meaning of this is r WORKPIECE: EXAMPLE
: The related file specified as link-symJ contains, among other things, a record of a range named "User Partition" and its associated starting and ending locations in the storage device. That's true. The names of the user partitions are the same as the file names of the various program partitions that are linked and loaded.

Now, return to the appendix, r,..., ltnk-sym file WORKPI
ECE: Consider the following commands: Define EXAMPLE...J.

This command is issued by the user as part of the map specification and in place of keying in the name of the symbol and its range. [
00, define ,..., The J instruction itself is not shown as part of Appendix Q, but rather the result of issuing that instruction. The result is "r 1 inked-files" information from lines 25 to 34 of Appendix O. This makes some extra information part of the map specification compared to what is available in the appendix. This extra information is that the starting and ending values for the range of symbols are given. This allows an address or operand to be outside any such range by simple means of expressing it in absolute value, while anything within such a range can be expressed as a particular unique symbol or within that range. It will later be possible to indicate in the trace list that it is represented as relating to the special symbol concerned.

Before considering the resulting trace list, a somewhat different trace specification must also be considered.

The user will at this point think of the trace specification in terms of the symbols INDEX and FACTORIAL. However, in the new Map Specification in Appendix 0, although the information is shown absolutely, these symbols are not shown clearly. That is, the symbol INDEX is MAIII: EXAMPLE
(Line 44 of the appendix) is declared global, and the symbol FACTORIAL is FAC
The global functionality is declared in a file named TOR:EXPLE (see line 45 of Appendix E). This absolute connection is established in the trace specification by the file name MAIN: Eχ^MPt, H and the symbol INDEX, the file name FACTOR: EXAMPLE and the symbol FAC:
It becomes clear by linking it with TORIAL.

See lines 2 and 4 of APPENDIX R.

Let us now consider the resulting trace list shown in pages i and ii of APPENDIX S.

First, look at the example of row +004. This line of tracing is now r FACTOR→-00002JSM PAIIA
METER-ENTRY, RAM [! TI! R...
,,J. The Uchiko land in Appendix S is simply P.
Instead of ARAMETER+ 0004, this time it's P^RA
METER-ENTI? This is expressed as Y. This is based on inspection of the files created when assembling PARAMIETER:EXAMPLE. The actual complete specification of this file is PARAMIETER:
EXAMPLIE: asmb-sym. This is specified by a loose operating system that manages files and operates compilers, assemblers, linkers, etc.rfHename: user id
: Represents the rules for file type J.

Following the JSH operand <rPARAMETIEI'
lJ refers to the complete file specification. That is JSH
Identifies the file used to symbolically represent the operands of . However, the display device is limited to 80 columns, and the user can also use the following I” name: user
id: Since the rules for typeJ are likely to be recognized, it is generally a good compromise to just give the name part.

In trace lists such as Appendices P and S, the overall value (
It looks at the symbols (in the files used by the linker) from the state analysis resulting from the logic state analyzer. File HORKPIEcrs included in map usage for trace list 5 in Appendix S:
Due to the comprehensive nature of the information in EXAMPLE (7), the operation to find the absolute value of the symbol can be performed on all addresses and operands.

See, for example, Appendix S, line +006. It is simply r,
,,,PA)IAMETER+ 00004 STA
PARAM, ETER+0000. ,,,, instead of J, r,,,,PAl? llMnTl1tR-ENTR
Y, STA DOPEVBCTOR, PARAMIE
It is expressed as TER,...,J.

As mentioned in connection with Appendix S, once you have the ability to inspect a source file for symbolic names, you can include in the trace list the line number of the original source program that produced the pending behavior that is captured by the trace. It will also be possible to enter it. For example, APPENDIX T
), it can be seen that the line from Trigger to +004 is related to line #8 of the source program. Such associations are limited to compiled source lines. Assembled source lines already generally have a one-to-one correspondence with trace lists due to their word-by-word or byte-byte nature and their similarity to executable object code. doing.

Appendix ↑ is the same trace list as before, with these original line numbers added. For example, line-002 of Appendix T
ni, r,,, #18 M^lN0O-L2. MAIN
It is written as JSM,...,J.

This means that line 18 of the primitive programming consisting of a file named MAIN is sent to the compiler caravel lN00.
This means that L2A was generated and an executable command JSM was issued. The following executable commands come from source located in a file named FACTOR.

Now let's consider APPENDIX U.

Here is a complete trace list for the example trace usage used throughout this course. Not only are line numbers included, but one copy of each associated source line is also included at the beginning of each block of different source line numbers.

FIG. 2 shows a block diagram of the logic analyzer of the present invention. FIG. 2 includes both a logic state analyzer and an emulator. As shown in FIG. 2, a logic state analyzer module 8 and an emulator module 9 are provided and cooperate and are supported by a host system 10.

The emulation bus Briprosensor generally corresponds to switching elements 13 and 14.

As shown in FIG. 2, logic state analyzer module 8 can receive data via clock probe bond 11 and data probe bond 12 or emulator module 9 connected to system under test 50. As shown in FIG. The invention operates on the data received by logic state analyzer module 8 in either case.

To facilitate this, logic state analyzer module 8 incorporates switching elements or multiplexers 13 and 14.

Host system 10 controls the operation of both emulator module 9 and logic state analyzer module 8. For this purpose, an operating system containing various instructions is encoded in the system ROM 15 and executed on the microprocessor unit 17. This control interacts with the user via keyboard 18 and display word ff 119 and includes concepts such as "soft keys,""soft front panel,""directedbranches," and the like. 22 is the I10 bus. If mass storage 20 is present, command files establishing certain commonly used facilities can be stored in labeled command files that can be recalled and executed at will. Similarly, the results of various measurements can be stored for later analysis and comparison.

Module 8 with emulator and logic analyzer
control includes the preparation of various tables of information, some of which resides in areas of system RAM 16, and some of which resides in modules 8 and 9. kept in place. These locations are responsive to store cycles on microprocessor address/data bus 21 initiated by microprocessor 17.

This allows the trigger recognition device 23 and the memory recognition device 24 to be individually and selectively programmed by the user to perform the appropriate recognition task for a given measurement. These operations ultimately produce state data on state bus 26 that is stored in trace storage 25. This is the raw data of the trace list and will be formatted as described in Appendices P, S, T, and U.

Such stylization is due in part to system ROM 1 of host system 10 in the preferred embodiment shown in FIG.
This is done by various routines executed by the operating system that are coded in 5. This includes examining various tables and files of information that may be found in either system RAM 16 or mass storage 20. Much of this necessary information, as mentioned earlier, is generated when the user uses various software tools to compile, assemble, link, and load the various programs and data structures that are subject to the trace list. do.

Now what exactly is this information and appendix p, s.

Let us return to T, and how it is used to create the various trace lists drawn in U.

The appendix shows the general arrangement of the various files created during the generation, loading, and execution of the example program for the workpiece of FIG. Also shown are the parts of the appendix that are related to these files.

Figure 3 diagrammatically arranges the special types of data relevant to producing the non-relocated tabulations of Appendices P, S, T, and U, as well as the associated trace, format, and map specifications.

In particular, captured data 27 is what logic state analyzer module 8 will store in trace storage 25 . This is raw information that is meant to work in a way that is as useful as possible to the user and as easy to translate as possible.

This, in turn, is done by correctly translating certain trace symbols 32 that are classified as either software symbols 28 or analysis symbols 29.

Software symbols 28 are simply symbols that appear in various source programs and are passed through compilation and assembly. The analysis symbol 29 is a symbol that is necessary when the idea of operating the logic state analyzer module is to consider what has already been specified in programming. This embodiment shows the case of data labels that are related to the signal lines of the respective systems under test and can take various values. For example, the three lines may be called states, read, write,
It may have various absolute values indicating command fetch, etc. The various data labels can be associated with maps in which different values are given symbolic names. In addition, the analyzer can specify symbols that are relevant only for the analysis of a particular programming whose execution is being traced, or if the symbol cannot be added to the symbol map. would have to be added to the source. Adding them to the symbol map eliminates the need for editing, re-editing, reassembling, reloading, etc.

Data label 30 is defined by formant specification 34, while symbol map 31 is defined by map specification 33. Once these two specifications have been created, symbols that are either software symbols 28 or analysis symbols 29 can be specified in the trace specification 35 and then placed in the non-relocated trace list 36. Therefore, the combination of software symbol 28 and analysis symbol 29 is 1-
It's called race symbol 32.

Figure 4 shows trace specification 3 with corresponding absolute address.
5 is a flowchart of a process for replacing software symbols 28 in 5; Analysis symbols 29 can also be included in the trace specification, but their absolute values are obtained from the associated symbol map 31. A flowchart for this has been omitted. FIG. 5 is a flow diagram of the process of removing absolute values in the trace list produced by the logic state analyzer and replacing the absolute values with symbols according to the various l-race symbols of FIG. This flowchart shows the procedure for finding the various types of symbols defined.

If the user defines symbols in a symbol map from a collection of software symbols whose associated absolute values have associated other signals, then the analytic symbols are the symbols that are used in the trace list. This allows the user to rename software symbols during debugging without editing the source program and without re-editing, reassembling, and reloading.

The following applies to source line numbers and trace lists containing source lines as listed in Appendices T and U, respectively. That is, line numbers are generated by the compiler and appear in the =asn+b-sym file. The rows generally appear in their own columns in the list as if they were symbols, and can be extracted with an algorithm similar to that of the flowchart of FIG. especially,
When making small changes related to the positive (Yl!S) path through decision 37, processes 38 and 39 must be adjusted to provide line numbers if necessary.

If you also want the source line itself, process 3
8 also provides the source line.

The following considerations apply when the present invention is used in conjunction with a system under test incorporating a storage control unit. In such systems, the MMU intercepts the storage path between the processing unit and the storage device. No special consideration is required if the address probe of the logic analyzer is connected to a virtual address between the processing unit and the terminal.

The existence of a frontage cannot be discerned.

However, some special operations are generally required when the address probe is connected to a physical address between the MM[I and the storage device. First, the memory will generally adjust the address of the storage cycle according to an amount determined or selected by the operating system. This quantity may be the contents of several callable registers. The logic analyzer will have to monitor write operations to its registers to know the commands it is passing to the MMU. It then maps between the absolute values of the raw trace information and the available trace symbols, and in other directions between the symbols used for various trace, modality, and map specifications and their associated absolute values. On the other hand, there is a change in the relationship shown in Figure 3. In the case of the first mapping above, the preliminary subtraction creates a physical memory location.

As previously mentioned, the added amount will be provided to the controller and monitored by the logic analyzer to correspond to the previous command.

Another method of utilizing the present invention is that the files in the mass storage device of FIG.
It concerns a condition containing a lace image. Such a trace file does not even need to originate from the logic state analyzer module 8. The data therein may be collected under completely different circumstances and transmitted by means of removable recording media and suitable data links. Once in mass storage 20, such a file behaves according to the invention as if it actually came from trace storage 25.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an outline of a program used in the logic analyzer of the present invention. FIG. 2 is a block diagram of the logic analyzer of the present invention. FIG. 3 is a diagram showing the relationship between the trace specifications, format specifications, map specifications, and each symbol of the logic analyzer of the present invention. FIG. 4 is a flowchart for replacing symbols and absolute addresses in the logic analyzer of the present invention. FIG. 5 is a flowchart of the logic analyzer of the present invention when replacing the (-race symbol with an absolute value. 8: Logic state analyzer module 9: Emulator module. 10: Host system, 11: Clock probe bond, 12: Data probe pound, 15 Nijistem RO?
l, i6: System RA11. 17: Microprocessing device, IB; Keyboard, 19: Display device zO; Mass storage device, 23: MJ recognition device. 24: Memory recognition device, 25F) Race memory device. Procedural amendment 1. Incident display 1982 patent front box 63135
No. 3, Relationship with the case of the person making the amendment Patent applicant 4, Agent address: 9-1, Takakura-cho, Heoji City, Tokyo, No. 5, Date of amendment order: July 31, 1980 [Shipping date 3 Table 1]
1 absolutely (to 1n rl":, r Ih h -1'to";'z l
Table of contents of appendix GA...Main program source attached fiB...Recovery program source list C...Data block assembly list Appendix D...List of the main program developed by the compiler Appendix E...・List of decompressed program developed by compiler Appendix F...Parameter assembly list II Volume G...MULTIPLY assembly list Appendix H...BOOLlli:ANIN
) Assembly list (j record I... Linker load map (L I NK)
A LOAD MAP) Appendix J...Format specification Appendix K...Trace specification appendix...Trace list Appendix M...Map specification Appendix N...Format specification Appendix O...Trace with analysis symbol Specified appendix P
...Trace list with analysis symbols Q...Map specification appendix R with software symbols...Trace specification appendix S with trace symbols...Trace list appendix T with trace symbols ...Trace list with source line numbers and trace symbols Appendix U...Full trace list with source lines and trace symbols

Claims (1)

[Claims] a storage means for storing an input signal; a setting means for setting a symbol corresponding to a value of the input signal; a recognition means for recognizing that a signal value stored in the storage means corresponds to the signal; replacing means for replacing the signal value with the corresponding signal.