JPS6032393A - Method of producing multilayer circuit board - Google Patents
Method of producing multilayer circuit boardInfo
- Publication number
- JPS6032393A JPS6032393A JP14147083A JP14147083A JPS6032393A JP S6032393 A JPS6032393 A JP S6032393A JP 14147083 A JP14147083 A JP 14147083A JP 14147083 A JP14147083 A JP 14147083A JP S6032393 A JPS6032393 A JP S6032393A
- Authority
- JP
- Japan
- Prior art keywords
- layer material
- circuit board
- multilayer circuit
- inner layer
- adhesive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Laminated Bodies (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
工、 〔接衝分野〕
13 本発明は亀気概器、電子機器、通信機器、計算1
4機器等に用いられる多層回路板の製造方法に関す1、
るものである。[Detailed Description of the Invention] Engineering, [Contact field] 13 The present invention is applicable to mechanical instruments, electronic devices, communication devices, calculations 1
1. Regarding the manufacturing method of multilayer circuit boards used in 4 devices, etc.
It is something that
16〔背景技術〕
1□ 従来、多層回路板は内層材上に接着剤付金属箔、
8を重ねたり或は内層材上に樹脂含浸基材を介して19
片面金属張積積層板重ねてから積層成形して一体2o化
して得られるものであるが内層材と外層材との接着力が
比較的弱く特に加熱時の接着力が極度に低下する欠点が
あった。16 [Background technology] 1□ Conventionally, multilayer circuit boards have a metal foil with adhesive on the inner layer material,
8 or 19 on the inner layer material via a resin-impregnated base material.
It is obtained by stacking single-sided metal-clad laminates and then laminating them to form a 2O unit, but it has the drawback that the adhesive strength between the inner layer material and the outer layer material is relatively weak, especially when the adhesive strength is extremely reduced when heated. Ta.
[発明の目的〕
本発明の目的とするところは内層材と外層材との接着力
を向上させることにある。[Object of the Invention] An object of the present invention is to improve the adhesive force between the inner layer material and the outer layer material.
本発明は内層材表面を予じめ粗面化しておいてから接着
性材料を介して外層材と積層成形して一体化することを
特徴とする多層回路板の製造方法で以下本発明の詳細な
説明する。本発明に用いる内層材は金属張積層板、アデ
ィティブ積層板、フレキシブル積層板、金属ベース積層
板等のように表面に電気回路を形成することのできる電
気用積層板をベースとし表面に回路を有する材料全般で
特に限定するものではないが内服材表面を予じめ粗面化
しておくことが必要である。粗面化の程度も特に限定す
るものではないが好ましくは1〜15ミクロンの凹凸で
あることが望ましい。即ち1ミクロン米温では外層材と
の接着力が低下する傾向にあり、bミクロンをこえると
回路に損傷を与える傾向があるからである。粗面化方法
としてはパフ研磨、サンドブラスト研磨、サンダー研磨
等の機械的研磨方法や重クロム酸カリウム溶液等で化学
的に腐蝕させる化学的研磨方法等容れの方法でもよく又
、機械的研磨と化学的研磨の併用でもよく特に限定する
もの゛・ではない。接着性材料としては外層材か金属箔
の場合は金属箔に塗布された接着剤、外層材が片面金属
張積層板の場合は樹脂含浸基材が主として用いられるが
金属箔の場合に樹脂含浸基材を用いたり或は接着剤と併
用することも出来るので接着性材料、外層材共に通常用
いられるものをそのまま用いることができ特に限定する
ものではない。更に内層材は回路が片面に存在するもの
だけでなく回路が両面に存在するものにも適用すること
ができ加えて内層材を一層丈でなく複数層用い多層化す
ることもできるものである0積層成形としては油圧式プ
レス、マルチロール、細端ベルト、ドラム等で積層成り
しされ一体化するものである。以下本発明を実施例にも
とすいて詳細に説明する。The present invention relates to a method for producing a multilayer circuit board, which is characterized in that the surface of the inner layer material is roughened in advance and then laminated and molded with the outer layer material via an adhesive material to be integrated.Details of the present invention are as follows. Explain. The inner layer material used in the present invention is based on an electrical laminate that can form an electric circuit on its surface, such as a metal-clad laminate, an additive laminate, a flexible laminate, a metal-based laminate, etc., and has a circuit on its surface. Although the material in general is not particularly limited, it is necessary to roughen the surface of the oral material in advance. Although the degree of surface roughening is not particularly limited, it is preferable that the roughness is 1 to 15 microns. That is, if the temperature exceeds 1 micron, the adhesive force with the outer layer material tends to decrease, and if it exceeds b micron, the circuit tends to be damaged. The surface roughening method may include mechanical polishing methods such as puff polishing, sandblasting polishing, and sander polishing, or chemical polishing methods such as chemically etching with a potassium dichromate solution. It is not particularly limited, and may be used in combination with target polishing. In the case of the outer layer material or metal foil, adhesive applied to the metal foil is mainly used as the adhesive material, and in the case of the outer layer material being a single-sided metal-clad laminate, a resin-impregnated base material is mainly used. Since the adhesive material and the outer layer material can be used in combination with an adhesive, commonly used adhesive materials and outer layer materials can be used as they are, and are not particularly limited. Furthermore, the inner layer material can be applied not only to those with circuits on one side but also to those with circuits on both sides, and in addition, the inner layer material can be multilayered by using multiple layers instead of one layer. Lamination molding involves laminating and integrating using a hydraulic press, multi-roll, narrow-end belt, drum, etc. The present invention will be described in detail below using examples.
実施例1
厚さ1・2wxの両面銅張エポキシ樹脂積層板をベース
として両面に回路を形成して内層材とし次に該内層材表
面をサンドブラスト研磨して深さ7〜13 aの凹凸を
つけてからその上、下面に厚さ0.1−のエポキシ樹脂
含浸ガラス布を夫々2枚づつ介在させてから厚さ1.2
瓢の片面銅張積層板を重ね170℃、40%で60分間
加熱加圧して一体化し4層回路板を得た。Example 1 A double-sided copper-clad epoxy resin laminate with a thickness of 1.2 wx was used as an inner layer material by forming circuits on both sides, and then the surface of the inner layer material was sandblasted to form irregularities with a depth of 7 to 13 a. After that, two sheets of epoxy resin-impregnated glass cloth with a thickness of 0.1 mm were interposed on the lower surface, and then two sheets of glass cloth with a thickness of 1.2 mm were interposed on each layer.
Single-sided copper-clad laminates of gourd were stacked and heated and pressed at 170° C. and 40% for 60 minutes to obtain a four-layer circuit board.
実施例2
厚さ1.2關のアルミペニス片面銅張板ヲベースとし銅
箔側に回路を形成して内層材とし次に該内層材表面を重
クロム酸カリウム溶液で処理して深さ2〜6箇の凹凸を
つけてからその表面に厚さ0.1閣のエポキシ樹脂含浸
ガラス布を1枚介在させてから厚さ0.035 trm
の銅箔を重ね170 Cs 40 ¥iで60分間加熱
加圧して一体化し2層回路板を得た。Example 2 A single-sided copper-clad aluminum plate with a thickness of 1.2 mm was used as the base, and a circuit was formed on the copper foil side to form an inner layer material.The surface of the inner layer material was then treated with a potassium dichromate solution to a depth of 2~ After creating 6 unevennesses, a piece of epoxy resin-impregnated glass cloth with a thickness of 0.1 mm was interposed on the surface, and then a thickness of 0.035 trm was created.
The copper foils were stacked and heated and pressed at 170 Cs 40 yen for 60 minutes to obtain a two-layer circuit board.
従来例
実施例1の内層材表面を粗面化せずに用いた以外は実施
例1と同様に処理して4層回路板を得た従来例2
実施例2の内層材表面を粗面化ぜずに用いた以外は実施
例2と同様に処理して2層回路板を得た〔発明の効氷〕
実施例1と2及び従来例1と2の多層回路板のit熟熱
時着力は第1表で明白なように本発明の多層回路板の性
能はよく本発明の多層回路板の製造方法の伐れているこ
とを確認した。Conventional Example 2 A 4-layer circuit board was obtained by processing the same as in Example 1 except that the inner layer material surface of Example 1 was used without roughening.Conventional Example 2 The inner layer material surface of Example 2 was roughened. A two-layer circuit board was obtained by processing in the same manner as in Example 2, except that no liquid was used. As shown in Table 1, it was confirmed that the performance of the multilayer circuit board of the present invention was well achieved by the method of manufacturing the multilayer circuit board of the present invention.
注
米 260 ℃の溶融ハンダ上にまき層間剥離する迄の
時間をみる。Pour rice onto molten solder at 260°C and observe the time until delamination occurs.
Claims (1)
着性祠料を介して外層材と積層成形して一体化7するこ
とを特徴とする多層回路板の製造方法。 8(2)粗面化が深さ1− ls ミクロンの凹凸であ
る9ことを特徴とする特許請求の範囲第1項記載の多1
o層回路板の製造方法。[Scope of Claims] 5(1) A multilayer circuit characterized in that the surface of the inner layer material is roughened in advance and then laminated with the outer layer material via an adhesive abrasive material 7 to be integrated. Method of manufacturing the board. 8(2) The polyurethane according to claim 1, wherein the surface roughening is unevenness with a depth of 1-ls microns.
A method for manufacturing an o-layer circuit board.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14147083A JPS6032393A (en) | 1983-08-01 | 1983-08-01 | Method of producing multilayer circuit board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14147083A JPS6032393A (en) | 1983-08-01 | 1983-08-01 | Method of producing multilayer circuit board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6032393A true JPS6032393A (en) | 1985-02-19 |
Family
ID=15292630
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14147083A Pending JPS6032393A (en) | 1983-08-01 | 1983-08-01 | Method of producing multilayer circuit board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6032393A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6247190A (en) * | 1985-08-27 | 1987-02-28 | 日立化成工業株式会社 | Manufacture of flat surface laminate body for multilayer circuit board |
JPS6334196A (en) * | 1986-07-29 | 1988-02-13 | イビデン株式会社 | Printed wiring board for ic card |
JPS63149192A (en) * | 1986-12-15 | 1988-06-21 | 日立マクセル株式会社 | Ic card and manufacture thereof |
-
1983
- 1983-08-01 JP JP14147083A patent/JPS6032393A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6247190A (en) * | 1985-08-27 | 1987-02-28 | 日立化成工業株式会社 | Manufacture of flat surface laminate body for multilayer circuit board |
JPS6334196A (en) * | 1986-07-29 | 1988-02-13 | イビデン株式会社 | Printed wiring board for ic card |
JPS63149192A (en) * | 1986-12-15 | 1988-06-21 | 日立マクセル株式会社 | Ic card and manufacture thereof |
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