JPS6031113B2 - semiconductor equipment - Google Patents

Description

Detailed Description of the Invention The present invention provides a structure in which minority carriers are injected into a P-type or N-type semiconductor region from one end thereof, and on the other hand, minority carriers are absorbed at the end of the semiconductor region. The present invention relates to an improvement of a semiconductor device having the following.

As such a semiconductor device, one having the following configuration has been proposed.

That is, as shown in FIG. 1, it has, for example, a P-type semiconductor region' and an N+-type semiconductor region 3 arranged in series to form a PN junction 2 at one end of the P-type semiconductor region. An electrode 4 is provided at the other end of the semiconductor region 1 opposite to the semiconductor region 3 side and at the end of the semiconductor region 3 opposite to the semiconductor region 1 side.
and 5 are ohmicly attached, so that those electrodes 4
If a bias power supply that is in the forward direction with respect to the PN junction 2 is connected between the electrodes 4 and 5, an on state is obtained between the electrodes 4 and 5, and from this state, a P voltage between the electrodes 4 and 5 is obtained.
A diode device in which an OFF state is obtained between the electrodes 4 and 5 when a bias power source is connected in the opposite direction to the N junction 2 is used as a diode device.

Further, as shown in FIG. 2, for example, a P-type semiconductor region 1
1, an N-type semiconductor region 13 connected to form a PN junction 12 at one end thereof, and an N-type semiconductor region 13 connected to form a PN junction 14 at the end opposite to the semiconductor region 11 side. It has a P-type semiconductor region 15 disposed in the opposite direction from the semiconductor region 13 side, and an N+ type semiconductor region 17 disposed in series so as to form a PN junction 16 at the end opposite to the semiconductor region 13 side. , electrodes 18 and 19 are ohmically attached to the end of the semiconductor region 11 opposite to the semiconductor region 13 side and the end of the semiconductor region 17 opposite to the semiconductor region 15 side, respectively. Another electrode 20 is ohmically attached to the semiconductor region 13 in the figure, so that the electrode 18 is connected between the electrodes 18 and 19.
For example, if a signal source with the electrode 20 side negative is connected between the electrodes 18 and 20 while a bias power supply with the positive side connected, an on state is obtained between the electrodes 18 and 19, and In such a state, if a bias source is connected between electrodes 18 and 19 with the electrode 18 side being positive,
A thyristor device having a configuration in which an OFF state is obtained between electrodes 18 and 19 is put into practical use as a thyristor device.

Incidentally, in the case of the semiconductor device shown in FIG. 1, when the above-mentioned on state is obtained between the electrodes 4 and 5, minority carriers 6 (in this case , electrons) are injected and the minority carriers 6 are absorbed into the electrode 4 side of the semiconductor region l.
When obtaining the above-mentioned off state, it is desirable that minority carriers 6 are not accumulated in the semiconductor region 1 in the sense that the off state can be obtained quickly.

Also, in the case of the semiconductor device shown in FIG. 2, when the above-mentioned on state is obtained between the electrodes 18 and 19, the semiconductor regions 15 and 13 are inserted into the semiconductor region 11 from the semiconductor region 17 side. The operation is based on a mechanism in which minority carriers 21 (electrons in this case) are injected through the semiconductor region 11 and absorbed into the electrode 18 side of the semiconductor region 11. When obtaining the above-mentioned OFF state, it is desirable that the minority carriers 21 are not accumulated in the semiconductor region 11 in the sense that the OFF state can be obtained quickly. From the above,
In the case of the semiconductor device shown in FIG. 1, in order to prevent minority carriers 6 from accumulating in the semiconductor region 1, as shown in FIG. A structure similar to that shown in FIG. 1 has been proposed, except that a P+ type semiconductor region 7 is inserted. In the case of the semiconductor device shown in FIG. 2, in order to prevent minority carriers 21 from accumulating in the semiconductor region 11, as shown in FIG. 2 has been proposed, except that a P+ type semiconductor region 22 is inserted.

However, even in the case of the semiconductor device shown in FIG. 3, as shown in FIG. 5, there is a built-in potential ◇ between semiconductor regions 1 and 7 based on the difference in impurity concentration between them. This prevents the minority carriers 6 injected from the semiconductor region 3 side of the semiconductor region 1 from passing through the semiconductor region 7 toward the electrode 4, thereby preventing the minority carriers 6 from accumulating in the semiconductor region 1. be lost.

Also, in the case of the semiconductor device shown in FIG. 4, as shown in FIG. 5, minority carriers 21 are accumulated in the semiconductor region 11 for the same reason as in the case of the semiconductor device shown in FIG.

Therefore, the present invention aims to propose a novel semiconductor device that prevents the accumulation of > several carriers in the semiconductor region as described above, and it is clear from the detailed description below. It will be. FIG. 6 shows an example of a semiconductor device according to the present invention. Parts corresponding to those in FIG. 1 are given the same reference numerals and detailed explanations are omitted. , has the same structure as that of FIG. 1, except that it is replaced with a metal layer or metal silicide layer 32 attached to form a Schottky acid compound 31 between it and the semiconductor region 1.

However, in this case, the potential barrier OB for majority carriers (holes in this case) of the Schottky junction 31 is
Diction ■＜Monkey.

g house. ...-------{1} Where, NA is the impurity concentration in the semiconductor region 1; Nv is the density of states in the valence band of the semiconductor region 1; A is the Richardson constant of majority carriers in the semiconductor region 1 , Jp is the current density of majority carriers flowing into the semiconductor region 1 from the Schottky junction 31 side, T is the absolute temperature during use, K is the Borckmann constant, and q is the absolute value of the amount of electron charge. .

The above is an exemplary configuration of a semiconductor device according to the present invention.

According to such a configuration, it has the same configuration as the case of FIG. Since the potential barrier JB for majority carriers (holes in this case) of 31 satisfies the condition of the above-mentioned equation '1), it functions as a diode device similar to the case of FIG. 1.

That is, the electrode 5 and the metal layer or metal silicide layer 3
When a bias power source that is forward directed with respect to the PN junction 2 is connected between
Since the right-hand side of the equation is obtained from equations (1) to (5) described later, an on state is obtained between the electrode 4 and the metal layer or metal silicide layer 32.

Furthermore, in such a state, if a bias power source with a direction opposite to the PN junction 2 is connected between the electrode 5 and the metal layer or metal silicide layer 32, the electrode 5 and the metal layer or metal silicide layer 32 An off state is obtained between the silicide layer 32 and the silicide layer 32.

Also, in the case of the semiconductor device according to the present invention shown in FIG.
Similarly to the case of FIG. 1, when the above-mentioned on state is obtained, minority carriers 6 are injected into the semiconductor region 1 from the semiconductor region 3 side, and the minority carriers 6 are transferred to the Schottky junction 31. It operates by a mechanism in which it is absorbed into the metal layer or metal silicide layer 32 through the metal layer.

However, in the case of the semiconductor device of the present invention shown in FIG. 6, the potential barrier for majority carriers in the Schottky junction 31? 8 satisfies the condition on the left side of equation (1} above, the conduction band of the semiconductor region 1 is bent downward at the end on the metal layer or metal silicide layer 32 side as shown in FIG. ing.

Therefore, when the above-described on state is obtained, the minority carriers 6 are effectively absorbed into the metal layer or metal silicide layer 32, and therefore, the edge of the semiconductor region 1 on the metal layer or metal silicide layer 32 side As shown in FIG. 7, the electron concentration is at or close to zero. Therefore, in the semiconductor device according to the present invention shown in FIG. 6, almost no minority carriers 6 are accumulated in the semiconductor region 1.
It has the following characteristics.

Incidentally, the potential wall ma with respect to the majority carriers of the Schottky junction 31.

If satisfies the condition on the right side of the above equation '1}, then
When the above-mentioned on state is obtained, the semiconductor region 1
The majority carriers flow from the metal layer or metal silicide layer 32 side without being unnecessarily restricted. Also,'
1) If the conditions on the left side of the equation are satisfied, as mentioned above,
The semiconductor region 1 has a conduction band that curves downward as shown in FIG. 7 at the end on the metal layer or metal silicide layer 32 side. This can be explained as follows.

That is, when the above-described on state is obtained, the potential barrier OB is removed from the metal layer or metal silicide layer 32 side.
The current density of majority carriers (holes in this case) flowing into the semiconductor region 1 beyond
The current density Jp of the majority carrier IJ flowing into the semiconductor region 1 from the metal layer or metal silicide layer 32 side is the potential barrier? A large number of carriers that can flow beyond B (in this case,
hole) maximum current density Jmax, Jp>Jmax
...{21 relationships,
And the maximum current density Jm arc is Jmpine: AT2e-g
Ichito B ---'31. Therefore,■
From the equation [3', the conditional expression Jp<AT2e-Zenzou...{4' is obtained, and by rewriting this, equation [4] becomes the same as the right-hand side of the above-mentioned equation '1'. potato.

g etc.・The conditional expression on the side is obtained.

Therefore, the potential barrier? If B satisfies the condition on the right side of equation '1' above, majority carriers will not flow into the semiconductor region 1 from the metal layer or metal silicide layer 32 side without being unnecessarily restricted. be.

Also, when the potential difference between the valence band of the semiconductor region 1 and the Fermi level is (EF - Ev), ? B>(EF-Ev
)...[By establishing the relationship 61, the conduction band at the end of the semiconductor region 1 on the metal layer or metal silicide layer 32 side can be bent downward as shown in FIG.

In this case, (EF-Ev) is EF-EV=V, where P is the hole concentration in the semiconductor region 1.

Increase. -Represented by '7l.

On the other hand, the hole concentration P is equal to the acceptor concentration in the semiconductor region 1, and therefore to the impurity concentration NA. For this reason,(
6. From the equation 7', we can obtain the conditional expression on the side of the same log poem as the left side of the equation 1' mentioned above.

Therefore, if the potential barrier JB satisfies the condition on the left side of the equation {1} described above, the conduction band of the semiconductor region 1 will be located at the end of the metal layer or metal silicide layer 32 side, as shown in FIG. It is curved downward.

Note that in practice, when the semiconductor region 1 is made of silicon, N
v=1.1×1p9c-3, A=(30 ampere/negative)・K2, and Jp is the majority carrier IJA passing through the metal layer or metal silicide layer 32 side of the semiconductor region 1. has a value smaller than the total current density J (ampere/earth), which is the sum of the current density and the current density of minority carriers;
In use, it is desirable that the majority carrier current density is at least an order of magnitude lower than the total current density, so the metal layer or metal silicide layer 32 has a
OB is...

■. 26, Increase --- Odd three times 9<? B<Qo2610g2
It is desirable that the material satisfies the condition of 7≦1 and --(9}).

Note that equation '9) is derived from equation '1) above, assuming that the current density of majority carriers is one order of magnitude smaller than the total current density, and J =
It was calculated as Jp×0.1. Also, in this case, N^ = 1 x 1 and 5 cm-3, and J
If p=ship/c, 0.2 clam V<OB<0.37e
It becomes V. For the metal layer or metal silicide layer 32 where OB satisfies the condition of formula (2), J = 100 ampere/
When NA=1 and 5-3, platinum, platinum silicide (B=0.2&V), palladium, etc. can be used.

Also, Fig. 10 shows that when N^=1×1 and 5ka-3,
? 7 is an actual measurement result of the forward voltage drop of the semiconductor device shown in FIG. 6 and the minority carrier accumulation time nS with respect to B.

From this result, in this case, OB is 0.2 clam V ~ 0.37
It is clear that by setting the voltage to eV, the forward voltage drop and the carrier accumulation time can be made sufficiently small. next,
Another embodiment of the semiconductor device according to the present invention will be described with reference to FIG. 8. Parts corresponding to those in FIG. 6 will be given the same reference numerals and detailed explanations will be omitted. The structure is similar to that of FIG. 6, except that a P-type semiconductor region 33 having a high impurity concentration is interposed between the semiconductor region 1 and the metal layer or metal silicide layer 32.

However, in this case, the thickness of the semiconductor region 33 is set so that the thickness of the semiconductor region 33 is smaller than the depletion layer at zero bias extending from the Schottky junction 31 toward the semiconductor region 33.
The thickness and impurity concentration are selected.

The above is the configuration of another embodiment of the semiconductor device according to the present invention.

According to this configuration, it has the same configuration as the case of FIG. 6 except for the above-mentioned matters, so detailed explanation will be omitted, but it has the same excellent features as the case of FIG. 6. have

Further, in the case of the semiconductor device according to the present invention shown in FIG. 8, there is a semiconductor region 33 with a high impurity concentration between the semiconductor region 1 and the metal layer or metal silicide layer 32. , molybdenum, chromium, tungsten, etc., can be used even if the material has a large potential barrier to majority carriers B when applied to the semiconductor region 1 to form a Schottky junction with it. It has the following characteristics.

Note that in the case of the configuration shown in FIG. 8, semiconductor regions 1 and 33
As shown in FIG. 9, the conduction band is curved in the same way as in FIG. It can flow through the tunnel effect without exceeding B. Therefore, in the case of the configuration shown in FIG. 8, the value of the equivalent potential barrier OB is changed from the value of Q (0<Q<1
) can be doubled to 4. Note that in this case, the semiconductor region 33
may have a thickness of 50 Å or less and an impurity concentration of 1 and 8 to 1 poc and 3. In addition, in the above,
Although the embodiment has been described in which the present invention is applied to a diode device, it can also be applied to a thyristor device as described above in FIG.
The present invention can be applied in accordance with the above, and in other words, P-type or N-type semiconductor regions (in the case of the above example,
Minority carriers (electrons 6 in the above example) are injected into the semiconductor region 1) from one end (in the case of the above example, the end on the semiconductor region 3 side), while the other end of the semiconductor region (in the case of the above example, the end on the semiconductor region 3 side) In this case, it is clear that the present invention can be applied to a semiconductor device having a structure in which minority carriers are absorbed on the side opposite to the semiconductor region 3 side.

However, in this case, if the semiconductor region is N type, in the above description, "Nv is the density of states in the valence band of the semiconductor region" should be read as "density of states in the conduction band", and accordingly, ``The conduction band of the semiconductor region is bent downward at the edge of the metal layer or metal silicide layer'' is replaced by ``The valence band of the semiconductor is bent upward at the edge of the metal layer or metal silicide layer.'' ”, it is a thing.

[Brief explanation of the drawing]

1 and 2 are schematic cross-sectional views each showing an example of a conventional semiconductor device. 3 and 4 are schematic cross-sectional views showing other examples of conventional semiconductor devices. FIG. 5 is an energy level diagram for explaining this. FIG. 6 is a schematic cross-sectional view showing an example of a semiconductor device according to the present invention. FIG. 7 is an energy standard diagram and an electron concentration diagram for explaining this. FIG. 8 is a schematic cross-sectional view showing another example of the semiconductor device according to the present invention. FIG. 9 is an energy level diagram for explaining this. FIG. 10 shows the structure of the semiconductor device shown in FIG. FIG. 7 is a diagram showing the relationship between the accumulation time and the voltage drop in the mark top direction with respect to B. FIG. 1, 3, 33...semiconductor region, 2...PN junction, 5
... Electrode, 6 ... Minority carrier, 31 ...
...Schottky junction, 32...metal layer or metal silicide layer. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10

Claims (1)

[Claims] 1. A semiconductor device having a structure in which minority carriers are injected into a P-type or N-type semiconductor region from one end thereof, and the minority carriers are absorbed at the other end of the semiconductor region. At the other end of the semiconductor region, a metal layer or a metal silicide layer is formed, depending on whether the semiconductor region is P type or N type, the semiconductor region is placed at the other end of the metal layer or metal silicide layer side. , a conduction band curved downward or a valence band curved upward, and a shottock junction is formed such that a majority of carriers flow into the semiconductor region from the metal layer or metal silicide layer side. A semiconductor device characterized by being attached to.