JPS6027951A - Dual calendar mechanism for computer systems - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a duplex calendar mechanism for a computer system.

[Problems with conventional technology]

As a basic problem for the entire system, in the calendar system targeted by the present invention, there is a possibility that the stoppage of the calendar mechanism may lead to the stoppage of the information processing system, and the system cannot supply calendar data in the event of a failure. It is undesirable for the data to be discontinuous, and the calendar mechanism is required to have high accuracy and provide data continuously.

One possible means of achieving the above-mentioned high reliability and continuity is to duplicate the calendar mechanism, but in this case, the duplicated calendars must always operate in synchronization. If there is a discrepancy between the two data, how much is the difference? How much is the correct calendar data? How much is the difference from the correct value? How much should be corrected in the information processing program based on the context? Many troublesome problems arise.

In a commonly used computer system equipped with a data bus, as shown in FIG. 1, a central processing unit 5. Main memory 4. Calendar mechanism 800 will be arranged, and if the calendar mechanism is duplicated, calendar mechanism 9 will be installed.
00 will be added.

When the basic form shown in Fig. 1 is made concrete by duplication, it becomes as shown in Fig. 2. That is, the calendar mechanism 1 in FIG.
2 have the same circuit configuration, and the central processing unit 5 always accesses either the calendar mechanism 1 or 2. Calendar mechanisms 1, 2 each include a bus interface 11.21 for connection with bus 3, and calendar circuits 12, 22. Clock generation circuits 14, 24. Failure detection circuit 13 consisting of a clock stop detection circuit, etc.
．． Consists of 23.

If a failure occurs in the regular calendar mechanism 1 in the normal duplex system shown in FIG. 2, the following will occur.

The failure detection circuit 13 of the calendar mechanism 1 outputs the failure notification signal 15.
In response to this, the medium heat treatment device 5 switches the access destination to access the preliminary calendar mechanism 2. In this case, since the calendars 12 and 22 are driven using independent clock generating circuits 14 and 24, the calendar data does not become continuous when switching is performed. One possible way to eliminate this drawback is to synchronize the two calendar mechanisms with one clock generation circuit.
In this case, when the clock stops, both calendar mechanisms stop, making duplication meaningless.

Furthermore, when obtaining calendar data from the central processing unit 5 side, it is desirable to be able to access it without being aware that the calendar mechanism is duplicated. Otherwise, undesirable problems may arise, such as the need for various complicated access procedures using software programs, and the time it takes for access.

[Purpose of the invention]

In view of the above circumstances, the present invention provides a central processing unit)
Calendar data with high reliability and continuity without having to be aware of which of the P-FP mechanism and the duplicated calendar mechanism is dominant or subordinate in case of a conflict. The purpose of this invention is to provide a dual calendar mechanism for creating a calendar.

[Key points of the invention]

Two calendar mechanisms, each equipped with a clock generation circuit and a calendar circuit, are provided in a computer system including a central processing unit, and both mechanisms provide calendar data from one of them to the computer system according to a predetermined procedure. In this case, one clock pulse line is provided in common for both mechanisms, and the clock pulse line is connected to the clock generation circuit of either one of the mechanisms. clock pulses are supplied from the respective mechanisms through respective gates, and each mechanism has a failure detection circuit for detecting a failure within the respective mechanism, and a failure detection circuit for detecting a failure within the mechanism. A switching circuit for controlling the gate is provided respectively, and each switching circuit normally opens the gate of one of the mechanisms and sends a clock pulse from the clock in the one mechanism to the clock pulse line. When the failure detection circuit in one mechanism detects a failure, it sends a signal to that effect to the switching circuit in the other mechanism to open the gate in the other mechanism and close the gate in one mechanism. This is a dual calendar mechanism for a computer system that provides certain highly reliable calendar data.

[Embodiments of the invention]

FIG. 3 shows an embodiment constructed using the present invention. The central processing unit 5 communicates with the calendar mechanism 6 via the bus 3.
Access 7. A transmission line for a switching signal 100 that determines whether one of the calendar mechanisms 6 and 7 is normally used or reserved, which is generated locally independently of the central processing unit 5, and the calendar mechanism 6.
, 7 is connected. A clock pulse signal 101 is sent from either one to the other, thereby synchronizing the calendar data between the two mechanisms so that the calendar data does not deviate from each other.

Furthermore, since the same address is assigned to each of the calendar mechanisms 6 and 7, when the central processing unit 5 accesses the data input bus interface 6 of both mechanisms shown in FIG.
1 open their mouths at the same time and accept and set the same calendar data. When the central processing unit 5 wants to read calendar data, both bus interfaces 61 open, but only the data access system is configured to allow the data to flow out.

FIG. 4 is a circuit diagram showing the inside of the calendar mechanism 6. The calendar mechanism 7 is also exactly the same.

A clock generation circuit 64 generates clock pulses for keeping time for the calendar circuit. The clock signal 103 depends on the output of the clock switching gate 67. The clock switching gate 67 is composed of a NAND circuit and outputs in the form of an open collector.

If the regular calendar mechanism is on the 6 side, the clock valid signal 1
06 is "1", and the clock valid signal 106 of one of the preliminary calendar mechanisms 7 is "0". Therefore, since it is the gate 67kINAND circuit on the side of the backup calendar mechanism 7, its output 101 is always '0' even if the output of the clock 64 on the side of the backup calendar mechanism 17 becomes ``0'' or 1.
1”.

On the other hand, the output 101 of the gate 67 of the regular calendar mechanism 6 is
Since the clock valid signal 106 is 1'', the clock 6
0", '1" according to the output of 4.

It pulsates as 0, 1"... Moreover, the common spare output 101 is connected to the open collector output, υ,
Since the output of the preliminary calendar mechanism is '1', the output 101 operates with the commonly used clock.

Calendar circuit 62 therefore operates synchronously with active reservists. If the regular calendar mechanism 6 fails, the failure detection circuit 63 issues a failure signal 105, and the calendar switching circuit 66 receives this and notifies the standby calendar mechanism by a signal 100.

This enables the reserve calendar mechanism. The calendar switching circuit 66 of the calendar mechanism 7 on the standby side sets the access valid signal 102 to 1" and the clock valid signal 106 to 1" due to the switching control signal 100, although the priority level initially set for its own circuit is low. 1” respectively, output in the valid direction.

FIG. 5 shows a calendar switching circuit diagram. In the normal state, the failure signal 105 is 0', and the calendar switching signal 105 is 0'.
is 1". Therefore, the output of inverter 662 is 1", and the output of inverter 663 is "0", so A
The output of the ND circuit 664 is 0.

On the other hand, the priority level setting switch 667 has a high priority level when the switch is off and a low priority level when the switch is on. The priority level here refers to the level at which calendar mechanism is to be enabled when both are in a normal state. If the switch 667 is off, the output of the AND circuit 665 is 1", and the output of the OR circuit 666 is '1'. Both the access valid signal 102 and the clock valid signal 106 are '1'.
1" is output.

Therefore, since the clock valid signal 106 is output, the self-rendering mechanism is operated by its own clock, and the clock signal 106 is output.
1, other calendar mechanisms are also synchronized with their own clock. Furthermore, the access valid signal 102 causes the bus interface 61 to become active. On the other hand, in the other calendar mechanism that does not have priority, the output of the AND circuit 665 is 0, so it outputs the access valid signal 102 and the clock valid signal 106, and also outputs its own clock and data output to the bus 3. do not have. Make sure that the internal circuits are operating normally.
The data just doesn't go out.

Next, a case where a failure occurs in the clock generation circuit will be explained.

On the regular calendar mechanism 6 side, the failure notification signal 105 is '1''
Then, the output of the inverter 662 becomes "o" and the output of the AND circuit 664 becomes ``0''. On the other hand, AND circuit 665
When the input is 0, the input from the inverter 662 is '0', the input from the priority level setting circuit 667 is '1', and the AND
The output of circuit 665 is 10''. Therefore, OR circuit 666
The output of ``θ'' is ``0'', and both the clock valid signal 106 and the access valid signal 102, which are finally output to the outside, are ``0''.
”. At the same time, the switching control signal 1o.

changes to ``0''. Since the clock valid signal 106 becomes 0, the output of the gate 67 made of a NAND circuit becomes ``1'' regardless of the voltage system.

In the calendar mechanism 7 on the standby side, the switching control signal 100 changes to 0, and since the priority level setting is low, the output of the priority level setting circuit 667 remains 0, and the self-failure signal 1
05 remains 0. Moreover, since the outputs of the inverter 661 are connected via an open collector, the signal 100 is kept at @Ojl. Therefore, the output of inverter 663 becomes 1, and the output of inverter 662 also becomes 1.
become.

Therefore, the output of AND circuit 664 becomes 1. The output of the inverter 662 is 1", and the priority level setting circuit 667
Since the output of is '0', the output of AND circuit 665 is 0. Therefore, the output of OR circuit 666 is '1'. In other words, the bus interface valid signal 102 is also 1"
, the clock valid signal 106 also becomes '1'.

FIG. 6 is a circuit diagram of the bus interface 61. Address decoder 611 decodes the address appearing on bus 3, and outputs address decode signal 107 when the address assigned to it comes. Calendar data is set from the central processing unit using address decode signals 1o7. According to the AND condition of the write signal 108, the AND circuit 614 opens, the buffer 612 receives data from the bus, and outputs the data to the calendar circuit 62. Calendar data is provided to the central processing unit using address decode signals 107. Read control signal 109. The three AND conditions of the access valid signal 102 are satisfied and the output of the AND circuit 615 is “1”.
Therefore, the output buffer 613 reads data from the calendar 62 and outputs the data to the lotus 3. By providing one clock for each calendar mechanism and using one clock for the two calendar mechanisms, both sides can always be synchronized, and when setting or reading calendar data, the two-power rendering mechanism can be operated with one address to synchronize the two calendar mechanisms. There is no need to be aware that the mechanisms are duplicated, and even if one of the mechanisms fails, there is no need to change any procedures on the central processing unit side, and the calendar switching control signal output can be connected between the calendar mechanisms with a single line. Furthermore, since they are connected by another P-clock pulse line, both power renderers can have the same circuit configuration, and the effect of reducing the number of control signals between the calendar mechanisms can be obtained.

[Brief explanation of the drawings] Figure 1 is a block diagram showing the configuration of the duplex calendar mechanism.
FIG. 2 is a block diagram showing the configuration of a conventional duplex calendar mechanism, FIG. 3 is a block diagram showing an example of a system configuration to which the present invention is applied, and FIG. 4 is an internal block diagram of the calendar mechanism.
FIG. 5 shows an internal circuit diagram of the calendar switching circuit, and FIG. 6 shows an internal circuit diagram of the bus interface circuit.

Claims (1)

[Claims] 1) Two calendar mechanisms each having a clock generation circuit and a calendar circuit are provided in a computer system including a central processing unit, and calendar data is provided to the computer system from one of the two mechanisms. In such a device, one clock pulse line for passing clock pulses that commonly drives the calendar circuits of the cylinder mechanisms is provided in common for the cylinder mechanisms,
Clock pulses are supplied to the clock pulse line from one of the clock generation circuits in each mechanism via the respective gates, and each mechanism is provided with a failure detection circuit for detecting a failure in the respective mechanism, and a cylinder mechanism. and a switching circuit that controls the gate in response to a failure detection signal from the failure detection circuit, and normally each switching circuit is used to open the gate of one mechanism and switch from the clock in the one mechanism. A clock pulse is sent to the clock pulse line, and when the failure detection circuit in the one mechanism detects a failure, a signal to that effect is sent to the switching circuit of the other mechanism to open the gate in the other mechanism. A dual calendar mechanism for a computer system, characterized in that the gate of one mechanism is closed at the same time. 2. In the duplex calendar mechanism according to claim 1, a computer system characterized in that the gate output is given in the form of an open collector output, and the output is supplied to the clock pulse wire. Dual calendar mechanism. 3) In the duplex calendar mechanism according to claim 1, the dual power render mechanisms are given the same address on the bus of the computer system, and by specifying the address, the calendar data of the cylinder mechanism is sent from the υ central processing unit. A dual calendar mechanism for a computer system, characterized in that the calendar can be set simultaneously. 4) In the duplex calendar mechanism according to claim 1, both power render mechanisms are given the same address on the bus of the computer system, and by specifying the address, the calendar data in either cylinder mechanism is transferred. A redundant calendar mechanism for a computer system, characterized in that the calendar can be output on a bus. 5) In the dual calendar mechanism according to claim 1, the failure signal of the failure detection circuit of each calendar mechanism is given in the form of an open collector, and one failure detection line receiving the output is connected to both mechanisms. A dual calendar mechanism for a computer system, characterized in that it is commonly provided in both systems.