JPS60263517A - Shift path control circuit - Google Patents

Abstract

PURPOSE:To improve the trouble detection rate by setting the first and the second shift paths consisting of registers and latches to the shift mode simultaneously and providing a means which protects latch contents while setting the second shift path to the shift mode independently. CONSTITUTION:When a shift mode signal 1 is logical ''1'', both of shift paths 111-1n1 and 211-2m1 are set to the shift mode. When the signal 1 is logical ''0'' and a latch scan signal 4 is logical ''1'', the shift path consisting of latches 21-2m is held in the shift mode because the signal 4 is impressed to shift mode terminals of these latches through an OR gate 30. However, individual latches hold respective set contents without taking in variation of inputs because an AND gate 40 is closed at this time. Thus, the trouble detection rate of circuits of input/output parts related to latches is improved.

Description

TECHNICAL FIELD The present invention relates to a shift path control circuit, and more particularly to a control circuit for a diagnostic circuit using a shift path consisting of a shift register and a latch.

Conventional technology Conventionally, a shift path circuit for the purpose of diagnosing inside a logic circuit chained registers and latches together in one shift path from shift-in to shift-out in one LSI (Large-Scale Integrated Circuit). However, when switching the logic circuit from shift mode to normal mode, the contents of registers and latches that were set by scan-in in shift mode are set or reset by normal mode, and their contents change. occurs.

Therefore, there is a high possibility that the content will change. This means that in order to set a value in the latch, you must not only set it in shift mode and scan in, but also preset the input conditions of the latch so that the state when the normal mode is set is the hold state. It will have to be done. However, if the input conditions of the latch are preset to be in the bold state, the latch will not be able to receive circuit changes on the input side of the latch, resulting in a significant drop in failure detection rate. That is, in the shift path, switching between the shift mode and the normal mode at the same time for the register and the latch has the disadvantage that the failure detection rate of the input section or output section circuit related to the latch decreases.

OBJECTS OF THE INVENTION The present invention provides a shift path consisting of registers and a shift path consisting of latches independently of each other, puts them into shift mode at the same time, and sets the shift path using latches independently in shift mode to protect the set contents of the latch. The purpose of the present invention is to provide a shift path control circuit that provides a shift path control circuit.

Structure of the Invention The shift path control circuit of the present invention is a control circuit for controlling a shift path circuit having a first shift path consisting of a plurality of registers and a second shift path consisting of a plurality of latches. The present invention is characterized by having means for simultaneously setting the second shift path to shift mode, and means for protecting the latch contents while independently setting the second shift path to shift mode.

In other words, when diagnosing shift paths, if you prepare separate shift paths for registers and latches, and set data in the latches by scan-in to detect failures,
In order to protect the contents set in the latch, the shift mode is maintained independently of the operating mode of the 1-no register, and when the input change of the latch is taken into the latch and read out by scan-out, it is set in the register operating mode. The circuit is configured to control the latch so as to increase the failure detection rate of each circuit of the input section and output section of the latch.

Example The present invention will be described in detail below using the drawings.

The figure is a circuit diagram of an embodiment of the present invention, showing only parts related to the present invention.

The registers 11-1n are cascaded to each other by connection lines 111-1n1 to form a first shift path. The scan-in of this shift path is input from pin 3, and the scan-out is output from pin 6.

The latches 21-2m are cascaded together by connections lm211-2m1 to form a second shift path. The scan-in of this shift path is input from pin 5, and the scan-out is output from pin 7. Register 11~
1n is controlled by pin 1 to switch between shift mode and normal mode, and when pin 1 is at logic 1, it is in shift mode and a shift path is formed from pin 3 to pin 6. A clock is supplied from pin 2 to the clock terminal of each register, and a shift operation is performed by this clock. This pin 1 shift mode signal is simultaneously OR gate 3
0 to each shift mode terminal of the latch. As another input to this gate, a latch scan-in signal is supplied from pin 4.

Further, the latch group can be supplied with a clock by the AND gate 40 only when the shift mode signal 1 is logic I11.

Although not particularly shown in the figure, it goes without saying that each register and each latch is connected to the input from the previous circuit and the output to the subsequent circuit, and is also supplied with set and reset inputs. It is something that exists.

In such a configuration, if both the shift mode signal 1 and the latch scan-in signal 4 are logic O, both shift paths are in normal mode, and the output of the front-stage circuit (not shown) is taken in at a predetermined timing and sent to the rear-stage circuit at a predetermined timing. Derive the signal.

When the shift mode signal is logic 1, both shift paths enter shift mode and sequentially take in the inputs of scan ins 3 and 5, respectively, according to the timing of clock signal 2.
Also, each signal in the register and the latch is scanned out to scan outs 6 and 7, respectively.

If the shift mode signal 1 is a logic 0 and the latch scan-in signal is a logic 1, this signal 4 is output to the OR gate 30.
is applied to the shift mode terminal of each latch through the latches, so the shift pass by this latch maintains the shift mode, but since the AND gate 40 is closed at this time and 0 is not supplied, each latch is The contents of each set are retained without incorporating changes in each input. The last scan-in signal 4 is a signal from an instruction in a diagnostic program, and holds logic 1 until a series of diagnostic operations of this program are completed.

Effects of the Invention By doing this, when testing the latch output section (later-stage circuit), it is possible to maintain the set contents while setting the latch shift path to the shift mode, regardless of the operation mode of the register shift path. In addition, when testing the latch input section (pre-stage circuit), it is possible to control the operation by matching the operation mode of the shift path with the register (by register), which improves the failure detection rate of the input/output section circuit related to the latch. can be improved.

[Brief explanation of drawings]

The figure is a circuit diagram of an embodiment of the present invention. Explanation of symbols of main parts 1...Shift mode control signal 2...Clock signal 4...Latch scan-in control signal 11 to 1n
...Register 21-2m ...Latch applicant Shin Yanagawa, agent for NEC Corporation, patent attorney

Claims (1)

[Claims] A control circuit for controlling a shift path circuit having a first shift path consisting of a plurality of registers and a second shift path consisting of a plurality of latches, the control circuit comprising:
A shift path control circuit comprising: means for simultaneously putting the second shift path into a shift mode; and means for protecting latch contents while independently putting the second shift path into a shift mode.