JPS60263443A - Gate array type large scale integrated circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a gate array type LSI, and particularly to the structure of a basic cell in a gate array type LSI.

In a gate array type LSI, the manufacturing process is advanced to the step of arranging a large number of basic cells consisting of gate circuits such as NAND and NOR having basic logic functions in an array on a semiconductor chip, and then forming an integrated circuit. In almost the last step of forming the SI, the wiring pattern is changed in various ways to meet the user's requirements, and the SI is completed and shipped.

Therefore, the design development and delivery period is short, and it is suitable for high-mix, low-volume production, so Noibora ECL, TT
Various products are being developed in L, CMOS, NMO5 technologies, etc.

Further, research and development on increasing the speed and integration of the 1° SI for use in high-speed computer systems, etc., is active, and research on compound semiconductors other than silicon, such as GaAs technology, is also becoming more active.

In such a gate array type LSI, the operating speed decreases as the wiring length increases and the number of fan-outs increases due to the increase in size, so there is a strong demand for the development of a means to prevent this decrease in operating speed. .

[Conventional technology]

The delay in operating speed in the above LSI is caused by the parasitic capacitance of the 7SI.

Generally, in a gate array LSI, one unit cell GA has a plurality of unit cells such as Gn, GC, G
ll, Gli, etc. are often connected to form a logic circuit, but in some cases, the operating speed of this circuit is parasitic to the wiring connecting Gli, GC, Gll, GF to cell f; The input capacitance (Cc Il+ Cc c + Cc D ) parasitic to the wiring capacitance MC7 and the capacitance of the subsequent cell
(Decreased by the load capacity, which is the sum of / GE.

Therefore, when the number of other unit cells connected to one unit cell, that is, the number of fanouts increases, the load capacity increases in proportion to the number, and the delay in operating speed becomes significant. .

In a conventional gate array type LSI, data 1, i.e.
i′L(!′I) is a potential with input parameters (gate length of input transistor, gate width, dark voltage, input terminal, etc.) based on the same 81 standards such that excellent performance can be obtained by itself. The cell is the basic cell, and this is the chip.''
Second, a structure arranged in an array was used.

FIG. 5 shows an example of a basic cell in gate array type I and SI of the conventional structure.
OR gate symbol diagram (a) 1 circuit diagram (hl and pattern) 2-side view tc+ is shown.

In these figures, Q,,G2. Q is a switching transistor, G4 is a load transistor, G1, G
2. G 3. G4 is a gate electrode made of polycrystalline silicon, A, , A2. A3 is a signal input terminal, D is an output terminal or output wiring made of polycrystalline silicon, and E is VO
O power source or upper layer ■ made of aluminum, etc. 0 power supply wiring, GND is a ground point or upper layer ground wiring made of aluminum etc., LD is upper layer output wiring made of aluminum etc., INS is isolation insulating film, S+, S+, + are source diffusion regions, D, 2D4 are drains The diffusion region, SD is the source train diffusion region where the output is -1'N, I]
A represents a contact ball with an aluminum wiring, and Hl represents a contact pole with an output wiring made of a polycrystalline silicon layer.

In the figure, an example of gate length I and gate width W is shown in parentheses.

As shown in the figure, in the conventional structure, the parameters of the input circuit, that is, the switching transistors Q1°G2. The gate length and gate width W of G3, the thickness of the gate 1 (not shown) and the insulating film, etc. are all formed as follows, so that each input terminal of each basic cell (gate) has a certain human force capacity. 1c6
．． It had a threshold voltage l−E V t +. (
In the case of shock I, the plane area of the joint is constant, so C
c, Vt+, so the input current during operation is also constant at I).

Therefore, when increasing the number of fan-outs in a conventional Chi-array type LSI, the load capacitance increases significantly because the multiple cells connected to the output of the previous stage cell also have large input capacitances similar to the previous stage cells. In circuit configurations with a large number of fan-outs, there has been a problem in that the operating speed is significantly reduced due to the increase in load capacity.

In particular, in the Schottky gate type 1.81, in addition to the increase in the load capacitance mentioned above, the output current of the previous stage cell, which is the sum of the input currents of the subsequent stage cells, also increases in proportion to the number of fans. Installation d1 unit [11. In the conventional structure in which basic cells are formed by arise.

[Problem that the invention seeks to solve]

The present invention constructs a logic circuit with a large fan-out number in a data 1 to array type LSI with a conventional structure in which various parameters of input circuits of basic cells are uniformly formed according to fixed design standards as described above. This was done in order to solve the problems of a significant drop in operating speed and a drop in performance due to malfunctions, etc.

[Failure to solve the problem]

The above problems can be solved by the gate array type LSI provided by the present invention, which includes a basic cell having a plurality of input circuits with different input parameters and a plurality of input terminals individually connected to the input circuits. .

[Effect]

That is, in the gate array type LSI of the present invention, in a unit basic cell, for example, a standard input gate capacitance similar to the conventional one (including input terminal capacitance in Schott Case 1) is used for one input signal. A first input circuit having a Schottky gate design and a first input terminal connected thereto, and a second input circuit having a Schottky gate design and a second input terminal connected thereto.
multiple input terminals with different parameters, such as a third input circuit designed to have a small input capacitance (including input current in Schottky gates) and a third input terminal connected thereto; A circuit and a plurality of input terminals individually connected to these are provided.

When configuring a circuit with a large fan-out number,
Select small terminals such as the second and third human power capacity input terminals as the input terminals of the plurality of cells connected to the output terminal of one cell, and connect these terminals to the output terminal of the previous cell. .

In this way, even when the number of fanouts increases, the increase in load capacity and load current of the cells in the previous stage can be suppressed to a small extent, so the operating speed of logic LSIs with circuit configurations with a large number of fanouts can be significantly increased. Deterioration and malfunctions are prevented.

〔Example〕

The present invention will be specifically described below with reference to embodiments shown in the drawings.

FIG. 1 is an equivalent circuit diagram (al) and a schematic plan view (b) showing one embodiment of the basic cell structure in a gate array type LSI of the present invention, and FIG. 2 is an equivalent circuit diagram (a) showing another embodiment.
) and a schematic plan view (bl). FIG. 3 is a schematic top view of a chip schematically showing an example of the wiring state when the number of fan-outs is large. The same reference numerals throughout the figures indicate the same objects.

Figure 1 shows an example of a basic cell in a gate array type LSI with a MOS structure in which three types of input capacitance can be selected by changing the gate lengths of the three switching transistors in the basic cell consisting of three NOR gates. It is an equivalent circuit diagram +al and a schematic plan view shown.

In the figure, Q + , Q 2 and Q 3 are switching transistors, C 4 is a load transistor, and C. ,
C2.

G z and G 4 are cases made of polycrystalline silicon.
Electrode, A, B. C is a signal input terminal, D is an output terminal or an output wiring made of polycrystalline silicon, E is a VOO power supply or an upper layer VDD power supply wiring made of aluminum, etc.
GND is a grounding point or an upper layer ground wiring made of aluminum or the like, L is an upper layer output wiring made of aluminum or the like, and INS is an isolation insulating film.

523 is a source diffusion region, I)+x. Da is a drain diffusion region, SD is a source/drain diffusion region that becomes output -1'N, HA is a contact pole with an aluminum wiring, and H is a contact hole with an output wiring made of a polycrystalline silicon layer. .

In this embodiment, the gate length and gate width W of the switching transistor are, for example, as shown in parentheses in the same figure (al), transistor Q: L=3 pm, W=10 pm, transistor Q2: L=3 pm, W. =5 pm transistor Q
3 is formed so that L=3 pm and W=3 μm.

Note that in the above embodiment, the value of the gate length I was kept constant;
The width of I does not necessarily have to be constant, and if it is necessary to increase the operating speed of the switching transistor, it is necessary to make the gate length shorter for those with a narrow gate width W.

Also in the same figure (in bl, upper layer wiring E, GND, T-
D+ and contact hole ■■. are drawn with dotted lines to indicate that they are formed by the mask slicing method according to the required specifications.

FIG. 2 is an equivalent circuit diagram (al and It is a schematic plan view (b).

In the figure, Q + , Q 2 , and Q 3 have standard gate lengths of 5 μm. A switching transistor Q1 having a gate width W-10 μm and a standard gate capacitance.
1+ Q. ,,Q,3 is a switching transistor whose gate length is reduced to about 3 μm to improve operating speed, and whose gate width W is reduced to about 5 μm to reduce gate capacitance.C4 is a load transistor. C2,c;,
, Ga, Gz, G+□, G1. are the other electrodes made of polycrystalline silicon, A, , A2. AJ is an input terminal with an input capacitance of 131.13□, B is an input terminal with a small human capacity, D is an output terminal or an output wiring made of polycrystalline silicon, and E is a V[lD@ source or aluminum ■The upper layer consisting of etc. D power supply wiring, GND grounding point or upper layer grounding wiring made of aluminum, etc.;
is an upper layer output wiring made of aluminum or the like, INS is an isolation insulating film, and SI is an isolation insulating film. S3゜S4. SIl, Ski are source diffusion regions, D+, D++, D4 are train diffusion regions, N
denotes an output note, IIA a contact hole with an aluminum wiring, and II a contact ball with an output wiring made of a polycrystalline silicon layer.

In the same figure (in bl, upper layer wiring E, GND, I-o
, and the contact hole It are drawn with dotted lines to indicate that they are formed by the mask slicing method in accordance with the required specifications.

MO3 structure gate array type L according to the present invention? St
As shown in the above two embodiments, a basic cell has an input terminal with a standard input capacitance and one or more input terminals with different input capacitances (often smaller input capacitance than the standard terminal). , are arranged in an array on the chip with a wiring area in between.

Then, like a normal gate array, the desired LSI is formed by connecting the wiring between the desired cells using the mask slicing method in accordance with the specifications requested by the user. In this case, a method is adopted in which an input terminal of a cell in a subsequent stage having a small input capacitance is connected to an output terminal of a cell in a previous stage, thereby preventing a decrease in the operating speed of the logic.

FIG. 3 is a partial top view of the chip schematically showing the above wiring state. In the same figure, C8 to C4, CII to C,...
C2 to C24 are basic cells, D is an output terminal, A is an input terminal with a standard input capacitance, B and C are input terminals with an input capacitance smaller than the standard, and L represents wiring.

In the above embodiments, the present invention has been explained with reference to the MO3 structure, but the present invention can also be applied to Schottky gate type gate array LSIs often used in GaAs technology and the like.

That is, in the Schottky gate type, by reducing the gate width and gate length of the switching transistor as in the above embodiment, the junction area is reduced and the input capacitance and input current are reduced.

Therefore, by using the present invention, the operating speed can be improved, and at the same time, the potential drop at the output node of the preceding cell is reduced, so that malfunction of the subsequent cell is also prevented.

〔Effect of the invention〕

As explained above, in the gate array type LSI having the basic cell according to the present invention, when constructing a circuit configuration with a large number of fans, - the input capacitance and input current of a plurality of subsequent cells connected to the output of the cell. This is extremely effective for improving the operating speed and preventing malfunctions of gate array type LSIs.

[Brief explanation of drawings]

2. Fig. 1 is an equivalent circuit diagram (a) and a schematic plan view fb) showing one embodiment of the basic cell structure in the gate array type LSI of the present invention, and Fig. 2 is an equivalent circuit diagram fal showing another embodiment. and a schematic plan view (bl), Figure 3 is a schematic top view of a chip that schematically shows an example of the wiring state when the number of fan-outs is large, Figure 4 is a schematic diagram of the circuit configuration of a gate array type LSI, and Figure 5 is a diagram of the conventional circuit configuration. A symbol diagram ta+, a circuit diagram Tbl, and a pattern top view fcl of an example of a basic cell are shown. In the figure, Q, , G2.C3 are switching transistors, C4 is a load transistor, G, , G2.G3, G
4 is a gate electrode made of polycrystalline silicon; B and C are signal input terminals, D is an output terminal or an output wiring made of polycrystalline silicon, E is a VDD power supply or an upper-layer vDD power supply wiring made of aluminum, etc., GND is a ground point or an upper-layer grounding wiring made of aluminum, etc.
L, upper layer output wiring made of aluminum etc., INS
is an isolation insulating film, Sl, S23 is a source diffusion region, I)
, 2D 4 is the drain diffusion region, SD is the output voltage -1N
ItA is a contact hole with an aluminum wiring, and H is a contact pole with an output wiring made of a polycrystalline silicon layer. (ρ) (6) 5 Figure 1 (%-k・fi%カ)
Figure 3 Hayabusa 5 Figure 41

Claims (1)

[Claims] A gate array type LS characterized by comprising a basic cell having a plurality of input circuits with different input parameters and a plurality of input terminals individually connected to the input circuits.
I.