JPS60263392A - Semiconductor memory circuit - Google Patents

Abstract

PURPOSE:To eliminate the limitation for the active period of a row address strobe signal by holding the potential of a row line via a pull-up circuit based on the frequency signal that compensated the drop of potential for the row line produced in a prescribed period. CONSTITUTION:A chip selection clock is produced from a chip selection signal generating circuit 5 as a frequency signal that compensates the drop of the row line potential while the row address strobe signal given from a row address strobe signal is kept active. Thus a monostable multivibrator 6 is triggered. A pulse PHI1 delivered from the trigger 6 is supplied to a pull-up circuit 4. Therefore the row line WLi selected every cycle when the chip selection signal is activated is charged to the circuit 4. Thus the potential level of the circuit 4 is kept. This can eliminate the limitation for an active period of the row address signal. As a result, a semiconductor memory circuit can work without giving any minitation to a page mode action.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor memory circuit, and particularly to a semiconductor memory circuit using an insulated gate field effect transistor.

(Prior Art) Semiconductor memories, especially random access memories (hereinafter referred to as AM), have been becoming faster, more dense, and more multifunctional, but MOS dynamic RAM in particular has In addition to normal read-write cycle and refresh cycle operations, page mode operation is now possible.This operation is mainly performed using a single address input terminal called an address multiplex. Given the 'r address input signal in time division, it
,yriCA8 (Column Address 5tr
MOS-D that uses address selection (obe)
It is defined as R and AM, and its operation timing is shown in FIG. In this page mode operation, after selecting a certain row address, the row address is fixed, digit addresses are continuously selected, and write/read operations are executed. Since it is possible to operate in cycles at high speed and read information can be retrieved after selecting a digit address, only the CAS access time can be used, and the memory access time can be effectively utilized at high speed.

FIG. 2 is a circuit diagram of a memory array and its row selection circuit portion of a conventional semiconductor memory circuit.

The memory array 1 includes memory elements Mij arranged in a matrix in the row and column directions, to which row lines WLi and column lines DLj are connected. A transistor Qi is connected to each row line WL+ as a row line activation driver circuit, and the drain of the transistor Qi is connected to a row activation circuit (not shown) to output a row line activation signal RA-i. The transistor Qi is connected to a NOR type row decoder 2 via a decoupling transistor Tif. The row decoder 2 receives a precharge signal Pxf from the RA8 clock signal generation circuit 3.

f FIG. 3 is a timing chart of signals during operation of the semiconductor circuit 0 shown in FIG.

When the ftAs signal is activated, the precharge signal Px
When this row decoder is selected, the output terminal of the preceding decoder 2 is precharged by and maintains a high level, and after the nodes of non-selected decoders become low level (GND level), the row line activation signal (LA) When becomes high level, node N
2. That is, the row line WLi becomes high level. but,
After the activation signal RA becomes high level floating, the level of the node N2 driven by the row activation signal RA similarly becomes a high level floating state, and )IAS
When the activation pulse width of the signal is long, its high level gradually attenuates due to leakage of the row line activation signal RA and leakage of the row line VJIri itself, and falls to the ground level.

Therefore, the page mode operation originally described in Hikari activates all the digits of one selected row line to perform the operation, but if the floating high level of the row line is Therefore, it is actually limited by the maximum value of the AS clock activation width, and is currently limited to 1.
A maximum of 0 μs is common, and if the memory is 64 kilobits, it will actually take about 32 cycles, making it impossible to operate all column lines on the same row line. Therefore, large restrictions are placed on the page mode operation, which could originally be used very effectively, and there are cases where the page mode operation cannot be used in the system. As the memory size continues to expand in the future, this tendency will become even stronger, creating the disadvantage that the page mode operation loses its meaning.

(Object of the Invention) The object of the present invention is to eliminate the above-mentioned drawbacks, and to select the row lines.
To provide a semiconductor memory circuit which can maintain this high level even if the RAS clock width is activated for a long time when it becomes a high level, and can operate without restricting page mode operation. It is in.

(Structure of the Invention) A semiconductor memory circuit of the present invention includes a memory array in which memory elements are arranged in a multi-IJ sock shape in all row and column directions and all row lines and column lines are connected, and each of the row lines is a pull-up circuit connected to the RAS signal and inputting a signal having a frequency of 5- to compensate for a decrease in the potential of the selected row line during the RAS signal activation period and holding the potential of the selected row line. configured.

(Example) Next, embodiments of the present invention will be described using the drawings.

FIG. 4 is a circuit diagram of the first embodiment of the present invention.

This embodiment includes a memory array 1 formed by arranging memory elements Miji in a matrix in the row and column directions and connecting row lines WLi and column lines DLj, and the row lines WLI to WL.
a pull-up circuit connected to each of the row lines WLi and inputting a signal having a frequency that compensates for a decrease in the potential of the selected row line WLi during the RAS signal activation period and holding the potential of the selected row line WLi; 4. In addition, 5
is the CAS clock signal generation circuit and the precharge signal PY
A one-shot pulse generating circuit 6 generates a pulse signal φl.

Next, the operation of this embodiment will be explained.

FIG. 5 is a waveform diagram of each signal during operation of the embodiment shown in FIG. 4.

6- During the activation period of the RAS signal, the CAB' signal generated by the CAs clock signal generation circuit 5 causes the one-shot pulse generation circuit 6 to fully generate the pulse signal φ1.

This pulse signal φ1 is sent to the pull-up circuit 4. The pull-up circuit 4 charges the selected row line WLii every cycle when the στ lower double signal is activated, and holds the potential level of the row line WLii.

In this way, even if the memory capacity is expanded and the number of rows increases, page mode operation is always guaranteed.

FIG. 6 is a circuit diagram of a second embodiment of the present invention.

In Fig. 6, 6' is synchronized with the RAS signal, and I(,
The signal φ is applied to the pull-up circuit 4 during the activation period of the Af9 signal.
2. The potential level of the selected row line WLi is held by all inputs. In the first embodiment, the pulse signal φl was synchronized with the δ1 clock signal, but it is not necessarily necessary to synchronize with the plane clock signal, and as long as it is synchronized with the 1lLA8 signal as in the second embodiment. good.

Although the above embodiment has been explained using a one-transistor type memory cell, it can be similarly applied to other memory cells.

(Effects of the Invention) As explained above, according to the present invention, (1) RA S
(2) Page mode operation is possible for the number of all row lines. (3) A semiconductor memory circuit having effects such as an expanded RAS clock signal low-speed operation margin can be obtained.

[Brief explanation of the drawing]

Figure 1 is a timing diagram of page mode operation in address-using memory, Figure 2 is a circuit diagram of the memory array and its row selection circuit portion of a conventional semiconductor memory circuit, and Figure 3 is the semi-integrated structure shown in Figure 2. 4 is a circuit diagram of the first embodiment of the present invention; FIG. 5 is a waveform diagram of signals during operation of the embodiment shown in FIG. 4; FIG. 6 is a timing diagram of signals during operation of the memory circuit. FIG. 2 is a circuit diagram of a second embodiment of the present invention. 1...Memory array, 2...Row decoder, 3...RAS clock signal generation circuit, 4.
Old... Pull-up circuit, 5... CAS clock signal generation circuit, 6... One-shot pulse generation circuit, 7... Oscillator, AXI~Axn...
・Address signal, DL1 to DLn・Old ・Column line, N1
．． N... Node, Px, PY... Precharge signal % Qi... Transistor (row line activation driver), KA... Row line activation signal,
Ti ・−・・−・Transistor (for decoupling)
, WL 1-WLn... row line, φl-...
...One-shot pulse signal, φ2 ...... signal. 9- Bodhisattva /I! I 1000 yen

Claims (1)

[Claims] A memory array comprising memory elements arranged in a matrix in the row and column directions and connected to row lines and column lines, and a row connected to each of the row lines and selected during the RAS signal activation period. 1. A semiconductor memory circuit comprising: a pull-up circuit that receives a signal having a frequency that compensates for a drop in potential of the line and holds the potential of the selected row line.