JPS60262259A - Shared memory access control method using multiple microprocessors - Google Patents

Abstract

PURPOSE:To attain an asynchronous access to a shared memory using plural microprocessors with a simple circuit by performing successively the selective connection controls while switching an address bus to the shared memory from plural microprocessors with the prescribed timing and forming a memory cycle of each processor to the shared memory. CONSTITUTION:For the 1st and 2nd CPU11 and 12, the address outputs A0-A12 out of those outputs A0-A15 are connected selectively to the address input part of a shared memory 13 via a data selector 14. The data buses led from both CPU11 and 12 are connected to the data input/output part of the memory 13 via data latch buffers 15 and 16 respectively. These buffers 15 and 16 supply the data fed from both CPUs to the memory 13 as they are when they write data to the memory 13 via both CPU11 and 12. Then both buffers latch the output data of the memory 13 as soon as the CS signal changes when the data is read out of the memory 13. The rest three pieces of address information out of the address outputs of the CPUs and the RW signal are supplied to the 1st and 2nd decoders 17 and 18 respectively. The outputs of both decoders start a timing circuit 19.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for controlling access to a shared memory by a plurality of microprocessors.

[Technical background of the invention and its problems] In recent years, electronic devices that use microprocessors to control various parts have been actively developed. For example, when multiple microprocessors control one shared memory, The method of controlling access from each microprocessor to the shared memory is important, and depending on the access control method, the problem arises that the circuit becomes complicated.

[Objective of the Invention] The present invention has been made in view of the above points, and provides a shared memory access control method by multiple microprocessors that can realize asynchronous access to shared memory by multiple microprocessors using a simple circuit. The purpose is to provide

[Summary of the Invention] This invention forms a memory cycle for the shared memory of each processor by sequentially and selectively controlling the connection of address buses from a plurality of microprocessors to the shared memory while switching them at predetermined timing. When an access request is made to the processor, each processor detects the access request and sends REΔD to the corresponding processor from the start of the access request until the end of the memory cycle for the shared memory of the corresponding processor.
The access control method is such that the Y signal is supplied, and when the processor enters a memory cycle for the shared memory while the READY signal is being supplied, the processor is permitted to access the shared memory.

[Embodiments of the invention] Embodiments of the present invention will be described below with reference to the drawings.

In FIG. 1, 11 is a first microprocessor (hereinafter referred to as CPUI), 12 is a second microprocessor (hereinafter referred to as CPU 2), and 13 is controlled by this CPU 111 and CPU 212. shared memory. Said CPU111 and CPU212
For example, is a general-purpose 8-bit CPtJ such as Intel's 8085A, with 16 address outputs AO to A15, 8 data inputs and outputs DO to D7, and clock outputs CLKI,
It is equipped with a READY terminal, etc. The shared memory 13
For example, as a guest employee, I have a part-time job every 8 days. Said CP
Uzll and CPU 212 have their address outputs AO~A
Thirteen of the fifteen AO-A 12 are selectively connected to the address input section of the shared memory 13 via the data selector 14. The data buses from the CPU 11 and the CPU 212 are each connected to a data latch buffer 15.1.
6 to the data input/output section of the shared memory 13.

The data latch buffer 15.16 is the 0PU11.
When data is written to the shared memory 13 by the CPU 1 and the CPU 212, the data from the CPU is supplied as is to the shared memory, and when data is read from the shared memory 13, the output data of the shared memory is changed by one signal. I'm trying to latch it at the same time.

Address information and read/write signals of the remaining three address outputs of the CPLJ 11 are supplied to the first decoder 17, and address information and read signals of the remaining three address outputs of the CPLJ 212 are supplied to the first decoder 17. ,
A write signal and the like are supplied to the second decoder 18.

The timing circuit 19 is activated by the outputs of both decoders 17 and 18.

The first and second decoders 17. ．． 18 and timing circuit 19 are constructed as shown in FIG. That is, address outputs A13 to A15 from the CPU 111 are input to the first decoder 17, and
Signals MEMRO and MEM WO produced by signal outputs RD, WR, 10'N11 are input. Further, address outputs A13 to A15 from the CPU 212 are input to the second decoder 18, and
Signals CMEMRO and CMEMWO generated by the signal outputs RD, WR, IO, . type flip-flop 2L 22.23.24 and a four-stage D type flip-flop 25.2 corresponding to the second decoder 1j3.
6.27.28 are provided, and the clock signal CLK1 from the CPU 11 is divided into 1/2 and 1/4 by the frequency dividing circuit 20, and outputted from the output terminals QA and QB, respectively, and the fourth stage flip 70 Tsubu 24.28
It is input directly to the T input terminal of. The signals are supplied to one input terminal of the QA input/output dual-type Nantes gates 29 and 30 of the frequency dividing circuit 20, respectively. The QB ratio output inverter 31 of the frequency dividing circuit 20 is input to the king input terminal of the flip-flop 22 in the second stage corresponding to the CPU 111, and the king input terminal of the flip-flop 23 in the third stage corresponds to the CPU 212. It is directly input to the T input terminal of the second stage flip-flop 26. Further, the QB ratio output of the frequency dividing circuit 20 is sent to the data selector 14.
It is supplied as an LECT signal.

The output of the first decoder 17 is passed through an inverter 32 to a first stage 7-lip 70-tub 2 corresponding to the CPU 1.
At the same time, the output of the second decoder 18 is inputted via the inverter 33 to the T input terminal of the first stage 7-lip 70-tube 25 corresponding to the CPU 2.

First stage flip 70 knob 21 compatible with the CPUI
The Q output is input to the D input terminal of the 7-lip 70 tube 22 at the next stage, and the output is supplied to the READY terminal of the CPU 111. The Q output of the flip-flop 22 is input to the D input terminal of the next-stage flip-flop 23 and is also supplied to the other input terminal of the Nant gate 29. The Q output of the knob 70 knob 23 is input to the D input terminal of the final stage flip 70 knob 24, and the
The output is input to the clear (OL> terminal) of the flip-flops 21 and 22 in the previous stage and the previous stage.

・1. ' The Q output of the final stage 7 lip-flop 24 is input to the clear (CL) terminal of the previous stage 7 lip-flop 23 together with the 5RESETO signal generated when the power is turned on. The Q output of the first stage flip-flop 25 corresponding to the CPU 2 is converted to the next stage's 7-lip 70-tub 2.
6, and its output is supplied to the READY terminal of the CPU 212. The Q output of the flip-flop 26 is input to the D input terminal of the flip 70 block 27 at the next stage, and is also supplied to the other input terminal of the Nant gate 30. Q of the flip-flop 27
The output is input to the D input terminal of the 7-lip flop 28 in the final stage, and the 0 output is input to the 7-lip flop 70 in the previous stage and the previous stage.
It is input to the clear (CL) terminal of knobs 25 and 26.

The Q output of the 7-lip 70-tube 28 at the final stage is input to the clear (C) terminal of the flip-flop 27 at the previous stage along with the 5RESETO signal generated when the power is turned on.

The output of the Nant gate 29 is supplied to the chip select terminal of the data latch buffer 715, and is also supplied to the chip select terminal 71 of the shared memory 13 via the gate 34, and one of the two gates 35 and 36. Supplied to the input terminal. The other input terminals of the gates 35 and 36 receive the MEMWO signal and the MEM
RO signal is input. The output of the gate 35 is supplied to the terminal W of the shared memory 13 via the gate 37, and the output of the gate 36 is supplied to the terminal σ of the shared memory 13 via the gate 1-38. . Further, the output of the Nant gate 30 is supplied to the chip select terminal σK of the data latch buffer 116, and is also supplied to the chip select terminal of the shared memory 13 via the gate 34, and the two-person gate 39. 4
0 to one input terminal. the three gates;
The CMEMWO signal and the CMEMRO signal are input to the other input terminals of 40, respectively. The output of the gate 39 is supplied to the terminal 1r= of the shared memory 13 through the gate 37, and the output of the gate 40 is supplied to the terminal -σ of the shared memory 13 through the gate 38.
T" is supplied.

Next, the operation of the apparatus according to the embodiment of the present invention constructed as described above will be described with reference to the timing chart shown in FIG.

From the CPLJ't11 to the timing circuit 19, the (
The lock signal CLKI is inputted as shown in (a), and the timing circuit 19 divides the clock signal CLKI into 1/2 and
As shown in FIG. 3(C), the frequency is divided into 1/4. 1
The QB ratio output inverter 31 of the frequency dividing circuit 20 whose frequency is divided by /4 generates an inverted signal @σ■ as shown in FIG. 3(d).
becomes.

The QB signal of the frequency dividing circuit 20 is sent to the data selector 14 at 5EL.
Since the ECT signal is supplied as an ECT signal, the address input sections AO to A12 of the shared memory 13 receive the address outputs AO to AI2 of the CPU 111 and the address outputs of the CPU 2 at the timing when the QB signal switches, as shown in FIG. 3(e). A.O.
-A12 are input alternately. However, first of all, the CPU
When the access to the shared memory 13 is started from 111 and the output from the first decoder 17 is inverted to low level at the timing shown in (f) of FIG. 3, the d output of the flip-flop 21 is also inverted to low level. , At this timing, as shown in FIG. 3(h), the RE of the CPU 511 is
A low level READY signal is supplied to the ADY terminal. Subsequently, after a short delay, the CPU 212 starts accessing the shared memory 13, and when the output of the second decoder 18 changes to low level at the timing shown in (0) in FIG. 3, the Q output of the flip 70 knob 25 is inverted to low level, and at this timing, as shown in (i) of FIG.
An EADY signal is provided. Now CPU111 and CPU
212 is in READY state in both cases CPU1
11, the access operation to the shared memory 13 is not started immediately because it is in the middle of the period in which the address of the shared memory 13 can be specified. After that, the QB multiplied signal of the frequency dividing circuit 2o, 0-1/<)u"゛6 paroruro1"<8"(-,7
At step 7, the 7-rip 70 knob 26 is first set, and the Q output of this flip 70 knob 26 is inverted to a high level as shown in FIG. 3(k). Moreover, at this time, CPU21
2 becomes a period in which the address of the shared memory 13 can be specified. During this period, the timing circuit 19 sends signals to the T-terminal, "1-terminal" and "7f" U terminal of the shared memory 13 as shown in (1) and (m) in FIG. , (n), when a signal is supplied, the CPU 212 first stores the shared memory 1.
An access operation for 3 is started, and data is written and read. Subsequently, when the QB multiplied signal of the frequency dividing circuit 20 is inverted to low level, the W signal obtained through the inverter 31 rises from the low level to the high level, so the flip-flop 26 is reset and the flip knob 22 is set. be done. Therefore, the Q output of the 7-lip flop 22 is inverted to a high level as shown in FIG. 3(j). Moreover, at this time, the period has changed to a period in which the address of the shared memory 13 can be specified by the CPU 111. Therefore, during this period, the timing circuit 19
When signals as shown in (+), (m), and (n) in FIG. 3 are supplied to the W, WT, and σT terminals of the shared memory 13 from
An access operation is started, and data is written or read. Further, by resetting the flip 70 knob 26, the signal to the READY terminal of the CPU 212 becomes high level and the READY state is released. Furthermore, the output of the second decoder 18 returns to the high level state at a predetermined timing.

Thereafter, when the QB multiplier signal of the frequency divider circuit 20 rises from low level to high level, the flip-flop 23 is set, and its Q output is inverted to low level as shown in (0) in FIG. .22 is cleared. As a result, the input to the READY terminal of the CPU 111 becomes high level and the READY state is released, and furthermore, at a predetermined timing, the first decoder 17
The output returns to high level.

In this way, the CPU 111. READY of CPU212
By using the terminals, the frequency divider circuit 20 and the flip-flops 21, 22, 23, 24, 25, 26, 27, .
CPU2 and C with a simple circuit configuration using 28
Even if the shared memory 13 is accessed almost simultaneously from the PU 2, there is no collision between the two cycles, and asynchronous access control of the CPLI can be reliably performed.

In the above embodiment, two CPUs control access to one shared memory, but the present invention is not limited to this, and three or more CPUs control access to a shared memory. It's okay.

[Effects of the Invention] As detailed above, according to the present invention, it is possible to provide a method for controlling access to a shared memory by a plurality of microprocessors, which can realize asynchronous access to a shared memory by a plurality of microprocessors using a simple circuit. It is.

[Brief explanation of the drawing]

The figures show an embodiment of the present invention, in which Fig. 1 is a block diagram showing the overall circuit configuration, Fig. 2 is a detailed circuit diagram of the decoder and timing circuit, and Fig. 3 is a timing chart showing the operation timing of each part. It is. 11... CPUL (first microprocessor),
12...CPU2 (second microprocessor),
13... Shared memory, 14... Data selector, 1
7.18...decoder, 19...timing circuit,
20... Frequency divider circuit, 21-28... Flip-flop. Applicant's agent Patent attorney Takehiko Suzue

Claims (1)

[Claims] Address buses from a plurality of microprocessors to the shared memory are sequentially and selectively controlled while switching at predetermined timing to form a memory cycle for the shared memory of each of the processors, and each processor accesses the shared memory. When a request is made, each processor detects the access request and supplies a READY signal to the corresponding processor from the start of the access request until the end of the memory cycle for the shared memory of the corresponding processor. A method for controlling access to a shared memory by a plurality of microprocessors, characterized in that when the processor enters a memory cycle for the shared memory while a signal is being supplied, the processor is allowed to access the shared memory.